2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * - Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * - Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * - Neither the name of the Altera Corporation nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include <linux/errno.h>
36 #include "cadence_qspi.h"
38 #define CQSPI_REG_POLL_US 1 /* 1us */
39 #define CQSPI_REG_RETRY 10000
40 #define CQSPI_POLL_IDLE_RETRY 3
43 #define CQSPI_INST_TYPE_SINGLE 0
44 #define CQSPI_INST_TYPE_DUAL 1
45 #define CQSPI_INST_TYPE_QUAD 2
47 #define CQSPI_STIG_DATA_LEN_MAX 8
49 #define CQSPI_DUMMY_CLKS_PER_BYTE 8
50 #define CQSPI_DUMMY_BYTES_MAX 4
52 /****************************************************************************
53 * Controller's configuration and status register (offset from QSPI_BASE)
54 ****************************************************************************/
55 #define CQSPI_REG_CONFIG 0x00
56 #define CQSPI_REG_CONFIG_ENABLE BIT(0)
57 #define CQSPI_REG_CONFIG_CLK_POL BIT(1)
58 #define CQSPI_REG_CONFIG_CLK_PHA BIT(2)
59 #define CQSPI_REG_CONFIG_DIRECT BIT(7)
60 #define CQSPI_REG_CONFIG_DECODE BIT(9)
61 #define CQSPI_REG_CONFIG_XIP_IMM BIT(18)
62 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
63 #define CQSPI_REG_CONFIG_BAUD_LSB 19
64 #define CQSPI_REG_CONFIG_IDLE_LSB 31
65 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
66 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
68 #define CQSPI_REG_RD_INSTR 0x04
69 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
70 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
71 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
72 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
73 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
74 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
75 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
76 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
77 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
78 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
80 #define CQSPI_REG_WR_INSTR 0x08
81 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
82 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
84 #define CQSPI_REG_DELAY 0x0C
85 #define CQSPI_REG_DELAY_TSLCH_LSB 0
86 #define CQSPI_REG_DELAY_TCHSH_LSB 8
87 #define CQSPI_REG_DELAY_TSD2D_LSB 16
88 #define CQSPI_REG_DELAY_TSHSL_LSB 24
89 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
90 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
91 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
92 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
94 #define CQSPI_REG_RD_DATA_CAPTURE 0x10
95 #define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0)
96 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1
97 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF
99 #define CQSPI_REG_SIZE 0x14
100 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
101 #define CQSPI_REG_SIZE_PAGE_LSB 4
102 #define CQSPI_REG_SIZE_BLOCK_LSB 16
103 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
104 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
105 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
107 #define CQSPI_REG_SRAMPARTITION 0x18
108 #define CQSPI_REG_INDIRECTTRIGGER 0x1C
110 #define CQSPI_REG_REMAP 0x24
111 #define CQSPI_REG_MODE_BIT 0x28
113 #define CQSPI_REG_SDRAMLEVEL 0x2C
114 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
115 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
116 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
117 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
119 #define CQSPI_REG_IRQSTATUS 0x40
120 #define CQSPI_REG_IRQMASK 0x44
122 #define CQSPI_REG_INDIRECTRD 0x60
123 #define CQSPI_REG_INDIRECTRD_START BIT(0)
124 #define CQSPI_REG_INDIRECTRD_CANCEL BIT(1)
125 #define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2)
126 #define CQSPI_REG_INDIRECTRD_DONE BIT(5)
128 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
129 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
130 #define CQSPI_REG_INDIRECTRDBYTES 0x6C
132 #define CQSPI_REG_CMDCTRL 0x90
133 #define CQSPI_REG_CMDCTRL_EXECUTE BIT(0)
134 #define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1)
135 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
136 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
137 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
138 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
139 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
140 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
141 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
142 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
143 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
144 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
145 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
146 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
147 #define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
149 #define CQSPI_REG_INDIRECTWR 0x70
150 #define CQSPI_REG_INDIRECTWR_START BIT(0)
151 #define CQSPI_REG_INDIRECTWR_CANCEL BIT(1)
152 #define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2)
153 #define CQSPI_REG_INDIRECTWR_DONE BIT(5)
155 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
156 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
157 #define CQSPI_REG_INDIRECTWRBYTES 0x7C
159 #define CQSPI_REG_CMDADDRESS 0x94
160 #define CQSPI_REG_CMDREADDATALOWER 0xA0
161 #define CQSPI_REG_CMDREADDATAUPPER 0xA4
162 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
163 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
165 #define CQSPI_REG_IS_IDLE(base) \
166 ((readl(base + CQSPI_REG_CONFIG) >> \
167 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
169 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
170 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
171 CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
173 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \
174 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
175 CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
177 void cadence_qspi_apb_controller_enable(void *reg_base)
180 reg = readl(reg_base + CQSPI_REG_CONFIG);
181 reg |= CQSPI_REG_CONFIG_ENABLE;
182 writel(reg, reg_base + CQSPI_REG_CONFIG);
185 void cadence_qspi_apb_controller_disable(void *reg_base)
188 reg = readl(reg_base + CQSPI_REG_CONFIG);
189 reg &= ~CQSPI_REG_CONFIG_ENABLE;
190 writel(reg, reg_base + CQSPI_REG_CONFIG);
193 void cadence_qspi_apb_dac_mode_enable(void *reg_base)
197 reg = readl(reg_base + CQSPI_REG_CONFIG);
198 reg |= CQSPI_REG_CONFIG_DIRECT;
199 writel(reg, reg_base + CQSPI_REG_CONFIG);
202 /* Return 1 if idle, otherwise return 0 (busy). */
203 static unsigned int cadence_qspi_wait_idle(void *reg_base)
205 unsigned int start, count = 0;
206 /* timeout in unit of ms */
207 unsigned int timeout = 5000;
209 start = get_timer(0);
210 for ( ; get_timer(start) < timeout ; ) {
211 if (CQSPI_REG_IS_IDLE(reg_base))
216 * Ensure the QSPI controller is in true idle state after
217 * reading back the same idle status consecutively
219 if (count >= CQSPI_POLL_IDLE_RETRY)
223 /* Timeout, still in busy mode. */
224 printf("QSPI: QSPI is still busy after poll for %d times.\n",
229 void cadence_qspi_apb_readdata_capture(void *reg_base,
230 unsigned int bypass, unsigned int delay)
233 cadence_qspi_apb_controller_disable(reg_base);
235 reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
238 reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
240 reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
242 reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
243 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
245 reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
246 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
248 writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
250 cadence_qspi_apb_controller_enable(reg_base);
253 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
254 unsigned int ref_clk_hz, unsigned int sclk_hz)
259 cadence_qspi_apb_controller_disable(reg_base);
260 reg = readl(reg_base + CQSPI_REG_CONFIG);
261 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
264 * The baud_div field in the config reg is 4 bits, and the ref clock is
265 * divided by 2 * (baud_div + 1). Round up the divider to ensure the
266 * SPI clock rate is less than or equal to the requested clock rate.
268 div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
270 /* ensure the baud rate doesn't exceed the max value */
271 if (div > CQSPI_REG_CONFIG_BAUD_MASK)
272 div = CQSPI_REG_CONFIG_BAUD_MASK;
274 debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
275 ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
277 reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
278 writel(reg, reg_base + CQSPI_REG_CONFIG);
280 cadence_qspi_apb_controller_enable(reg_base);
283 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
287 cadence_qspi_apb_controller_disable(reg_base);
288 reg = readl(reg_base + CQSPI_REG_CONFIG);
289 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
292 reg |= CQSPI_REG_CONFIG_CLK_POL;
294 reg |= CQSPI_REG_CONFIG_CLK_PHA;
296 writel(reg, reg_base + CQSPI_REG_CONFIG);
298 cadence_qspi_apb_controller_enable(reg_base);
301 void cadence_qspi_apb_chipselect(void *reg_base,
302 unsigned int chip_select, unsigned int decoder_enable)
306 cadence_qspi_apb_controller_disable(reg_base);
308 debug("%s : chipselect %d decode %d\n", __func__, chip_select,
311 reg = readl(reg_base + CQSPI_REG_CONFIG);
313 if (decoder_enable) {
314 reg |= CQSPI_REG_CONFIG_DECODE;
316 reg &= ~CQSPI_REG_CONFIG_DECODE;
317 /* Convert CS if without decoder.
323 chip_select = 0xF & ~(1 << chip_select);
326 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
327 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
328 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
329 << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
330 writel(reg, reg_base + CQSPI_REG_CONFIG);
332 cadence_qspi_apb_controller_enable(reg_base);
335 void cadence_qspi_apb_delay(void *reg_base,
336 unsigned int ref_clk, unsigned int sclk_hz,
337 unsigned int tshsl_ns, unsigned int tsd2d_ns,
338 unsigned int tchsh_ns, unsigned int tslch_ns)
340 unsigned int ref_clk_ns;
341 unsigned int sclk_ns;
342 unsigned int tshsl, tchsh, tslch, tsd2d;
345 cadence_qspi_apb_controller_disable(reg_base);
348 ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
351 sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
353 /* The controller adds additional delay to that programmed in the reg */
354 if (tshsl_ns >= sclk_ns + ref_clk_ns)
355 tshsl_ns -= sclk_ns + ref_clk_ns;
356 if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
357 tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
358 tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
359 tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
360 tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
361 tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
363 reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
364 << CQSPI_REG_DELAY_TSHSL_LSB);
365 reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
366 << CQSPI_REG_DELAY_TCHSH_LSB);
367 reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
368 << CQSPI_REG_DELAY_TSLCH_LSB);
369 reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
370 << CQSPI_REG_DELAY_TSD2D_LSB);
371 writel(reg, reg_base + CQSPI_REG_DELAY);
373 cadence_qspi_apb_controller_enable(reg_base);
376 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
380 cadence_qspi_apb_controller_disable(plat->regbase);
382 /* Configure the device size and address bytes */
383 reg = readl(plat->regbase + CQSPI_REG_SIZE);
384 /* Clear the previous value */
385 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
386 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
387 reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
388 reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
389 writel(reg, plat->regbase + CQSPI_REG_SIZE);
391 /* Configure the remap address register, no remap */
392 writel(0, plat->regbase + CQSPI_REG_REMAP);
394 /* Indirect mode configurations */
395 writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION);
397 /* Disable all interrupts */
398 writel(0, plat->regbase + CQSPI_REG_IRQMASK);
400 cadence_qspi_apb_controller_enable(plat->regbase);
403 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
406 unsigned int retry = CQSPI_REG_RETRY;
408 /* Write the CMDCTRL without start execution. */
409 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
411 reg |= CQSPI_REG_CMDCTRL_EXECUTE;
412 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
415 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
416 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
422 printf("QSPI: flash command execution timeout\n");
426 /* Polling QSPI idle status. */
427 if (!cadence_qspi_wait_idle(reg_base))
433 /* For command RDID, RDSR. */
434 int cadence_qspi_apb_command_read(void *reg_base, const struct spi_mem_op *op)
437 unsigned int read_len;
439 unsigned int rxlen = op->data.nbytes;
440 void *rxbuf = op->data.buf.in;
442 if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
443 printf("QSPI: Invalid input arguments rxlen %u\n", rxlen);
447 reg = op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
449 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
451 /* 0 means 1 byte. */
452 reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
453 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
454 status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
458 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
460 /* Put the read value into rx_buf */
461 read_len = (rxlen > 4) ? 4 : rxlen;
462 memcpy(rxbuf, ®, read_len);
466 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
468 read_len = rxlen - read_len;
469 memcpy(rxbuf, ®, read_len);
474 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
475 int cadence_qspi_apb_command_write(void *reg_base, const struct spi_mem_op *op)
477 unsigned int reg = 0;
478 unsigned int wr_data;
480 unsigned int txlen = op->data.nbytes;
481 const void *txbuf = op->data.buf.out;
484 /* Reorder address to SPI bus order if only transferring address */
486 addr = cpu_to_be32(op->addr.val);
487 if (op->addr.nbytes == 3)
490 txlen = op->addr.nbytes;
493 if (txlen > CQSPI_STIG_DATA_LEN_MAX) {
494 printf("QSPI: Invalid input arguments txlen %u\n", txlen);
498 reg |= op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
501 /* writing data = yes */
502 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
503 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
504 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
506 wr_len = txlen > 4 ? 4 : txlen;
507 memcpy(&wr_data, txbuf, wr_len);
508 writel(wr_data, reg_base +
509 CQSPI_REG_CMDWRITEDATALOWER);
513 wr_len = txlen - wr_len;
514 memcpy(&wr_data, txbuf, wr_len);
515 writel(wr_data, reg_base +
516 CQSPI_REG_CMDWRITEDATAUPPER);
520 /* Execute the command */
521 return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
524 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
525 int cadence_qspi_apb_read_setup(struct cadence_spi_platdata *plat,
526 const struct spi_mem_op *op)
530 unsigned int dummy_clk;
531 unsigned int dummy_bytes = op->dummy.nbytes;
533 /* Setup the indirect trigger address */
534 writel(plat->trigger_address,
535 plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
537 /* Configure the opcode */
538 rd_reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
540 if (op->data.buswidth == 4)
541 /* Instruction and address at DQ0, data at DQ0-3. */
542 rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
544 writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
547 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
548 dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
550 /* Convert to clock cycles. */
551 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
554 rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
555 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
558 writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
560 /* set device size */
561 reg = readl(plat->regbase + CQSPI_REG_SIZE);
562 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
563 reg |= (op->addr.nbytes - 1);
564 writel(reg, plat->regbase + CQSPI_REG_SIZE);
568 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
570 u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
571 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
572 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
575 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
577 unsigned int timeout = 10000;
581 reg = cadence_qspi_get_rd_sram_level(plat);
591 cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
592 unsigned int n_rx, u8 *rxbuf)
594 unsigned int remaining = n_rx;
595 unsigned int bytes_to_read = 0;
598 writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
600 /* Start the indirect read transfer */
601 writel(CQSPI_REG_INDIRECTRD_START,
602 plat->regbase + CQSPI_REG_INDIRECTRD);
604 while (remaining > 0) {
605 ret = cadence_qspi_wait_for_data(plat);
607 printf("Indirect write timed out (%i)\n", ret);
613 while (bytes_to_read != 0) {
614 bytes_to_read *= plat->fifo_width;
615 bytes_to_read = bytes_to_read > remaining ?
616 remaining : bytes_to_read;
618 * Handle non-4-byte aligned access to avoid
621 if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
622 readsb(plat->ahbbase, rxbuf, bytes_to_read);
624 readsl(plat->ahbbase, rxbuf,
626 rxbuf += bytes_to_read;
627 remaining -= bytes_to_read;
628 bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
632 /* Check indirect done status */
633 ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
634 CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
636 printf("Indirect read completion error (%i)\n", ret);
640 /* Clear indirect completion status */
641 writel(CQSPI_REG_INDIRECTRD_DONE,
642 plat->regbase + CQSPI_REG_INDIRECTRD);
647 /* Cancel the indirect read */
648 writel(CQSPI_REG_INDIRECTRD_CANCEL,
649 plat->regbase + CQSPI_REG_INDIRECTRD);
653 int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat,
654 const struct spi_mem_op *op)
656 u32 from = op->addr.val;
657 void *buf = op->data.buf.in;
658 size_t len = op->data.nbytes;
660 if (plat->use_dac_mode && (from + len < plat->ahbsize)) {
662 dma_memcpy(buf, plat->ahbbase + from, len) < 0) {
663 memcpy_fromio(buf, plat->ahbbase + from, len);
665 if (!cadence_qspi_wait_idle(plat->regbase))
670 return cadence_qspi_apb_indirect_read_execute(plat, len, buf);
673 /* Opcode + Address (3/4 bytes) */
674 int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat,
675 const struct spi_mem_op *op)
679 /* Setup the indirect trigger address */
680 writel(plat->trigger_address,
681 plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
683 /* Configure the opcode */
684 reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
685 writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
687 writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
689 reg = readl(plat->regbase + CQSPI_REG_SIZE);
690 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
691 reg |= (op->addr.nbytes - 1);
692 writel(reg, plat->regbase + CQSPI_REG_SIZE);
697 cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
698 unsigned int n_tx, const u8 *txbuf)
700 unsigned int page_size = plat->page_size;
701 unsigned int remaining = n_tx;
702 const u8 *bb_txbuf = txbuf;
703 void *bounce_buf = NULL;
704 unsigned int write_bytes;
708 * Use bounce buffer for non 32 bit aligned txbuf to avoid data
711 if ((uintptr_t)txbuf % 4) {
712 bounce_buf = malloc(n_tx);
715 memcpy(bounce_buf, txbuf, n_tx);
716 bb_txbuf = bounce_buf;
719 /* Configure the indirect read transfer bytes */
720 writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
722 /* Start the indirect write transfer */
723 writel(CQSPI_REG_INDIRECTWR_START,
724 plat->regbase + CQSPI_REG_INDIRECTWR);
726 while (remaining > 0) {
727 write_bytes = remaining > page_size ? page_size : remaining;
728 writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
730 writesb(plat->ahbbase,
731 bb_txbuf + rounddown(write_bytes, 4),
734 ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,
735 CQSPI_REG_SDRAMLEVEL_WR_MASK <<
736 CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
738 printf("Indirect write timed out (%i)\n", ret);
742 bb_txbuf += write_bytes;
743 remaining -= write_bytes;
746 /* Check indirect done status */
747 ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
748 CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
750 printf("Indirect write completion error (%i)\n", ret);
754 /* Clear indirect completion status */
755 writel(CQSPI_REG_INDIRECTWR_DONE,
756 plat->regbase + CQSPI_REG_INDIRECTWR);
762 /* Cancel the indirect write */
763 writel(CQSPI_REG_INDIRECTWR_CANCEL,
764 plat->regbase + CQSPI_REG_INDIRECTWR);
770 int cadence_qspi_apb_write_execute(struct cadence_spi_platdata *plat,
771 const struct spi_mem_op *op)
773 u32 to = op->addr.val;
774 const void *buf = op->data.buf.out;
775 size_t len = op->data.nbytes;
777 if (plat->use_dac_mode && (to + len < plat->ahbsize)) {
778 memcpy_toio(plat->ahbbase + to, buf, len);
779 if (!cadence_qspi_wait_idle(plat->regbase))
784 return cadence_qspi_apb_indirect_write_execute(plat, len, buf);
787 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
791 /* enter XiP mode immediately and enable direct mode */
792 reg = readl(reg_base + CQSPI_REG_CONFIG);
793 reg |= CQSPI_REG_CONFIG_ENABLE;
794 reg |= CQSPI_REG_CONFIG_DIRECT;
795 reg |= CQSPI_REG_CONFIG_XIP_IMM;
796 writel(reg, reg_base + CQSPI_REG_CONFIG);
798 /* keep the XiP mode */
799 writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
801 /* Enable mode bit at devrd */
802 reg = readl(reg_base + CQSPI_REG_RD_INSTR);
803 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
804 writel(reg, reg_base + CQSPI_REG_RD_INSTR);