drivers/spi/cadence_qspi_apb.c

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *  - Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  *  - Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *  - Neither the name of the Altera Corporation nor the
  13  *    names of its contributors may be used to endorse or promote products
  14  *    derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include <common.h>
  29 #include <asm/io.h>
  30 #include <linux/errno.h>
  31 #include <wait_bit.h>
  32 #include <spi.h>
  33 #include "cadence_qspi.h"
  34
  35 #define CQSPI_REG_POLL_US                       1 /* 1us */
  36 #define CQSPI_REG_RETRY                         10000
  37 #define CQSPI_POLL_IDLE_RETRY                   3
  38
  39 #define CQSPI_FIFO_WIDTH                        4
  40
  41 #define CQSPI_REG_SRAM_THRESHOLD_WORDS          50
  42
  43 /* Transfer mode */
  44 #define CQSPI_INST_TYPE_SINGLE                  0
  45 #define CQSPI_INST_TYPE_DUAL                    1
  46 #define CQSPI_INST_TYPE_QUAD                    2
  47
  48 #define CQSPI_STIG_DATA_LEN_MAX                 8
  49
  50 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
  51 #define CQSPI_DUMMY_BYTES_MAX                   4
  52
  53 #define CQSPI_REG_SRAM_FILL_THRESHOLD   \
  54         ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
  55
  56 /****************************************************************************
  57  * Controller's configuration and status register (offset from QSPI_BASE)
  58  ****************************************************************************/
  59 #define CQSPI_REG_CONFIG                        0x00
  60 #define CQSPI_REG_CONFIG_ENABLE                 BIT(0)
  61 #define CQSPI_REG_CONFIG_CLK_POL                BIT(1)
  62 #define CQSPI_REG_CONFIG_CLK_PHA                BIT(2)
  63 #define CQSPI_REG_CONFIG_DIRECT                 BIT(7)
  64 #define CQSPI_REG_CONFIG_DECODE                 BIT(9)
  65 #define CQSPI_REG_CONFIG_XIP_IMM                BIT(18)
  66 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
  67 #define CQSPI_REG_CONFIG_BAUD_LSB               19
  68 #define CQSPI_REG_CONFIG_IDLE_LSB               31
  69 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
  70 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
  71
  72 #define CQSPI_REG_RD_INSTR                      0x04
  73 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
  74 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
  75 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
  76 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
  77 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
  78 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
  79 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
  80 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
  81 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
  82 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
  83
  84 #define CQSPI_REG_WR_INSTR                      0x08
  85 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
  86
  87 #define CQSPI_REG_DELAY                         0x0C
  88 #define CQSPI_REG_DELAY_TSLCH_LSB               0
  89 #define CQSPI_REG_DELAY_TCHSH_LSB               8
  90 #define CQSPI_REG_DELAY_TSD2D_LSB               16
  91 #define CQSPI_REG_DELAY_TSHSL_LSB               24
  92 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
  93 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
  94 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
  95 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
  96
  97 #define CQSPI_REG_RD_DATA_CAPTURE               0x10
  98 #define CQSPI_REG_RD_DATA_CAPTURE_BYPASS        BIT(0)
  99 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB     1
 100 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK    0xF
 101
 102 #define CQSPI_REG_SIZE                          0x14
 103 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 104 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 105 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 106 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 107 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 108 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 109
 110 #define CQSPI_REG_SRAMPARTITION                 0x18
 111 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 112
 113 #define CQSPI_REG_REMAP                         0x24
 114 #define CQSPI_REG_MODE_BIT                      0x28
 115
 116 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 117 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 118 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 119 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 120 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 121
 122 #define CQSPI_REG_IRQSTATUS                     0x40
 123 #define CQSPI_REG_IRQMASK                       0x44
 124
 125 #define CQSPI_REG_INDIRECTRD                    0x60
 126 #define CQSPI_REG_INDIRECTRD_START              BIT(0)
 127 #define CQSPI_REG_INDIRECTRD_CANCEL             BIT(1)
 128 #define CQSPI_REG_INDIRECTRD_INPROGRESS         BIT(2)
 129 #define CQSPI_REG_INDIRECTRD_DONE               BIT(5)
 130
 131 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 132 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 133 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 134
 135 #define CQSPI_REG_CMDCTRL                       0x90
 136 #define CQSPI_REG_CMDCTRL_EXECUTE               BIT(0)
 137 #define CQSPI_REG_CMDCTRL_INPROGRESS            BIT(1)
 138 #define CQSPI_REG_CMDCTRL_DUMMY_LSB             7
 139 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 140 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 141 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 142 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 143 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 144 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 145 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 146 #define CQSPI_REG_CMDCTRL_DUMMY_MASK            0x1F
 147 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 148 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 149 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 150 #define CQSPI_REG_CMDCTRL_OPCODE_MASK           0xFF
 151
 152 #define CQSPI_REG_INDIRECTWR                    0x70
 153 #define CQSPI_REG_INDIRECTWR_START              BIT(0)
 154 #define CQSPI_REG_INDIRECTWR_CANCEL             BIT(1)
 155 #define CQSPI_REG_INDIRECTWR_INPROGRESS         BIT(2)
 156 #define CQSPI_REG_INDIRECTWR_DONE               BIT(5)
 157
 158 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 159 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 160 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 161
 162 #define CQSPI_REG_CMDADDRESS                    0x94
 163 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 164 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 165 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 166 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 167
 168 #define CQSPI_REG_IS_IDLE(base)                                 \
 169         ((readl(base + CQSPI_REG_CONFIG) >>             \
 170                 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
 171
 172 #define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns)           \
 173         ((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
 174
 175 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base)                       \
 176         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 177         CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
 178
 179 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base)                       \
 180         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 181         CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
 182
 183 static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
 184         unsigned int addr_width)
 185 {
 186         unsigned int addr;
 187
 188         addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
 189
 190         if (addr_width == 4)
 191                 addr = (addr << 8) | addr_buf[3];
 192
 193         return addr;
 194 }
 195
 196 void cadence_qspi_apb_controller_enable(void *reg_base)
 197 {
 198         unsigned int reg;
 199         reg = readl(reg_base + CQSPI_REG_CONFIG);
 200         reg |= CQSPI_REG_CONFIG_ENABLE;
 201         writel(reg, reg_base + CQSPI_REG_CONFIG);
 202 }
 203
 204 void cadence_qspi_apb_controller_disable(void *reg_base)
 205 {
 206         unsigned int reg;
 207         reg = readl(reg_base + CQSPI_REG_CONFIG);
 208         reg &= ~CQSPI_REG_CONFIG_ENABLE;
 209         writel(reg, reg_base + CQSPI_REG_CONFIG);
 210 }
 211
 212 /* Return 1 if idle, otherwise return 0 (busy). */
 213 static unsigned int cadence_qspi_wait_idle(void *reg_base)
 214 {
 215         unsigned int start, count = 0;
 216         /* timeout in unit of ms */
 217         unsigned int timeout = 5000;
 218
 219         start = get_timer(0);
 220         for ( ; get_timer(start) < timeout ; ) {
 221                 if (CQSPI_REG_IS_IDLE(reg_base))
 222                         count++;
 223                 else
 224                         count = 0;
 225                 /*
 226                  * Ensure the QSPI controller is in true idle state after
 227                  * reading back the same idle status consecutively
 228                  */
 229                 if (count >= CQSPI_POLL_IDLE_RETRY)
 230                         return 1;
 231         }
 232
 233         /* Timeout, still in busy mode. */
 234         printf("QSPI: QSPI is still busy after poll for %d times.\n",
 235                CQSPI_REG_RETRY);
 236         return 0;
 237 }
 238
 239 void cadence_qspi_apb_readdata_capture(void *reg_base,
 240                                 unsigned int bypass, unsigned int delay)
 241 {
 242         unsigned int reg;
 243         cadence_qspi_apb_controller_disable(reg_base);
 244
 245         reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
 246
 247         if (bypass)
 248                 reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
 249         else
 250                 reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
 251
 252         reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
 253                 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
 254
 255         reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
 256                 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
 257
 258         writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
 259
 260         cadence_qspi_apb_controller_enable(reg_base);
 261 }
 262
 263 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
 264         unsigned int ref_clk_hz, unsigned int sclk_hz)
 265 {
 266         unsigned int reg;
 267         unsigned int div;
 268
 269         cadence_qspi_apb_controller_disable(reg_base);
 270         reg = readl(reg_base + CQSPI_REG_CONFIG);
 271         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 272
 273         /*
 274          * The baud_div field in the config reg is 4 bits, and the ref clock is
 275          * divided by 2 * (baud_div + 1). Round up the divider to ensure the
 276          * SPI clock rate is less than or equal to the requested clock rate.
 277          */
 278         div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
 279
 280         /* ensure the baud rate doesn't exceed the max value */
 281         if (div > CQSPI_REG_CONFIG_BAUD_MASK)
 282                 div = CQSPI_REG_CONFIG_BAUD_MASK;
 283
 284         debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
 285               ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
 286
 287         reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
 288         writel(reg, reg_base + CQSPI_REG_CONFIG);
 289
 290         cadence_qspi_apb_controller_enable(reg_base);
 291 }
 292
 293 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
 294 {
 295         unsigned int reg;
 296
 297         cadence_qspi_apb_controller_disable(reg_base);
 298         reg = readl(reg_base + CQSPI_REG_CONFIG);
 299         reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
 300
 301         if (mode & SPI_CPOL)
 302                 reg |= CQSPI_REG_CONFIG_CLK_POL;
 303         if (mode & SPI_CPHA)
 304                 reg |= CQSPI_REG_CONFIG_CLK_PHA;
 305
 306         writel(reg, reg_base + CQSPI_REG_CONFIG);
 307
 308         cadence_qspi_apb_controller_enable(reg_base);
 309 }
 310
 311 void cadence_qspi_apb_chipselect(void *reg_base,
 312         unsigned int chip_select, unsigned int decoder_enable)
 313 {
 314         unsigned int reg;
 315
 316         cadence_qspi_apb_controller_disable(reg_base);
 317
 318         debug("%s : chipselect %d decode %d\n", __func__, chip_select,
 319               decoder_enable);
 320
 321         reg = readl(reg_base + CQSPI_REG_CONFIG);
 322         /* docoder */
 323         if (decoder_enable) {
 324                 reg |= CQSPI_REG_CONFIG_DECODE;
 325         } else {
 326                 reg &= ~CQSPI_REG_CONFIG_DECODE;
 327                 /* Convert CS if without decoder.
 328                  * CS0 to 4b'1110
 329                  * CS1 to 4b'1101
 330                  * CS2 to 4b'1011
 331                  * CS3 to 4b'0111
 332                  */
 333                 chip_select = 0xF & ~(1 << chip_select);
 334         }
 335
 336         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 337                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 338         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 339                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 340         writel(reg, reg_base + CQSPI_REG_CONFIG);
 341
 342         cadence_qspi_apb_controller_enable(reg_base);
 343 }
 344
 345 void cadence_qspi_apb_delay(void *reg_base,
 346         unsigned int ref_clk, unsigned int sclk_hz,
 347         unsigned int tshsl_ns, unsigned int tsd2d_ns,
 348         unsigned int tchsh_ns, unsigned int tslch_ns)
 349 {
 350         unsigned int ref_clk_ns;
 351         unsigned int sclk_ns;
 352         unsigned int tshsl, tchsh, tslch, tsd2d;
 353         unsigned int reg;
 354
 355         cadence_qspi_apb_controller_disable(reg_base);
 356
 357         /* Convert to ns. */
 358         ref_clk_ns = (1000000000) / ref_clk;
 359
 360         /* Convert to ns. */
 361         sclk_ns = (1000000000) / sclk_hz;
 362
 363         /* Plus 1 to round up 1 clock cycle. */
 364         tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1;
 365         tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1;
 366         tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1;
 367         tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1;
 368
 369         reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 370                         << CQSPI_REG_DELAY_TSHSL_LSB);
 371         reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 372                         << CQSPI_REG_DELAY_TCHSH_LSB);
 373         reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 374                         << CQSPI_REG_DELAY_TSLCH_LSB);
 375         reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 376                         << CQSPI_REG_DELAY_TSD2D_LSB);
 377         writel(reg, reg_base + CQSPI_REG_DELAY);
 378
 379         cadence_qspi_apb_controller_enable(reg_base);
 380 }
 381
 382 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
 383 {
 384         unsigned reg;
 385
 386         cadence_qspi_apb_controller_disable(plat->regbase);
 387
 388         /* Configure the device size and address bytes */
 389         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 390         /* Clear the previous value */
 391         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 392         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 393         reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 394         reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
 395         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 396
 397         /* Configure the remap address register, no remap */
 398         writel(0, plat->regbase + CQSPI_REG_REMAP);
 399
 400         /* Indirect mode configurations */
 401         writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
 402
 403         /* Disable all interrupts */
 404         writel(0, plat->regbase + CQSPI_REG_IRQMASK);
 405
 406         cadence_qspi_apb_controller_enable(plat->regbase);
 407 }
 408
 409 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
 410         unsigned int reg)
 411 {
 412         unsigned int retry = CQSPI_REG_RETRY;
 413
 414         /* Write the CMDCTRL without start execution. */
 415         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 416         /* Start execute */
 417         reg |= CQSPI_REG_CMDCTRL_EXECUTE;
 418         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 419
 420         while (retry--) {
 421                 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
 422                 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
 423                         break;
 424                 udelay(1);
 425         }
 426
 427         if (!retry) {
 428                 printf("QSPI: flash command execution timeout\n");
 429                 return -EIO;
 430         }
 431
 432         /* Polling QSPI idle status. */
 433         if (!cadence_qspi_wait_idle(reg_base))
 434                 return -EIO;
 435
 436         return 0;
 437 }
 438
 439 /* For command RDID, RDSR. */
 440 int cadence_qspi_apb_command_read(void *reg_base,
 441         unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
 442         u8 *rxbuf)
 443 {
 444         unsigned int reg;
 445         unsigned int read_len;
 446         int status;
 447
 448         if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
 449                 printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
 450                        cmdlen, rxlen);
 451                 return -EINVAL;
 452         }
 453
 454         reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 455
 456         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 457
 458         /* 0 means 1 byte. */
 459         reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 460                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 461         status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 462         if (status != 0)
 463                 return status;
 464
 465         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 466
 467         /* Put the read value into rx_buf */
 468         read_len = (rxlen > 4) ? 4 : rxlen;
 469         memcpy(rxbuf, &reg, read_len);
 470         rxbuf += read_len;
 471
 472         if (rxlen > 4) {
 473                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 474
 475                 read_len = rxlen - read_len;
 476                 memcpy(rxbuf, &reg, read_len);
 477         }
 478         return 0;
 479 }
 480
 481 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
 482 int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
 483         const u8 *cmdbuf, unsigned int txlen,  const u8 *txbuf)
 484 {
 485         unsigned int reg = 0;
 486         unsigned int addr_value;
 487         unsigned int wr_data;
 488         unsigned int wr_len;
 489
 490         if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
 491                 printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
 492                        cmdlen, txlen);
 493                 return -EINVAL;
 494         }
 495
 496         reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 497
 498         if (cmdlen == 4 || cmdlen == 5) {
 499                 /* Command with address */
 500                 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 501                 /* Number of bytes to write. */
 502                 reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 503                         << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 504                 /* Get address */
 505                 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
 506                         cmdlen >= 5 ? 4 : 3);
 507
 508                 writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
 509         }
 510
 511         if (txlen) {
 512                 /* writing data = yes */
 513                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 514                 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 515                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 516
 517                 wr_len = txlen > 4 ? 4 : txlen;
 518                 memcpy(&wr_data, txbuf, wr_len);
 519                 writel(wr_data, reg_base +
 520                         CQSPI_REG_CMDWRITEDATALOWER);
 521
 522                 if (txlen > 4) {
 523                         txbuf += wr_len;
 524                         wr_len = txlen - wr_len;
 525                         memcpy(&wr_data, txbuf, wr_len);
 526                         writel(wr_data, reg_base +
 527                                 CQSPI_REG_CMDWRITEDATAUPPER);
 528                 }
 529         }
 530
 531         /* Execute the command */
 532         return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 533 }
 534
 535 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
 536 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
 537         unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf)
 538 {
 539         unsigned int reg;
 540         unsigned int rd_reg;
 541         unsigned int addr_value;
 542         unsigned int dummy_clk;
 543         unsigned int dummy_bytes;
 544         unsigned int addr_bytes;
 545
 546         /*
 547          * Identify addr_byte. All NOR flash device drivers are using fast read
 548          * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
 549          * With that, the length is in value of 5 or 6. Only FRAM chip from
 550          * ramtron using normal read (which won't need dummy byte).
 551          * Unlikely NOR flash using normal read due to performance issue.
 552          */
 553         if (cmdlen >= 5)
 554                 /* to cater fast read where cmd + addr + dummy */
 555                 addr_bytes = cmdlen - 2;
 556         else
 557                 /* for normal read (only ramtron as of now) */
 558                 addr_bytes = cmdlen - 1;
 559
 560         /* Setup the indirect trigger address */
 561         writel((u32)plat->ahbbase,
 562                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 563
 564         /* Configure the opcode */
 565         rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 566
 567         if (rx_width & SPI_RX_QUAD)
 568                 /* Instruction and address at DQ0, data at DQ0-3. */
 569                 rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 570
 571         /* Get address */
 572         addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
 573         writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
 574
 575         /* The remaining lenght is dummy bytes. */
 576         dummy_bytes = cmdlen - addr_bytes - 1;
 577         if (dummy_bytes) {
 578                 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
 579                         dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
 580
 581                 rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 582 #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
 583                 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
 584 #else
 585                 writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
 586 #endif
 587
 588                 /* Convert to clock cycles. */
 589                 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
 590                 /* Need to minus the mode byte (8 clocks). */
 591                 dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
 592
 593                 if (dummy_clk)
 594                         rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 595                                 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 596         }
 597
 598         writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
 599
 600         /* set device size */
 601         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 602         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 603         reg |= (addr_bytes - 1);
 604         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 605         return 0;
 606 }
 607
 608 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
 609 {
 610         u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
 611         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 612         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 613 }
 614
 615 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
 616 {
 617         unsigned int timeout = 10000;
 618         u32 reg;
 619
 620         while (timeout--) {
 621                 reg = cadence_qspi_get_rd_sram_level(plat);
 622                 if (reg)
 623                         return reg;
 624                 udelay(1);
 625         }
 626
 627         return -ETIMEDOUT;
 628 }
 629
 630 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
 631         unsigned int n_rx, u8 *rxbuf)
 632 {
 633         unsigned int remaining = n_rx;
 634         unsigned int bytes_to_read = 0;
 635         int ret;
 636
 637         writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
 638
 639         /* Start the indirect read transfer */
 640         writel(CQSPI_REG_INDIRECTRD_START,
 641                plat->regbase + CQSPI_REG_INDIRECTRD);
 642
 643         while (remaining > 0) {
 644                 ret = cadence_qspi_wait_for_data(plat);
 645                 if (ret < 0) {
 646                         printf("Indirect write timed out (%i)\n", ret);
 647                         goto failrd;
 648                 }
 649
 650                 bytes_to_read = ret;
 651
 652                 while (bytes_to_read != 0) {
 653                         bytes_to_read *= CQSPI_FIFO_WIDTH;
 654                         bytes_to_read = bytes_to_read > remaining ?
 655                                         remaining : bytes_to_read;
 656                         /* Handle non-4-byte aligned access to avoid data abort. */
 657                         if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
 658                                 readsb(plat->ahbbase, rxbuf, bytes_to_read);
 659                         else
 660                                 readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2);
 661                         rxbuf += bytes_to_read;
 662                         remaining -= bytes_to_read;
 663                         bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
 664                 }
 665         }
 666
 667         /* Check indirect done status */
 668         ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD,
 669                            CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
 670         if (ret) {
 671                 printf("Indirect read completion error (%i)\n", ret);
 672                 goto failrd;
 673         }
 674
 675         /* Clear indirect completion status */
 676         writel(CQSPI_REG_INDIRECTRD_DONE,
 677                plat->regbase + CQSPI_REG_INDIRECTRD);
 678
 679         return 0;
 680
 681 failrd:
 682         /* Cancel the indirect read */
 683         writel(CQSPI_REG_INDIRECTRD_CANCEL,
 684                plat->regbase + CQSPI_REG_INDIRECTRD);
 685         return ret;
 686 }
 687
 688 /* Opcode + Address (3/4 bytes) */
 689 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
 690         unsigned int cmdlen, const u8 *cmdbuf)
 691 {
 692         unsigned int reg;
 693         unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
 694
 695         if (cmdlen < 4 || cmdbuf == NULL) {
 696                 printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
 697                        cmdlen, (unsigned int)cmdbuf);
 698                 return -EINVAL;
 699         }
 700         /* Setup the indirect trigger address */
 701         writel((u32)plat->ahbbase,
 702                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 703
 704         /* Configure the opcode */
 705         reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 706         writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
 707
 708         /* Setup write address. */
 709         reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
 710         writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
 711
 712         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 713         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 714         reg |= (addr_bytes - 1);
 715         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 716         return 0;
 717 }
 718
 719 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
 720         unsigned int n_tx, const u8 *txbuf)
 721 {
 722         unsigned int page_size = plat->page_size;
 723         unsigned int remaining = n_tx;
 724         unsigned int write_bytes;
 725         int ret;
 726
 727         /* Configure the indirect read transfer bytes */
 728         writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
 729
 730         /* Start the indirect write transfer */
 731         writel(CQSPI_REG_INDIRECTWR_START,
 732                plat->regbase + CQSPI_REG_INDIRECTWR);
 733
 734         while (remaining > 0) {
 735                 write_bytes = remaining > page_size ? page_size : remaining;
 736                 /* Handle non-4-byte aligned access to avoid data abort. */
 737                 if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
 738                         writesb(plat->ahbbase, txbuf, write_bytes);
 739                 else
 740                         writesl(plat->ahbbase, txbuf, write_bytes >> 2);
 741
 742                 ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
 743                                    CQSPI_REG_SDRAMLEVEL_WR_MASK <<
 744                                    CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
 745                 if (ret) {
 746                         printf("Indirect write timed out (%i)\n", ret);
 747                         goto failwr;
 748                 }
 749
 750                 txbuf += write_bytes;
 751                 remaining -= write_bytes;
 752         }
 753
 754         /* Check indirect done status */
 755         ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR,
 756                            CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
 757         if (ret) {
 758                 printf("Indirect write completion error (%i)\n", ret);
 759                 goto failwr;
 760         }
 761
 762         /* Clear indirect completion status */
 763         writel(CQSPI_REG_INDIRECTWR_DONE,
 764                plat->regbase + CQSPI_REG_INDIRECTWR);
 765         return 0;
 766
 767 failwr:
 768         /* Cancel the indirect write */
 769         writel(CQSPI_REG_INDIRECTWR_CANCEL,
 770                plat->regbase + CQSPI_REG_INDIRECTWR);
 771         return ret;
 772 }
 773
 774 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
 775 {
 776         unsigned int reg;
 777
 778         /* enter XiP mode immediately and enable direct mode */
 779         reg = readl(reg_base + CQSPI_REG_CONFIG);
 780         reg |= CQSPI_REG_CONFIG_ENABLE;
 781         reg |= CQSPI_REG_CONFIG_DIRECT;
 782         reg |= CQSPI_REG_CONFIG_XIP_IMM;
 783         writel(reg, reg_base + CQSPI_REG_CONFIG);
 784
 785         /* keep the XiP mode */
 786         writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
 787
 788         /* Enable mode bit at devrd */
 789         reg = readl(reg_base + CQSPI_REG_RD_INSTR);
 790         reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 791         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 792 }