drivers/spi/cadence_qspi_apb.c

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *  - Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  *  - Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *  - Neither the name of the Altera Corporation nor the
  13  *    names of its contributors may be used to endorse or promote products
  14  *    derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include <common.h>
  29 #include <log.h>
  30 #include <asm/io.h>
  31 #include <dma.h>
  32 #include <linux/bitops.h>
  33 #include <linux/delay.h>
  34 #include <linux/errno.h>
  35 #include <wait_bit.h>
  36 #include <spi.h>
  37 #include <spi-mem.h>
  38 #include <malloc.h>
  39 #include "cadence_qspi.h"
  40
  41 __weak void cadence_qspi_apb_enable_linear_mode(bool enable)
  42 {
  43         return;
  44 }
  45
  46 void cadence_qspi_apb_controller_enable(void *reg_base)
  47 {
  48         unsigned int reg;
  49         reg = readl(reg_base + CQSPI_REG_CONFIG);
  50         reg |= CQSPI_REG_CONFIG_ENABLE;
  51         writel(reg, reg_base + CQSPI_REG_CONFIG);
  52 }
  53
  54 void cadence_qspi_apb_controller_disable(void *reg_base)
  55 {
  56         unsigned int reg;
  57         reg = readl(reg_base + CQSPI_REG_CONFIG);
  58         reg &= ~CQSPI_REG_CONFIG_ENABLE;
  59         writel(reg, reg_base + CQSPI_REG_CONFIG);
  60 }
  61
  62 void cadence_qspi_apb_dac_mode_enable(void *reg_base)
  63 {
  64         unsigned int reg;
  65
  66         reg = readl(reg_base + CQSPI_REG_CONFIG);
  67         reg |= CQSPI_REG_CONFIG_DIRECT;
  68         writel(reg, reg_base + CQSPI_REG_CONFIG);
  69 }
  70
  71 static unsigned int cadence_qspi_calc_dummy(const struct spi_mem_op *op,
  72                                             bool dtr)
  73 {
  74         unsigned int dummy_clk;
  75
  76         if (!op->dummy.nbytes || !op->dummy.buswidth)
  77                 return 0;
  78
  79         dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
  80         if (dtr)
  81                 dummy_clk /= 2;
  82
  83         return dummy_clk;
  84 }
  85
  86 static u32 cadence_qspi_calc_rdreg(struct cadence_spi_priv *priv)
  87 {
  88         u32 rdreg = 0;
  89
  90         rdreg |= priv->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
  91         rdreg |= priv->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
  92         rdreg |= priv->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
  93
  94         return rdreg;
  95 }
  96
  97 static int cadence_qspi_buswidth_to_inst_type(u8 buswidth)
  98 {
  99         switch (buswidth) {
 100         case 0:
 101         case 1:
 102                 return CQSPI_INST_TYPE_SINGLE;
 103
 104         case 2:
 105                 return CQSPI_INST_TYPE_DUAL;
 106
 107         case 4:
 108                 return CQSPI_INST_TYPE_QUAD;
 109
 110         case 8:
 111                 return CQSPI_INST_TYPE_OCTAL;
 112
 113         default:
 114                 return -ENOTSUPP;
 115         }
 116 }
 117
 118 static int cadence_qspi_set_protocol(struct cadence_spi_priv *priv,
 119                                      const struct spi_mem_op *op)
 120 {
 121         int ret;
 122
 123         priv->dtr = op->data.dtr && op->cmd.dtr && op->addr.dtr;
 124
 125         ret = cadence_qspi_buswidth_to_inst_type(op->cmd.buswidth);
 126         if (ret < 0)
 127                 return ret;
 128         priv->inst_width = ret;
 129
 130         ret = cadence_qspi_buswidth_to_inst_type(op->addr.buswidth);
 131         if (ret < 0)
 132                 return ret;
 133         priv->addr_width = ret;
 134
 135         ret = cadence_qspi_buswidth_to_inst_type(op->data.buswidth);
 136         if (ret < 0)
 137                 return ret;
 138         priv->data_width = ret;
 139
 140         return 0;
 141 }
 142
 143 /* Return 1 if idle, otherwise return 0 (busy). */
 144 static unsigned int cadence_qspi_wait_idle(void *reg_base)
 145 {
 146         unsigned int start, count = 0;
 147         /* timeout in unit of ms */
 148         unsigned int timeout = 5000;
 149
 150         start = get_timer(0);
 151         for ( ; get_timer(start) < timeout ; ) {
 152                 if (CQSPI_REG_IS_IDLE(reg_base))
 153                         count++;
 154                 else
 155                         count = 0;
 156                 /*
 157                  * Ensure the QSPI controller is in true idle state after
 158                  * reading back the same idle status consecutively
 159                  */
 160                 if (count >= CQSPI_POLL_IDLE_RETRY)
 161                         return 1;
 162         }
 163
 164         /* Timeout, still in busy mode. */
 165         printf("QSPI: QSPI is still busy after poll for %d times.\n",
 166                CQSPI_REG_RETRY);
 167         return 0;
 168 }
 169
 170 void cadence_qspi_apb_readdata_capture(void *reg_base,
 171                                 unsigned int bypass, unsigned int delay)
 172 {
 173         unsigned int reg;
 174         cadence_qspi_apb_controller_disable(reg_base);
 175
 176         reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
 177
 178         if (bypass)
 179                 reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
 180         else
 181                 reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
 182
 183         reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
 184                 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
 185
 186         reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
 187                 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
 188
 189         writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
 190
 191         cadence_qspi_apb_controller_enable(reg_base);
 192 }
 193
 194 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
 195         unsigned int ref_clk_hz, unsigned int sclk_hz)
 196 {
 197         unsigned int reg;
 198         unsigned int div;
 199
 200         cadence_qspi_apb_controller_disable(reg_base);
 201         reg = readl(reg_base + CQSPI_REG_CONFIG);
 202         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 203
 204         /*
 205          * The baud_div field in the config reg is 4 bits, and the ref clock is
 206          * divided by 2 * (baud_div + 1). Round up the divider to ensure the
 207          * SPI clock rate is less than or equal to the requested clock rate.
 208          */
 209         div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
 210
 211         /* ensure the baud rate doesn't exceed the max value */
 212         if (div > CQSPI_REG_CONFIG_BAUD_MASK)
 213                 div = CQSPI_REG_CONFIG_BAUD_MASK;
 214
 215         debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
 216               ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
 217
 218         reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
 219         writel(reg, reg_base + CQSPI_REG_CONFIG);
 220
 221         cadence_qspi_apb_controller_enable(reg_base);
 222 }
 223
 224 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
 225 {
 226         unsigned int reg;
 227
 228         cadence_qspi_apb_controller_disable(reg_base);
 229         reg = readl(reg_base + CQSPI_REG_CONFIG);
 230         reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
 231
 232         if (mode & SPI_CPOL)
 233                 reg |= CQSPI_REG_CONFIG_CLK_POL;
 234         if (mode & SPI_CPHA)
 235                 reg |= CQSPI_REG_CONFIG_CLK_PHA;
 236
 237         writel(reg, reg_base + CQSPI_REG_CONFIG);
 238
 239         cadence_qspi_apb_controller_enable(reg_base);
 240 }
 241
 242 void cadence_qspi_apb_chipselect(void *reg_base,
 243         unsigned int chip_select, unsigned int decoder_enable)
 244 {
 245         unsigned int reg;
 246
 247         cadence_qspi_apb_controller_disable(reg_base);
 248
 249         debug("%s : chipselect %d decode %d\n", __func__, chip_select,
 250               decoder_enable);
 251
 252         reg = readl(reg_base + CQSPI_REG_CONFIG);
 253         /* docoder */
 254         if (decoder_enable) {
 255                 reg |= CQSPI_REG_CONFIG_DECODE;
 256         } else {
 257                 reg &= ~CQSPI_REG_CONFIG_DECODE;
 258                 /* Convert CS if without decoder.
 259                  * CS0 to 4b'1110
 260                  * CS1 to 4b'1101
 261                  * CS2 to 4b'1011
 262                  * CS3 to 4b'0111
 263                  */
 264                 chip_select = 0xF & ~(1 << chip_select);
 265         }
 266
 267         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 268                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 269         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 270                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 271         writel(reg, reg_base + CQSPI_REG_CONFIG);
 272
 273         cadence_qspi_apb_controller_enable(reg_base);
 274 }
 275
 276 void cadence_qspi_apb_delay(void *reg_base,
 277         unsigned int ref_clk, unsigned int sclk_hz,
 278         unsigned int tshsl_ns, unsigned int tsd2d_ns,
 279         unsigned int tchsh_ns, unsigned int tslch_ns)
 280 {
 281         unsigned int ref_clk_ns;
 282         unsigned int sclk_ns;
 283         unsigned int tshsl, tchsh, tslch, tsd2d;
 284         unsigned int reg;
 285
 286         cadence_qspi_apb_controller_disable(reg_base);
 287
 288         /* Convert to ns. */
 289         ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
 290
 291         /* Convert to ns. */
 292         sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
 293
 294         /* The controller adds additional delay to that programmed in the reg */
 295         if (tshsl_ns >= sclk_ns + ref_clk_ns)
 296                 tshsl_ns -= sclk_ns + ref_clk_ns;
 297         if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
 298                 tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
 299         tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
 300         tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
 301         tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
 302         tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
 303
 304         reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 305                         << CQSPI_REG_DELAY_TSHSL_LSB);
 306         reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 307                         << CQSPI_REG_DELAY_TCHSH_LSB);
 308         reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 309                         << CQSPI_REG_DELAY_TSLCH_LSB);
 310         reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 311                         << CQSPI_REG_DELAY_TSD2D_LSB);
 312         writel(reg, reg_base + CQSPI_REG_DELAY);
 313
 314         cadence_qspi_apb_controller_enable(reg_base);
 315 }
 316
 317 void cadence_qspi_apb_controller_init(struct cadence_spi_priv *priv)
 318 {
 319         unsigned reg;
 320
 321         cadence_qspi_apb_controller_disable(priv->regbase);
 322
 323         /* Configure the device size and address bytes */
 324         reg = readl(priv->regbase + CQSPI_REG_SIZE);
 325         /* Clear the previous value */
 326         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 327         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 328         reg |= (priv->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 329         reg |= (priv->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
 330         writel(reg, priv->regbase + CQSPI_REG_SIZE);
 331
 332         /* Configure the remap address register, no remap */
 333         writel(0, priv->regbase + CQSPI_REG_REMAP);
 334
 335         /* Indirect mode configurations */
 336         writel(priv->fifo_depth / 2, priv->regbase + CQSPI_REG_SRAMPARTITION);
 337
 338         /* Disable all interrupts */
 339         writel(0, priv->regbase + CQSPI_REG_IRQMASK);
 340
 341         cadence_qspi_apb_controller_enable(priv->regbase);
 342 }
 343
 344 int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg)
 345 {
 346         unsigned int retry = CQSPI_REG_RETRY;
 347
 348         /* Write the CMDCTRL without start execution. */
 349         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 350         /* Start execute */
 351         reg |= CQSPI_REG_CMDCTRL_EXECUTE;
 352         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 353
 354         while (retry--) {
 355                 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
 356                 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
 357                         break;
 358                 udelay(1);
 359         }
 360
 361         if (!retry) {
 362                 printf("QSPI: flash command execution timeout\n");
 363                 return -EIO;
 364         }
 365
 366         /* Polling QSPI idle status. */
 367         if (!cadence_qspi_wait_idle(reg_base))
 368                 return -EIO;
 369
 370         return 0;
 371 }
 372
 373 static int cadence_qspi_setup_opcode_ext(struct cadence_spi_priv *priv,
 374                                          const struct spi_mem_op *op,
 375                                          unsigned int shift)
 376 {
 377         unsigned int reg;
 378         u8 ext;
 379
 380         if (op->cmd.nbytes != 2)
 381                 return -EINVAL;
 382
 383         /* Opcode extension is the LSB. */
 384         ext = op->cmd.opcode & 0xff;
 385
 386         reg = readl(priv->regbase + CQSPI_REG_OP_EXT_LOWER);
 387         reg &= ~(0xff << shift);
 388         reg |= ext << shift;
 389         writel(reg, priv->regbase + CQSPI_REG_OP_EXT_LOWER);
 390
 391         return 0;
 392 }
 393
 394 static int cadence_qspi_enable_dtr(struct cadence_spi_priv *priv,
 395                                    const struct spi_mem_op *op,
 396                                    unsigned int shift,
 397                                    bool enable)
 398 {
 399         unsigned int reg;
 400         int ret;
 401
 402         reg = readl(priv->regbase + CQSPI_REG_CONFIG);
 403
 404         if (enable) {
 405                 reg |= CQSPI_REG_CONFIG_DTR_PROTO;
 406                 reg |= CQSPI_REG_CONFIG_DUAL_OPCODE;
 407
 408                 /* Set up command opcode extension. */
 409                 ret = cadence_qspi_setup_opcode_ext(priv, op, shift);
 410                 if (ret)
 411                         return ret;
 412         } else {
 413                 reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
 414                 reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
 415         }
 416
 417         writel(reg, priv->regbase + CQSPI_REG_CONFIG);
 418
 419         return 0;
 420 }
 421
 422 int cadence_qspi_apb_command_read_setup(struct cadence_spi_priv *priv,
 423                                         const struct spi_mem_op *op)
 424 {
 425         int ret;
 426         unsigned int reg;
 427
 428         ret = cadence_qspi_set_protocol(priv, op);
 429         if (ret)
 430                 return ret;
 431
 432         ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_STIG_LSB,
 433                                       priv->dtr);
 434         if (ret)
 435                 return ret;
 436
 437         reg = cadence_qspi_calc_rdreg(priv);
 438         writel(reg, priv->regbase + CQSPI_REG_RD_INSTR);
 439
 440         return 0;
 441 }
 442
 443 /* For command RDID, RDSR. */
 444 int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv,
 445                                   const struct spi_mem_op *op)
 446 {
 447         void *reg_base = priv->regbase;
 448         unsigned int reg;
 449         unsigned int read_len;
 450         int status;
 451         unsigned int rxlen = op->data.nbytes;
 452         void *rxbuf = op->data.buf.in;
 453         unsigned int dummy_clk;
 454         u8 opcode;
 455
 456         if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 457                 printf("QSPI: Invalid input arguments rxlen %u\n", rxlen);
 458                 return -EINVAL;
 459         }
 460
 461         if (priv->dtr)
 462                 opcode = op->cmd.opcode >> 8;
 463         else
 464                 opcode = op->cmd.opcode;
 465
 466         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 467
 468         /* Set up dummy cycles. */
 469         dummy_clk = cadence_qspi_calc_dummy(op, priv->dtr);
 470         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 471                 return -ENOTSUPP;
 472
 473         if (dummy_clk)
 474                 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
 475                      << CQSPI_REG_CMDCTRL_DUMMY_LSB;
 476
 477         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 478
 479         /* 0 means 1 byte. */
 480         reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 481                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 482         status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 483         if (status != 0)
 484                 return status;
 485
 486         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 487
 488         /* Put the read value into rx_buf */
 489         read_len = (rxlen > 4) ? 4 : rxlen;
 490         memcpy(rxbuf, &reg, read_len);
 491         rxbuf += read_len;
 492
 493         if (rxlen > 4) {
 494                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 495
 496                 read_len = rxlen - read_len;
 497                 memcpy(rxbuf, &reg, read_len);
 498         }
 499         return 0;
 500 }
 501
 502 int cadence_qspi_apb_command_write_setup(struct cadence_spi_priv *priv,
 503                                          const struct spi_mem_op *op)
 504 {
 505         int ret;
 506         unsigned int reg;
 507
 508         ret = cadence_qspi_set_protocol(priv, op);
 509         if (ret)
 510                 return ret;
 511
 512         ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_STIG_LSB,
 513                                       priv->dtr);
 514         if (ret)
 515                 return ret;
 516
 517         reg = cadence_qspi_calc_rdreg(priv);
 518         writel(reg, priv->regbase + CQSPI_REG_RD_INSTR);
 519
 520         return 0;
 521 }
 522
 523 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
 524 int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv,
 525                                    const struct spi_mem_op *op)
 526 {
 527         unsigned int reg = 0;
 528         unsigned int wr_data;
 529         unsigned int wr_len;
 530         unsigned int txlen = op->data.nbytes;
 531         const void *txbuf = op->data.buf.out;
 532         void *reg_base = priv->regbase;
 533         u32 addr;
 534         u8 opcode;
 535
 536         /* Reorder address to SPI bus order if only transferring address */
 537         if (!txlen) {
 538                 addr = cpu_to_be32(op->addr.val);
 539                 if (op->addr.nbytes == 3)
 540                         addr >>= 8;
 541                 txbuf = &addr;
 542                 txlen = op->addr.nbytes;
 543         }
 544
 545         if (txlen > CQSPI_STIG_DATA_LEN_MAX) {
 546                 printf("QSPI: Invalid input arguments txlen %u\n", txlen);
 547                 return -EINVAL;
 548         }
 549
 550         if (priv->dtr)
 551                 opcode = op->cmd.opcode >> 8;
 552         else
 553                 opcode = op->cmd.opcode;
 554
 555         reg |= opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 556
 557         if (txlen) {
 558                 /* writing data = yes */
 559                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 560                 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 561                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 562
 563                 wr_len = txlen > 4 ? 4 : txlen;
 564                 memcpy(&wr_data, txbuf, wr_len);
 565                 writel(wr_data, reg_base +
 566                         CQSPI_REG_CMDWRITEDATALOWER);
 567
 568                 if (txlen > 4) {
 569                         txbuf += wr_len;
 570                         wr_len = txlen - wr_len;
 571                         memcpy(&wr_data, txbuf, wr_len);
 572                         writel(wr_data, reg_base +
 573                                 CQSPI_REG_CMDWRITEDATAUPPER);
 574                 }
 575         }
 576
 577         /* Execute the command */
 578         return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 579 }
 580
 581 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
 582 int cadence_qspi_apb_read_setup(struct cadence_spi_priv *priv,
 583                                 const struct spi_mem_op *op)
 584 {
 585         unsigned int reg;
 586         unsigned int rd_reg;
 587         unsigned int dummy_clk;
 588         unsigned int dummy_bytes = op->dummy.nbytes;
 589         int ret;
 590         u8 opcode;
 591
 592         ret = cadence_qspi_set_protocol(priv, op);
 593         if (ret)
 594                 return ret;
 595
 596         ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_READ_LSB,
 597                                       priv->dtr);
 598         if (ret)
 599                 return ret;
 600
 601         /* Setup the indirect trigger address */
 602         writel(priv->trigger_address,
 603                priv->regbase + CQSPI_REG_INDIRECTTRIGGER);
 604
 605         /* Configure the opcode */
 606         if (priv->dtr)
 607                 opcode = op->cmd.opcode >> 8;
 608         else
 609                 opcode = op->cmd.opcode;
 610
 611         rd_reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 612         rd_reg |= cadence_qspi_calc_rdreg(priv);
 613
 614         writel(op->addr.val, priv->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
 615
 616         if (dummy_bytes) {
 617                 /* Convert to clock cycles. */
 618                 dummy_clk = cadence_qspi_calc_dummy(op, priv->dtr);
 619
 620                 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 621                         return -ENOTSUPP;
 622
 623                 if (dummy_clk)
 624                         rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 625                                 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 626         }
 627
 628         writel(rd_reg, priv->regbase + CQSPI_REG_RD_INSTR);
 629
 630         /* set device size */
 631         reg = readl(priv->regbase + CQSPI_REG_SIZE);
 632         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 633         reg |= (op->addr.nbytes - 1);
 634         writel(reg, priv->regbase + CQSPI_REG_SIZE);
 635         return 0;
 636 }
 637
 638 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_priv *priv)
 639 {
 640         u32 reg = readl(priv->regbase + CQSPI_REG_SDRAMLEVEL);
 641         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 642         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 643 }
 644
 645 static int cadence_qspi_wait_for_data(struct cadence_spi_priv *priv)
 646 {
 647         unsigned int timeout = 10000;
 648         u32 reg;
 649
 650         while (timeout--) {
 651                 reg = cadence_qspi_get_rd_sram_level(priv);
 652                 if (reg)
 653                         return reg;
 654                 udelay(1);
 655         }
 656
 657         return -ETIMEDOUT;
 658 }
 659
 660 static int
 661 cadence_qspi_apb_indirect_read_execute(struct cadence_spi_priv *priv,
 662                                        unsigned int n_rx, u8 *rxbuf)
 663 {
 664         unsigned int remaining = n_rx;
 665         unsigned int bytes_to_read = 0;
 666         int ret;
 667
 668         writel(n_rx, priv->regbase + CQSPI_REG_INDIRECTRDBYTES);
 669
 670         /* Start the indirect read transfer */
 671         writel(CQSPI_REG_INDIRECTRD_START,
 672                priv->regbase + CQSPI_REG_INDIRECTRD);
 673
 674         while (remaining > 0) {
 675                 ret = cadence_qspi_wait_for_data(priv);
 676                 if (ret < 0) {
 677                         printf("Indirect write timed out (%i)\n", ret);
 678                         goto failrd;
 679                 }
 680
 681                 bytes_to_read = ret;
 682
 683                 while (bytes_to_read != 0) {
 684                         bytes_to_read *= priv->fifo_width;
 685                         bytes_to_read = bytes_to_read > remaining ?
 686                                         remaining : bytes_to_read;
 687                         /*
 688                          * Handle non-4-byte aligned access to avoid
 689                          * data abort.
 690                          */
 691                         if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
 692                                 readsb(priv->ahbbase, rxbuf, bytes_to_read);
 693                         else
 694                                 readsl(priv->ahbbase, rxbuf,
 695                                        bytes_to_read >> 2);
 696                         rxbuf += bytes_to_read;
 697                         remaining -= bytes_to_read;
 698                         bytes_to_read = cadence_qspi_get_rd_sram_level(priv);
 699                 }
 700         }
 701
 702         /* Check indirect done status */
 703         ret = wait_for_bit_le32(priv->regbase + CQSPI_REG_INDIRECTRD,
 704                                 CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
 705         if (ret) {
 706                 printf("Indirect read completion error (%i)\n", ret);
 707                 goto failrd;
 708         }
 709
 710         /* Clear indirect completion status */
 711         writel(CQSPI_REG_INDIRECTRD_DONE,
 712                priv->regbase + CQSPI_REG_INDIRECTRD);
 713
 714         /* Check indirect done status */
 715         ret = wait_for_bit_le32(priv->regbase + CQSPI_REG_INDIRECTRD,
 716                                 CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0);
 717         if (ret) {
 718                 printf("Indirect read clear completion error (%i)\n", ret);
 719                 goto failrd;
 720         }
 721
 722         return 0;
 723
 724 failrd:
 725         /* Cancel the indirect read */
 726         writel(CQSPI_REG_INDIRECTRD_CANCEL,
 727                priv->regbase + CQSPI_REG_INDIRECTRD);
 728         return ret;
 729 }
 730
 731 int cadence_qspi_apb_read_execute(struct cadence_spi_priv *priv,
 732                                   const struct spi_mem_op *op)
 733 {
 734         u64 from = op->addr.val;
 735         void *buf = op->data.buf.in;
 736         size_t len = op->data.nbytes;
 737
 738         if (CONFIG_IS_ENABLED(ARCH_VERSAL))
 739                 cadence_qspi_apb_enable_linear_mode(true);
 740
 741         if (priv->use_dac_mode && (from + len < priv->ahbsize)) {
 742                 if (len < 256 ||
 743                     dma_memcpy(buf, priv->ahbbase + from, len) < 0) {
 744                         memcpy_fromio(buf, priv->ahbbase + from, len);
 745                 }
 746                 if (!cadence_qspi_wait_idle(priv->regbase))
 747                         return -EIO;
 748                 return 0;
 749         }
 750
 751         return cadence_qspi_apb_indirect_read_execute(priv, len, buf);
 752 }
 753
 754 /* Opcode + Address (3/4 bytes) */
 755 int cadence_qspi_apb_write_setup(struct cadence_spi_priv *priv,
 756                                  const struct spi_mem_op *op)
 757 {
 758         unsigned int reg;
 759         int ret;
 760         u8 opcode;
 761
 762         ret = cadence_qspi_set_protocol(priv, op);
 763         if (ret)
 764                 return ret;
 765
 766         ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_WRITE_LSB,
 767                                       priv->dtr);
 768         if (ret)
 769                 return ret;
 770
 771         /* Setup the indirect trigger address */
 772         writel(priv->trigger_address,
 773                priv->regbase + CQSPI_REG_INDIRECTTRIGGER);
 774
 775         /* Configure the opcode */
 776         if (priv->dtr)
 777                 opcode = op->cmd.opcode >> 8;
 778         else
 779                 opcode = op->cmd.opcode;
 780
 781         reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 782         reg |= priv->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
 783         reg |= priv->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
 784         writel(reg, priv->regbase + CQSPI_REG_WR_INSTR);
 785
 786         reg = cadence_qspi_calc_rdreg(priv);
 787         writel(reg, priv->regbase + CQSPI_REG_RD_INSTR);
 788
 789         writel(op->addr.val, priv->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
 790
 791         if (priv->dtr) {
 792                 /*
 793                  * Some flashes like the cypress Semper flash expect a 4-byte
 794                  * dummy address with the Read SR command in DTR mode, but this
 795                  * controller does not support sending address with the Read SR
 796                  * command. So, disable write completion polling on the
 797                  * controller's side. spi-nor will take care of polling the
 798                  * status register.
 799                  */
 800                 reg = readl(priv->regbase + CQSPI_REG_WR_COMPLETION_CTRL);
 801                 reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
 802                 writel(reg, priv->regbase + CQSPI_REG_WR_COMPLETION_CTRL);
 803         }
 804
 805         reg = readl(priv->regbase + CQSPI_REG_SIZE);
 806         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 807         reg |= (op->addr.nbytes - 1);
 808         writel(reg, priv->regbase + CQSPI_REG_SIZE);
 809         return 0;
 810 }
 811
 812 static int
 813 cadence_qspi_apb_indirect_write_execute(struct cadence_spi_priv *priv,
 814                                         unsigned int n_tx, const u8 *txbuf)
 815 {
 816         unsigned int page_size = priv->page_size;
 817         unsigned int remaining = n_tx;
 818         const u8 *bb_txbuf = txbuf;
 819         void *bounce_buf = NULL;
 820         unsigned int write_bytes;
 821         int ret;
 822
 823         /*
 824          * Use bounce buffer for non 32 bit aligned txbuf to avoid data
 825          * aborts
 826          */
 827         if ((uintptr_t)txbuf % 4) {
 828                 bounce_buf = malloc(n_tx);
 829                 if (!bounce_buf)
 830                         return -ENOMEM;
 831                 memcpy(bounce_buf, txbuf, n_tx);
 832                 bb_txbuf = bounce_buf;
 833         }
 834
 835         /* Configure the indirect read transfer bytes */
 836         writel(n_tx, priv->regbase + CQSPI_REG_INDIRECTWRBYTES);
 837
 838         /* Start the indirect write transfer */
 839         writel(CQSPI_REG_INDIRECTWR_START,
 840                priv->regbase + CQSPI_REG_INDIRECTWR);
 841
 842         /*
 843          * Some delay is required for the above bit to be internally
 844          * synchronized by the QSPI module.
 845          */
 846         ndelay(priv->wr_delay);
 847
 848         while (remaining > 0) {
 849                 write_bytes = remaining > page_size ? page_size : remaining;
 850                 writesl(priv->ahbbase, bb_txbuf, write_bytes >> 2);
 851                 if (write_bytes % 4)
 852                         writesb(priv->ahbbase,
 853                                 bb_txbuf + rounddown(write_bytes, 4),
 854                                 write_bytes % 4);
 855
 856                 ret = wait_for_bit_le32(priv->regbase + CQSPI_REG_SDRAMLEVEL,
 857                                         CQSPI_REG_SDRAMLEVEL_WR_MASK <<
 858                                         CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
 859                 if (ret) {
 860                         printf("Indirect write timed out (%i)\n", ret);
 861                         goto failwr;
 862                 }
 863
 864                 bb_txbuf += write_bytes;
 865                 remaining -= write_bytes;
 866         }
 867
 868         /* Check indirect done status */
 869         ret = wait_for_bit_le32(priv->regbase + CQSPI_REG_INDIRECTWR,
 870                                 CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
 871         if (ret) {
 872                 printf("Indirect write completion error (%i)\n", ret);
 873                 goto failwr;
 874         }
 875
 876         /* Clear indirect completion status */
 877         writel(CQSPI_REG_INDIRECTWR_DONE,
 878                priv->regbase + CQSPI_REG_INDIRECTWR);
 879
 880         /* Check indirect done status */
 881         ret = wait_for_bit_le32(priv->regbase + CQSPI_REG_INDIRECTWR,
 882                                 CQSPI_REG_INDIRECTWR_DONE, 0, 10, 0);
 883         if (ret) {
 884                 printf("Indirect write clear completion error (%i)\n", ret);
 885                 goto failwr;
 886         }
 887
 888         if (bounce_buf)
 889                 free(bounce_buf);
 890         return 0;
 891
 892 failwr:
 893         /* Cancel the indirect write */
 894         writel(CQSPI_REG_INDIRECTWR_CANCEL,
 895                priv->regbase + CQSPI_REG_INDIRECTWR);
 896         if (bounce_buf)
 897                 free(bounce_buf);
 898         return ret;
 899 }
 900
 901 int cadence_qspi_apb_write_execute(struct cadence_spi_priv *priv,
 902                                    const struct spi_mem_op *op)
 903 {
 904         u32 to = op->addr.val;
 905         const void *buf = op->data.buf.out;
 906         size_t len = op->data.nbytes;
 907
 908         if (CONFIG_IS_ENABLED(ARCH_VERSAL))
 909                 cadence_qspi_apb_enable_linear_mode(true);
 910
 911         /*
 912          * Some flashes like the Cypress Semper flash expect a dummy 4-byte
 913          * address (all 0s) with the read status register command in DTR mode.
 914          * But this controller does not support sending dummy address bytes to
 915          * the flash when it is polling the write completion register in DTR
 916          * mode. So, we can not use direct mode when in DTR mode for writing
 917          * data.
 918          */
 919         cadence_qspi_apb_enable_linear_mode(true);
 920         if (!priv->dtr && priv->use_dac_mode && (to + len < priv->ahbsize)) {
 921                 memcpy_toio(priv->ahbbase + to, buf, len);
 922                 if (!cadence_qspi_wait_idle(priv->regbase))
 923                         return -EIO;
 924                 return 0;
 925         }
 926
 927         return cadence_qspi_apb_indirect_write_execute(priv, len, buf);
 928 }
 929
 930 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
 931 {
 932         unsigned int reg;
 933
 934         /* enter XiP mode immediately and enable direct mode */
 935         reg = readl(reg_base + CQSPI_REG_CONFIG);
 936         reg |= CQSPI_REG_CONFIG_ENABLE;
 937         reg |= CQSPI_REG_CONFIG_DIRECT;
 938         reg |= CQSPI_REG_CONFIG_XIP_IMM;
 939         writel(reg, reg_base + CQSPI_REG_CONFIG);
 940
 941         /* keep the XiP mode */
 942         writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
 943
 944         /* Enable mode bit at devrd */
 945         reg = readl(reg_base + CQSPI_REG_RD_INSTR);
 946         reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 947         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 948 }