drivers/spi/cadence_qspi_apb.c

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *  - Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  *  - Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *  - Neither the name of the Altera Corporation nor the
  13  *    names of its contributors may be used to endorse or promote products
  14  *    derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include <common.h>
  29 #include <asm/io.h>
  30 #include <dma.h>
  31 #include <linux/errno.h>
  32 #include <wait_bit.h>
  33 #include <spi.h>
  34 #include <spi-mem.h>
  35 #include <malloc.h>
  36 #include "cadence_qspi.h"
  37
  38 #define CQSPI_REG_POLL_US                       1 /* 1us */
  39 #define CQSPI_REG_RETRY                         10000
  40 #define CQSPI_POLL_IDLE_RETRY                   3
  41
  42 /* Transfer mode */
  43 #define CQSPI_INST_TYPE_SINGLE                  0
  44 #define CQSPI_INST_TYPE_DUAL                    1
  45 #define CQSPI_INST_TYPE_QUAD                    2
  46 #define CQSPI_INST_TYPE_OCTAL                   3
  47
  48 #define CQSPI_STIG_DATA_LEN_MAX                 8
  49
  50 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
  51 #define CQSPI_DUMMY_BYTES_MAX                   4
  52
  53 /****************************************************************************
  54  * Controller's configuration and status register (offset from QSPI_BASE)
  55  ****************************************************************************/
  56 #define CQSPI_REG_CONFIG                        0x00
  57 #define CQSPI_REG_CONFIG_ENABLE                 BIT(0)
  58 #define CQSPI_REG_CONFIG_CLK_POL                BIT(1)
  59 #define CQSPI_REG_CONFIG_CLK_PHA                BIT(2)
  60 #define CQSPI_REG_CONFIG_DIRECT                 BIT(7)
  61 #define CQSPI_REG_CONFIG_DECODE                 BIT(9)
  62 #define CQSPI_REG_CONFIG_XIP_IMM                BIT(18)
  63 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
  64 #define CQSPI_REG_CONFIG_BAUD_LSB               19
  65 #define CQSPI_REG_CONFIG_IDLE_LSB               31
  66 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
  67 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
  68
  69 #define CQSPI_REG_RD_INSTR                      0x04
  70 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
  71 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
  72 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
  73 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
  74 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
  75 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
  76 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
  77 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
  78 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
  79 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
  80
  81 #define CQSPI_REG_WR_INSTR                      0x08
  82 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
  83 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
  84
  85 #define CQSPI_REG_DELAY                         0x0C
  86 #define CQSPI_REG_DELAY_TSLCH_LSB               0
  87 #define CQSPI_REG_DELAY_TCHSH_LSB               8
  88 #define CQSPI_REG_DELAY_TSD2D_LSB               16
  89 #define CQSPI_REG_DELAY_TSHSL_LSB               24
  90 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
  91 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
  92 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
  93 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
  94
  95 #define CQSPI_REG_RD_DATA_CAPTURE               0x10
  96 #define CQSPI_REG_RD_DATA_CAPTURE_BYPASS        BIT(0)
  97 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB     1
  98 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK    0xF
  99
 100 #define CQSPI_REG_SIZE                          0x14
 101 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 102 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 103 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 104 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 105 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 106 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 107
 108 #define CQSPI_REG_SRAMPARTITION                 0x18
 109 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 110
 111 #define CQSPI_REG_REMAP                         0x24
 112 #define CQSPI_REG_MODE_BIT                      0x28
 113
 114 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 115 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 116 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 117 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 118 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 119
 120 #define CQSPI_REG_IRQSTATUS                     0x40
 121 #define CQSPI_REG_IRQMASK                       0x44
 122
 123 #define CQSPI_REG_INDIRECTRD                    0x60
 124 #define CQSPI_REG_INDIRECTRD_START              BIT(0)
 125 #define CQSPI_REG_INDIRECTRD_CANCEL             BIT(1)
 126 #define CQSPI_REG_INDIRECTRD_INPROGRESS         BIT(2)
 127 #define CQSPI_REG_INDIRECTRD_DONE               BIT(5)
 128
 129 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 130 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 131 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 132
 133 #define CQSPI_REG_CMDCTRL                       0x90
 134 #define CQSPI_REG_CMDCTRL_EXECUTE               BIT(0)
 135 #define CQSPI_REG_CMDCTRL_INPROGRESS            BIT(1)
 136 #define CQSPI_REG_CMDCTRL_DUMMY_LSB             7
 137 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 138 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 139 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 140 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 141 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 142 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 143 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 144 #define CQSPI_REG_CMDCTRL_DUMMY_MASK            0x1F
 145 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 146 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 147 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 148 #define CQSPI_REG_CMDCTRL_OPCODE_MASK           0xFF
 149
 150 #define CQSPI_REG_INDIRECTWR                    0x70
 151 #define CQSPI_REG_INDIRECTWR_START              BIT(0)
 152 #define CQSPI_REG_INDIRECTWR_CANCEL             BIT(1)
 153 #define CQSPI_REG_INDIRECTWR_INPROGRESS         BIT(2)
 154 #define CQSPI_REG_INDIRECTWR_DONE               BIT(5)
 155
 156 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 157 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 158 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 159
 160 #define CQSPI_REG_CMDADDRESS                    0x94
 161 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 162 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 163 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 164 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 165
 166 #define CQSPI_REG_IS_IDLE(base)                                 \
 167         ((readl(base + CQSPI_REG_CONFIG) >>             \
 168                 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
 169
 170 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base)                       \
 171         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 172         CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
 173
 174 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base)                       \
 175         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 176         CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
 177
 178 void cadence_qspi_apb_controller_enable(void *reg_base)
 179 {
 180         unsigned int reg;
 181         reg = readl(reg_base + CQSPI_REG_CONFIG);
 182         reg |= CQSPI_REG_CONFIG_ENABLE;
 183         writel(reg, reg_base + CQSPI_REG_CONFIG);
 184 }
 185
 186 void cadence_qspi_apb_controller_disable(void *reg_base)
 187 {
 188         unsigned int reg;
 189         reg = readl(reg_base + CQSPI_REG_CONFIG);
 190         reg &= ~CQSPI_REG_CONFIG_ENABLE;
 191         writel(reg, reg_base + CQSPI_REG_CONFIG);
 192 }
 193
 194 void cadence_qspi_apb_dac_mode_enable(void *reg_base)
 195 {
 196         unsigned int reg;
 197
 198         reg = readl(reg_base + CQSPI_REG_CONFIG);
 199         reg |= CQSPI_REG_CONFIG_DIRECT;
 200         writel(reg, reg_base + CQSPI_REG_CONFIG);
 201 }
 202
 203 /* Return 1 if idle, otherwise return 0 (busy). */
 204 static unsigned int cadence_qspi_wait_idle(void *reg_base)
 205 {
 206         unsigned int start, count = 0;
 207         /* timeout in unit of ms */
 208         unsigned int timeout = 5000;
 209
 210         start = get_timer(0);
 211         for ( ; get_timer(start) < timeout ; ) {
 212                 if (CQSPI_REG_IS_IDLE(reg_base))
 213                         count++;
 214                 else
 215                         count = 0;
 216                 /*
 217                  * Ensure the QSPI controller is in true idle state after
 218                  * reading back the same idle status consecutively
 219                  */
 220                 if (count >= CQSPI_POLL_IDLE_RETRY)
 221                         return 1;
 222         }
 223
 224         /* Timeout, still in busy mode. */
 225         printf("QSPI: QSPI is still busy after poll for %d times.\n",
 226                CQSPI_REG_RETRY);
 227         return 0;
 228 }
 229
 230 void cadence_qspi_apb_readdata_capture(void *reg_base,
 231                                 unsigned int bypass, unsigned int delay)
 232 {
 233         unsigned int reg;
 234         cadence_qspi_apb_controller_disable(reg_base);
 235
 236         reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
 237
 238         if (bypass)
 239                 reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
 240         else
 241                 reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
 242
 243         reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
 244                 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
 245
 246         reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
 247                 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
 248
 249         writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
 250
 251         cadence_qspi_apb_controller_enable(reg_base);
 252 }
 253
 254 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
 255         unsigned int ref_clk_hz, unsigned int sclk_hz)
 256 {
 257         unsigned int reg;
 258         unsigned int div;
 259
 260         cadence_qspi_apb_controller_disable(reg_base);
 261         reg = readl(reg_base + CQSPI_REG_CONFIG);
 262         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 263
 264         /*
 265          * The baud_div field in the config reg is 4 bits, and the ref clock is
 266          * divided by 2 * (baud_div + 1). Round up the divider to ensure the
 267          * SPI clock rate is less than or equal to the requested clock rate.
 268          */
 269         div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
 270
 271         /* ensure the baud rate doesn't exceed the max value */
 272         if (div > CQSPI_REG_CONFIG_BAUD_MASK)
 273                 div = CQSPI_REG_CONFIG_BAUD_MASK;
 274
 275         debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
 276               ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
 277
 278         reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
 279         writel(reg, reg_base + CQSPI_REG_CONFIG);
 280
 281         cadence_qspi_apb_controller_enable(reg_base);
 282 }
 283
 284 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
 285 {
 286         unsigned int reg;
 287
 288         cadence_qspi_apb_controller_disable(reg_base);
 289         reg = readl(reg_base + CQSPI_REG_CONFIG);
 290         reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
 291
 292         if (mode & SPI_CPOL)
 293                 reg |= CQSPI_REG_CONFIG_CLK_POL;
 294         if (mode & SPI_CPHA)
 295                 reg |= CQSPI_REG_CONFIG_CLK_PHA;
 296
 297         writel(reg, reg_base + CQSPI_REG_CONFIG);
 298
 299         cadence_qspi_apb_controller_enable(reg_base);
 300 }
 301
 302 void cadence_qspi_apb_chipselect(void *reg_base,
 303         unsigned int chip_select, unsigned int decoder_enable)
 304 {
 305         unsigned int reg;
 306
 307         cadence_qspi_apb_controller_disable(reg_base);
 308
 309         debug("%s : chipselect %d decode %d\n", __func__, chip_select,
 310               decoder_enable);
 311
 312         reg = readl(reg_base + CQSPI_REG_CONFIG);
 313         /* docoder */
 314         if (decoder_enable) {
 315                 reg |= CQSPI_REG_CONFIG_DECODE;
 316         } else {
 317                 reg &= ~CQSPI_REG_CONFIG_DECODE;
 318                 /* Convert CS if without decoder.
 319                  * CS0 to 4b'1110
 320                  * CS1 to 4b'1101
 321                  * CS2 to 4b'1011
 322                  * CS3 to 4b'0111
 323                  */
 324                 chip_select = 0xF & ~(1 << chip_select);
 325         }
 326
 327         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 328                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 329         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 330                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 331         writel(reg, reg_base + CQSPI_REG_CONFIG);
 332
 333         cadence_qspi_apb_controller_enable(reg_base);
 334 }
 335
 336 void cadence_qspi_apb_delay(void *reg_base,
 337         unsigned int ref_clk, unsigned int sclk_hz,
 338         unsigned int tshsl_ns, unsigned int tsd2d_ns,
 339         unsigned int tchsh_ns, unsigned int tslch_ns)
 340 {
 341         unsigned int ref_clk_ns;
 342         unsigned int sclk_ns;
 343         unsigned int tshsl, tchsh, tslch, tsd2d;
 344         unsigned int reg;
 345
 346         cadence_qspi_apb_controller_disable(reg_base);
 347
 348         /* Convert to ns. */
 349         ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
 350
 351         /* Convert to ns. */
 352         sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
 353
 354         /* The controller adds additional delay to that programmed in the reg */
 355         if (tshsl_ns >= sclk_ns + ref_clk_ns)
 356                 tshsl_ns -= sclk_ns + ref_clk_ns;
 357         if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
 358                 tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
 359         tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
 360         tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
 361         tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
 362         tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
 363
 364         reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 365                         << CQSPI_REG_DELAY_TSHSL_LSB);
 366         reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 367                         << CQSPI_REG_DELAY_TCHSH_LSB);
 368         reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 369                         << CQSPI_REG_DELAY_TSLCH_LSB);
 370         reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 371                         << CQSPI_REG_DELAY_TSD2D_LSB);
 372         writel(reg, reg_base + CQSPI_REG_DELAY);
 373
 374         cadence_qspi_apb_controller_enable(reg_base);
 375 }
 376
 377 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
 378 {
 379         unsigned reg;
 380
 381         cadence_qspi_apb_controller_disable(plat->regbase);
 382
 383         /* Configure the device size and address bytes */
 384         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 385         /* Clear the previous value */
 386         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 387         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 388         reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 389         reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
 390         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 391
 392         /* Configure the remap address register, no remap */
 393         writel(0, plat->regbase + CQSPI_REG_REMAP);
 394
 395         /* Indirect mode configurations */
 396         writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION);
 397
 398         /* Disable all interrupts */
 399         writel(0, plat->regbase + CQSPI_REG_IRQMASK);
 400
 401         cadence_qspi_apb_controller_enable(plat->regbase);
 402 }
 403
 404 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
 405         unsigned int reg)
 406 {
 407         unsigned int retry = CQSPI_REG_RETRY;
 408
 409         /* Write the CMDCTRL without start execution. */
 410         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 411         /* Start execute */
 412         reg |= CQSPI_REG_CMDCTRL_EXECUTE;
 413         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 414
 415         while (retry--) {
 416                 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
 417                 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
 418                         break;
 419                 udelay(1);
 420         }
 421
 422         if (!retry) {
 423                 printf("QSPI: flash command execution timeout\n");
 424                 return -EIO;
 425         }
 426
 427         /* Polling QSPI idle status. */
 428         if (!cadence_qspi_wait_idle(reg_base))
 429                 return -EIO;
 430
 431         return 0;
 432 }
 433
 434 /* For command RDID, RDSR. */
 435 int cadence_qspi_apb_command_read(void *reg_base, const struct spi_mem_op *op)
 436 {
 437         unsigned int reg;
 438         unsigned int read_len;
 439         int status;
 440         unsigned int rxlen = op->data.nbytes;
 441         void *rxbuf = op->data.buf.in;
 442
 443         if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 444                 printf("QSPI: Invalid input arguments rxlen %u\n", rxlen);
 445                 return -EINVAL;
 446         }
 447
 448         reg = op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 449
 450         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 451
 452         /* 0 means 1 byte. */
 453         reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 454                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 455         status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 456         if (status != 0)
 457                 return status;
 458
 459         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 460
 461         /* Put the read value into rx_buf */
 462         read_len = (rxlen > 4) ? 4 : rxlen;
 463         memcpy(rxbuf, &reg, read_len);
 464         rxbuf += read_len;
 465
 466         if (rxlen > 4) {
 467                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 468
 469                 read_len = rxlen - read_len;
 470                 memcpy(rxbuf, &reg, read_len);
 471         }
 472         return 0;
 473 }
 474
 475 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
 476 int cadence_qspi_apb_command_write(void *reg_base, const struct spi_mem_op *op)
 477 {
 478         unsigned int reg = 0;
 479         unsigned int wr_data;
 480         unsigned int wr_len;
 481         unsigned int txlen = op->data.nbytes;
 482         const void *txbuf = op->data.buf.out;
 483         u32 addr;
 484
 485         /* Reorder address to SPI bus order if only transferring address */
 486         if (!txlen) {
 487                 addr = cpu_to_be32(op->addr.val);
 488                 if (op->addr.nbytes == 3)
 489                         addr >>= 8;
 490                 txbuf = &addr;
 491                 txlen = op->addr.nbytes;
 492         }
 493
 494         if (txlen > CQSPI_STIG_DATA_LEN_MAX) {
 495                 printf("QSPI: Invalid input arguments txlen %u\n", txlen);
 496                 return -EINVAL;
 497         }
 498
 499         reg |= op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 500
 501         if (txlen) {
 502                 /* writing data = yes */
 503                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 504                 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 505                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 506
 507                 wr_len = txlen > 4 ? 4 : txlen;
 508                 memcpy(&wr_data, txbuf, wr_len);
 509                 writel(wr_data, reg_base +
 510                         CQSPI_REG_CMDWRITEDATALOWER);
 511
 512                 if (txlen > 4) {
 513                         txbuf += wr_len;
 514                         wr_len = txlen - wr_len;
 515                         memcpy(&wr_data, txbuf, wr_len);
 516                         writel(wr_data, reg_base +
 517                                 CQSPI_REG_CMDWRITEDATAUPPER);
 518                 }
 519         }
 520
 521         /* Execute the command */
 522         return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 523 }
 524
 525 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
 526 int cadence_qspi_apb_read_setup(struct cadence_spi_platdata *plat,
 527                                 const struct spi_mem_op *op)
 528 {
 529         unsigned int reg;
 530         unsigned int rd_reg;
 531         unsigned int dummy_clk;
 532         unsigned int dummy_bytes = op->dummy.nbytes;
 533
 534         /* Setup the indirect trigger address */
 535         writel(plat->trigger_address,
 536                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 537
 538         /* Configure the opcode */
 539         rd_reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 540
 541         if (op->data.buswidth == 8)
 542                 /* Instruction and address at DQ0, data at DQ0-7. */
 543                 rd_reg |= CQSPI_INST_TYPE_OCTAL << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 544         else if (op->data.buswidth == 4)
 545                 /* Instruction and address at DQ0, data at DQ0-3. */
 546                 rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 547
 548         writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
 549
 550         if (dummy_bytes) {
 551                 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
 552                         dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
 553
 554                 /* Convert to clock cycles. */
 555                 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
 556
 557                 if (dummy_clk)
 558                         rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 559                                 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 560         }
 561
 562         writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
 563
 564         /* set device size */
 565         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 566         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 567         reg |= (op->addr.nbytes - 1);
 568         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 569         return 0;
 570 }
 571
 572 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
 573 {
 574         u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
 575         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 576         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 577 }
 578
 579 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
 580 {
 581         unsigned int timeout = 10000;
 582         u32 reg;
 583
 584         while (timeout--) {
 585                 reg = cadence_qspi_get_rd_sram_level(plat);
 586                 if (reg)
 587                         return reg;
 588                 udelay(1);
 589         }
 590
 591         return -ETIMEDOUT;
 592 }
 593
 594 static int
 595 cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
 596                                        unsigned int n_rx, u8 *rxbuf)
 597 {
 598         unsigned int remaining = n_rx;
 599         unsigned int bytes_to_read = 0;
 600         int ret;
 601
 602         writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
 603
 604         /* Start the indirect read transfer */
 605         writel(CQSPI_REG_INDIRECTRD_START,
 606                plat->regbase + CQSPI_REG_INDIRECTRD);
 607
 608         while (remaining > 0) {
 609                 ret = cadence_qspi_wait_for_data(plat);
 610                 if (ret < 0) {
 611                         printf("Indirect write timed out (%i)\n", ret);
 612                         goto failrd;
 613                 }
 614
 615                 bytes_to_read = ret;
 616
 617                 while (bytes_to_read != 0) {
 618                         bytes_to_read *= plat->fifo_width;
 619                         bytes_to_read = bytes_to_read > remaining ?
 620                                         remaining : bytes_to_read;
 621                         /*
 622                          * Handle non-4-byte aligned access to avoid
 623                          * data abort.
 624                          */
 625                         if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
 626                                 readsb(plat->ahbbase, rxbuf, bytes_to_read);
 627                         else
 628                                 readsl(plat->ahbbase, rxbuf,
 629                                        bytes_to_read >> 2);
 630                         rxbuf += bytes_to_read;
 631                         remaining -= bytes_to_read;
 632                         bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
 633                 }
 634         }
 635
 636         /* Check indirect done status */
 637         ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
 638                                 CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
 639         if (ret) {
 640                 printf("Indirect read completion error (%i)\n", ret);
 641                 goto failrd;
 642         }
 643
 644         /* Clear indirect completion status */
 645         writel(CQSPI_REG_INDIRECTRD_DONE,
 646                plat->regbase + CQSPI_REG_INDIRECTRD);
 647
 648         return 0;
 649
 650 failrd:
 651         /* Cancel the indirect read */
 652         writel(CQSPI_REG_INDIRECTRD_CANCEL,
 653                plat->regbase + CQSPI_REG_INDIRECTRD);
 654         return ret;
 655 }
 656
 657 int cadence_qspi_apb_read_execute(struct cadence_spi_platdata *plat,
 658                                   const struct spi_mem_op *op)
 659 {
 660         u64 from = op->addr.val;
 661         void *buf = op->data.buf.in;
 662         size_t len = op->data.nbytes;
 663
 664         if (plat->use_dac_mode && (from + len < plat->ahbsize)) {
 665                 if (len < 256 ||
 666                     dma_memcpy(buf, plat->ahbbase + from, len) < 0) {
 667                         memcpy_fromio(buf, plat->ahbbase + from, len);
 668                 }
 669                 if (!cadence_qspi_wait_idle(plat->regbase))
 670                         return -EIO;
 671                 return 0;
 672         }
 673
 674         return cadence_qspi_apb_indirect_read_execute(plat, len, buf);
 675 }
 676
 677 /* Opcode + Address (3/4 bytes) */
 678 int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat,
 679                                  const struct spi_mem_op *op)
 680 {
 681         unsigned int reg;
 682
 683         /* Setup the indirect trigger address */
 684         writel(plat->trigger_address,
 685                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 686
 687         /* Configure the opcode */
 688         reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 689         writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
 690
 691         writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
 692
 693         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 694         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 695         reg |= (op->addr.nbytes - 1);
 696         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 697         return 0;
 698 }
 699
 700 static int
 701 cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
 702                                         unsigned int n_tx, const u8 *txbuf)
 703 {
 704         unsigned int page_size = plat->page_size;
 705         unsigned int remaining = n_tx;
 706         const u8 *bb_txbuf = txbuf;
 707         void *bounce_buf = NULL;
 708         unsigned int write_bytes;
 709         int ret;
 710
 711         /*
 712          * Use bounce buffer for non 32 bit aligned txbuf to avoid data
 713          * aborts
 714          */
 715         if ((uintptr_t)txbuf % 4) {
 716                 bounce_buf = malloc(n_tx);
 717                 if (!bounce_buf)
 718                         return -ENOMEM;
 719                 memcpy(bounce_buf, txbuf, n_tx);
 720                 bb_txbuf = bounce_buf;
 721         }
 722
 723         /* Configure the indirect read transfer bytes */
 724         writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
 725
 726         /* Start the indirect write transfer */
 727         writel(CQSPI_REG_INDIRECTWR_START,
 728                plat->regbase + CQSPI_REG_INDIRECTWR);
 729
 730         while (remaining > 0) {
 731                 write_bytes = remaining > page_size ? page_size : remaining;
 732                 writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
 733                 if (write_bytes % 4)
 734                         writesb(plat->ahbbase,
 735                                 bb_txbuf + rounddown(write_bytes, 4),
 736                                 write_bytes % 4);
 737
 738                 ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,
 739                                         CQSPI_REG_SDRAMLEVEL_WR_MASK <<
 740                                         CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
 741                 if (ret) {
 742                         printf("Indirect write timed out (%i)\n", ret);
 743                         goto failwr;
 744                 }
 745
 746                 bb_txbuf += write_bytes;
 747                 remaining -= write_bytes;
 748         }
 749
 750         /* Check indirect done status */
 751         ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
 752                                 CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
 753         if (ret) {
 754                 printf("Indirect write completion error (%i)\n", ret);
 755                 goto failwr;
 756         }
 757
 758         /* Clear indirect completion status */
 759         writel(CQSPI_REG_INDIRECTWR_DONE,
 760                plat->regbase + CQSPI_REG_INDIRECTWR);
 761         if (bounce_buf)
 762                 free(bounce_buf);
 763         return 0;
 764
 765 failwr:
 766         /* Cancel the indirect write */
 767         writel(CQSPI_REG_INDIRECTWR_CANCEL,
 768                plat->regbase + CQSPI_REG_INDIRECTWR);
 769         if (bounce_buf)
 770                 free(bounce_buf);
 771         return ret;
 772 }
 773
 774 int cadence_qspi_apb_write_execute(struct cadence_spi_platdata *plat,
 775                                    const struct spi_mem_op *op)
 776 {
 777         u32 to = op->addr.val;
 778         const void *buf = op->data.buf.out;
 779         size_t len = op->data.nbytes;
 780
 781         if (plat->use_dac_mode && (to + len < plat->ahbsize)) {
 782                 memcpy_toio(plat->ahbbase + to, buf, len);
 783                 if (!cadence_qspi_wait_idle(plat->regbase))
 784                         return -EIO;
 785                 return 0;
 786         }
 787
 788         return cadence_qspi_apb_indirect_write_execute(plat, len, buf);
 789 }
 790
 791 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
 792 {
 793         unsigned int reg;
 794
 795         /* enter XiP mode immediately and enable direct mode */
 796         reg = readl(reg_base + CQSPI_REG_CONFIG);
 797         reg |= CQSPI_REG_CONFIG_ENABLE;
 798         reg |= CQSPI_REG_CONFIG_DIRECT;
 799         reg |= CQSPI_REG_CONFIG_XIP_IMM;
 800         writel(reg, reg_base + CQSPI_REG_CONFIG);
 801
 802         /* keep the XiP mode */
 803         writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
 804
 805         /* Enable mode bit at devrd */
 806         reg = readl(reg_base + CQSPI_REG_RD_INSTR);
 807         reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 808         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 809 }