drivers/spi/cadence_qspi_apb.c

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *  - Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  *  - Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *  - Neither the name of the Altera Corporation nor the
  13  *    names of its contributors may be used to endorse or promote products
  14  *    derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include <common.h>
  29 #include <asm/io.h>
  30 #include <linux/errno.h>
  31 #include <wait_bit.h>
  32 #include <spi.h>
  33 #include <malloc.h>
  34 #include "cadence_qspi.h"
  35
  36 #define CQSPI_REG_POLL_US                       1 /* 1us */
  37 #define CQSPI_REG_RETRY                         10000
  38 #define CQSPI_POLL_IDLE_RETRY                   3
  39
  40 /* Transfer mode */
  41 #define CQSPI_INST_TYPE_SINGLE                  0
  42 #define CQSPI_INST_TYPE_DUAL                    1
  43 #define CQSPI_INST_TYPE_QUAD                    2
  44
  45 #define CQSPI_STIG_DATA_LEN_MAX                 8
  46
  47 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
  48 #define CQSPI_DUMMY_BYTES_MAX                   4
  49
  50 /****************************************************************************
  51  * Controller's configuration and status register (offset from QSPI_BASE)
  52  ****************************************************************************/
  53 #define CQSPI_REG_CONFIG                        0x00
  54 #define CQSPI_REG_CONFIG_ENABLE                 BIT(0)
  55 #define CQSPI_REG_CONFIG_CLK_POL                BIT(1)
  56 #define CQSPI_REG_CONFIG_CLK_PHA                BIT(2)
  57 #define CQSPI_REG_CONFIG_DIRECT                 BIT(7)
  58 #define CQSPI_REG_CONFIG_DECODE                 BIT(9)
  59 #define CQSPI_REG_CONFIG_XIP_IMM                BIT(18)
  60 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
  61 #define CQSPI_REG_CONFIG_BAUD_LSB               19
  62 #define CQSPI_REG_CONFIG_IDLE_LSB               31
  63 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
  64 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
  65
  66 #define CQSPI_REG_RD_INSTR                      0x04
  67 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
  68 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
  69 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
  70 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
  71 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
  72 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
  73 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
  74 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
  75 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
  76 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
  77
  78 #define CQSPI_REG_WR_INSTR                      0x08
  79 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
  80
  81 #define CQSPI_REG_DELAY                         0x0C
  82 #define CQSPI_REG_DELAY_TSLCH_LSB               0
  83 #define CQSPI_REG_DELAY_TCHSH_LSB               8
  84 #define CQSPI_REG_DELAY_TSD2D_LSB               16
  85 #define CQSPI_REG_DELAY_TSHSL_LSB               24
  86 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
  87 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
  88 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
  89 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
  90
  91 #define CQSPI_REG_RD_DATA_CAPTURE               0x10
  92 #define CQSPI_REG_RD_DATA_CAPTURE_BYPASS        BIT(0)
  93 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB     1
  94 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK    0xF
  95
  96 #define CQSPI_REG_SIZE                          0x14
  97 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
  98 #define CQSPI_REG_SIZE_PAGE_LSB                 4
  99 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 100 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 101 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 102 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 103
 104 #define CQSPI_REG_SRAMPARTITION                 0x18
 105 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 106
 107 #define CQSPI_REG_REMAP                         0x24
 108 #define CQSPI_REG_MODE_BIT                      0x28
 109
 110 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 111 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 112 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 113 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 114 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 115
 116 #define CQSPI_REG_IRQSTATUS                     0x40
 117 #define CQSPI_REG_IRQMASK                       0x44
 118
 119 #define CQSPI_REG_INDIRECTRD                    0x60
 120 #define CQSPI_REG_INDIRECTRD_START              BIT(0)
 121 #define CQSPI_REG_INDIRECTRD_CANCEL             BIT(1)
 122 #define CQSPI_REG_INDIRECTRD_INPROGRESS         BIT(2)
 123 #define CQSPI_REG_INDIRECTRD_DONE               BIT(5)
 124
 125 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 126 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 127 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 128
 129 #define CQSPI_REG_CMDCTRL                       0x90
 130 #define CQSPI_REG_CMDCTRL_EXECUTE               BIT(0)
 131 #define CQSPI_REG_CMDCTRL_INPROGRESS            BIT(1)
 132 #define CQSPI_REG_CMDCTRL_DUMMY_LSB             7
 133 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 134 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 135 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 136 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 137 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 138 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 139 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 140 #define CQSPI_REG_CMDCTRL_DUMMY_MASK            0x1F
 141 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 142 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 143 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 144 #define CQSPI_REG_CMDCTRL_OPCODE_MASK           0xFF
 145
 146 #define CQSPI_REG_INDIRECTWR                    0x70
 147 #define CQSPI_REG_INDIRECTWR_START              BIT(0)
 148 #define CQSPI_REG_INDIRECTWR_CANCEL             BIT(1)
 149 #define CQSPI_REG_INDIRECTWR_INPROGRESS         BIT(2)
 150 #define CQSPI_REG_INDIRECTWR_DONE               BIT(5)
 151
 152 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 153 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 154 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 155
 156 #define CQSPI_REG_CMDADDRESS                    0x94
 157 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 158 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 159 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 160 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 161
 162 #define CQSPI_REG_IS_IDLE(base)                                 \
 163         ((readl(base + CQSPI_REG_CONFIG) >>             \
 164                 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
 165
 166 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base)                       \
 167         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 168         CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
 169
 170 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base)                       \
 171         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 172         CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
 173
 174 static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
 175         unsigned int addr_width)
 176 {
 177         unsigned int addr;
 178
 179         addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
 180
 181         if (addr_width == 4)
 182                 addr = (addr << 8) | addr_buf[3];
 183
 184         return addr;
 185 }
 186
 187 void cadence_qspi_apb_controller_enable(void *reg_base)
 188 {
 189         unsigned int reg;
 190         reg = readl(reg_base + CQSPI_REG_CONFIG);
 191         reg |= CQSPI_REG_CONFIG_ENABLE;
 192         writel(reg, reg_base + CQSPI_REG_CONFIG);
 193 }
 194
 195 void cadence_qspi_apb_controller_disable(void *reg_base)
 196 {
 197         unsigned int reg;
 198         reg = readl(reg_base + CQSPI_REG_CONFIG);
 199         reg &= ~CQSPI_REG_CONFIG_ENABLE;
 200         writel(reg, reg_base + CQSPI_REG_CONFIG);
 201 }
 202
 203 /* Return 1 if idle, otherwise return 0 (busy). */
 204 static unsigned int cadence_qspi_wait_idle(void *reg_base)
 205 {
 206         unsigned int start, count = 0;
 207         /* timeout in unit of ms */
 208         unsigned int timeout = 5000;
 209
 210         start = get_timer(0);
 211         for ( ; get_timer(start) < timeout ; ) {
 212                 if (CQSPI_REG_IS_IDLE(reg_base))
 213                         count++;
 214                 else
 215                         count = 0;
 216                 /*
 217                  * Ensure the QSPI controller is in true idle state after
 218                  * reading back the same idle status consecutively
 219                  */
 220                 if (count >= CQSPI_POLL_IDLE_RETRY)
 221                         return 1;
 222         }
 223
 224         /* Timeout, still in busy mode. */
 225         printf("QSPI: QSPI is still busy after poll for %d times.\n",
 226                CQSPI_REG_RETRY);
 227         return 0;
 228 }
 229
 230 void cadence_qspi_apb_readdata_capture(void *reg_base,
 231                                 unsigned int bypass, unsigned int delay)
 232 {
 233         unsigned int reg;
 234         cadence_qspi_apb_controller_disable(reg_base);
 235
 236         reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
 237
 238         if (bypass)
 239                 reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
 240         else
 241                 reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
 242
 243         reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
 244                 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
 245
 246         reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
 247                 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
 248
 249         writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
 250
 251         cadence_qspi_apb_controller_enable(reg_base);
 252 }
 253
 254 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
 255         unsigned int ref_clk_hz, unsigned int sclk_hz)
 256 {
 257         unsigned int reg;
 258         unsigned int div;
 259
 260         cadence_qspi_apb_controller_disable(reg_base);
 261         reg = readl(reg_base + CQSPI_REG_CONFIG);
 262         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 263
 264         /*
 265          * The baud_div field in the config reg is 4 bits, and the ref clock is
 266          * divided by 2 * (baud_div + 1). Round up the divider to ensure the
 267          * SPI clock rate is less than or equal to the requested clock rate.
 268          */
 269         div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
 270
 271         /* ensure the baud rate doesn't exceed the max value */
 272         if (div > CQSPI_REG_CONFIG_BAUD_MASK)
 273                 div = CQSPI_REG_CONFIG_BAUD_MASK;
 274
 275         debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
 276               ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
 277
 278         reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
 279         writel(reg, reg_base + CQSPI_REG_CONFIG);
 280
 281         cadence_qspi_apb_controller_enable(reg_base);
 282 }
 283
 284 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
 285 {
 286         unsigned int reg;
 287
 288         cadence_qspi_apb_controller_disable(reg_base);
 289         reg = readl(reg_base + CQSPI_REG_CONFIG);
 290         reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
 291
 292         if (mode & SPI_CPOL)
 293                 reg |= CQSPI_REG_CONFIG_CLK_POL;
 294         if (mode & SPI_CPHA)
 295                 reg |= CQSPI_REG_CONFIG_CLK_PHA;
 296
 297         writel(reg, reg_base + CQSPI_REG_CONFIG);
 298
 299         cadence_qspi_apb_controller_enable(reg_base);
 300 }
 301
 302 void cadence_qspi_apb_chipselect(void *reg_base,
 303         unsigned int chip_select, unsigned int decoder_enable)
 304 {
 305         unsigned int reg;
 306
 307         cadence_qspi_apb_controller_disable(reg_base);
 308
 309         debug("%s : chipselect %d decode %d\n", __func__, chip_select,
 310               decoder_enable);
 311
 312         reg = readl(reg_base + CQSPI_REG_CONFIG);
 313         /* docoder */
 314         if (decoder_enable) {
 315                 reg |= CQSPI_REG_CONFIG_DECODE;
 316         } else {
 317                 reg &= ~CQSPI_REG_CONFIG_DECODE;
 318                 /* Convert CS if without decoder.
 319                  * CS0 to 4b'1110
 320                  * CS1 to 4b'1101
 321                  * CS2 to 4b'1011
 322                  * CS3 to 4b'0111
 323                  */
 324                 chip_select = 0xF & ~(1 << chip_select);
 325         }
 326
 327         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 328                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 329         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 330                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 331         writel(reg, reg_base + CQSPI_REG_CONFIG);
 332
 333         cadence_qspi_apb_controller_enable(reg_base);
 334 }
 335
 336 void cadence_qspi_apb_delay(void *reg_base,
 337         unsigned int ref_clk, unsigned int sclk_hz,
 338         unsigned int tshsl_ns, unsigned int tsd2d_ns,
 339         unsigned int tchsh_ns, unsigned int tslch_ns)
 340 {
 341         unsigned int ref_clk_ns;
 342         unsigned int sclk_ns;
 343         unsigned int tshsl, tchsh, tslch, tsd2d;
 344         unsigned int reg;
 345
 346         cadence_qspi_apb_controller_disable(reg_base);
 347
 348         /* Convert to ns. */
 349         ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
 350
 351         /* Convert to ns. */
 352         sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
 353
 354         /* The controller adds additional delay to that programmed in the reg */
 355         if (tshsl_ns >= sclk_ns + ref_clk_ns)
 356                 tshsl_ns -= sclk_ns + ref_clk_ns;
 357         if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
 358                 tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
 359         tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
 360         tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
 361         tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
 362         tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
 363
 364         reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 365                         << CQSPI_REG_DELAY_TSHSL_LSB);
 366         reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 367                         << CQSPI_REG_DELAY_TCHSH_LSB);
 368         reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 369                         << CQSPI_REG_DELAY_TSLCH_LSB);
 370         reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 371                         << CQSPI_REG_DELAY_TSD2D_LSB);
 372         writel(reg, reg_base + CQSPI_REG_DELAY);
 373
 374         cadence_qspi_apb_controller_enable(reg_base);
 375 }
 376
 377 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
 378 {
 379         unsigned reg;
 380
 381         cadence_qspi_apb_controller_disable(plat->regbase);
 382
 383         /* Configure the device size and address bytes */
 384         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 385         /* Clear the previous value */
 386         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 387         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 388         reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 389         reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
 390         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 391
 392         /* Configure the remap address register, no remap */
 393         writel(0, plat->regbase + CQSPI_REG_REMAP);
 394
 395         /* Indirect mode configurations */
 396         writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION);
 397
 398         /* Disable all interrupts */
 399         writel(0, plat->regbase + CQSPI_REG_IRQMASK);
 400
 401         cadence_qspi_apb_controller_enable(plat->regbase);
 402 }
 403
 404 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
 405         unsigned int reg)
 406 {
 407         unsigned int retry = CQSPI_REG_RETRY;
 408
 409         /* Write the CMDCTRL without start execution. */
 410         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 411         /* Start execute */
 412         reg |= CQSPI_REG_CMDCTRL_EXECUTE;
 413         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 414
 415         while (retry--) {
 416                 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
 417                 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
 418                         break;
 419                 udelay(1);
 420         }
 421
 422         if (!retry) {
 423                 printf("QSPI: flash command execution timeout\n");
 424                 return -EIO;
 425         }
 426
 427         /* Polling QSPI idle status. */
 428         if (!cadence_qspi_wait_idle(reg_base))
 429                 return -EIO;
 430
 431         return 0;
 432 }
 433
 434 /* For command RDID, RDSR. */
 435 int cadence_qspi_apb_command_read(void *reg_base,
 436         unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
 437         u8 *rxbuf)
 438 {
 439         unsigned int reg;
 440         unsigned int read_len;
 441         int status;
 442
 443         if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
 444                 printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
 445                        cmdlen, rxlen);
 446                 return -EINVAL;
 447         }
 448
 449         reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 450
 451         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 452
 453         /* 0 means 1 byte. */
 454         reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 455                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 456         status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 457         if (status != 0)
 458                 return status;
 459
 460         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 461
 462         /* Put the read value into rx_buf */
 463         read_len = (rxlen > 4) ? 4 : rxlen;
 464         memcpy(rxbuf, &reg, read_len);
 465         rxbuf += read_len;
 466
 467         if (rxlen > 4) {
 468                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 469
 470                 read_len = rxlen - read_len;
 471                 memcpy(rxbuf, &reg, read_len);
 472         }
 473         return 0;
 474 }
 475
 476 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
 477 int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
 478         const u8 *cmdbuf, unsigned int txlen,  const u8 *txbuf)
 479 {
 480         unsigned int reg = 0;
 481         unsigned int addr_value;
 482         unsigned int wr_data;
 483         unsigned int wr_len;
 484
 485         if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
 486                 printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
 487                        cmdlen, txlen);
 488                 return -EINVAL;
 489         }
 490
 491         reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 492
 493         if (cmdlen == 4 || cmdlen == 5) {
 494                 /* Command with address */
 495                 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 496                 /* Number of bytes to write. */
 497                 reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 498                         << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 499                 /* Get address */
 500                 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
 501                         cmdlen >= 5 ? 4 : 3);
 502
 503                 writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
 504         }
 505
 506         if (txlen) {
 507                 /* writing data = yes */
 508                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 509                 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 510                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 511
 512                 wr_len = txlen > 4 ? 4 : txlen;
 513                 memcpy(&wr_data, txbuf, wr_len);
 514                 writel(wr_data, reg_base +
 515                         CQSPI_REG_CMDWRITEDATALOWER);
 516
 517                 if (txlen > 4) {
 518                         txbuf += wr_len;
 519                         wr_len = txlen - wr_len;
 520                         memcpy(&wr_data, txbuf, wr_len);
 521                         writel(wr_data, reg_base +
 522                                 CQSPI_REG_CMDWRITEDATAUPPER);
 523                 }
 524         }
 525
 526         /* Execute the command */
 527         return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 528 }
 529
 530 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
 531 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
 532         unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf)
 533 {
 534         unsigned int reg;
 535         unsigned int rd_reg;
 536         unsigned int addr_value;
 537         unsigned int dummy_clk;
 538         unsigned int dummy_bytes;
 539         unsigned int addr_bytes;
 540
 541         /*
 542          * Identify addr_byte. All NOR flash device drivers are using fast read
 543          * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
 544          * With that, the length is in value of 5 or 6. Only FRAM chip from
 545          * ramtron using normal read (which won't need dummy byte).
 546          * Unlikely NOR flash using normal read due to performance issue.
 547          */
 548         if (cmdlen >= 5)
 549                 /* to cater fast read where cmd + addr + dummy */
 550                 addr_bytes = cmdlen - 2;
 551         else
 552                 /* for normal read (only ramtron as of now) */
 553                 addr_bytes = cmdlen - 1;
 554
 555         /* Setup the indirect trigger address */
 556         writel(plat->trigger_address,
 557                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 558
 559         /* Configure the opcode */
 560         rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 561
 562         if (rx_width & SPI_RX_QUAD)
 563                 /* Instruction and address at DQ0, data at DQ0-3. */
 564                 rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 565
 566         /* Get address */
 567         addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
 568         writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
 569
 570         /* The remaining lenght is dummy bytes. */
 571         dummy_bytes = cmdlen - addr_bytes - 1;
 572         if (dummy_bytes) {
 573                 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
 574                         dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
 575
 576                 rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 577 #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
 578                 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
 579 #else
 580                 writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
 581 #endif
 582
 583                 /* Convert to clock cycles. */
 584                 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
 585                 /* Need to minus the mode byte (8 clocks). */
 586                 dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
 587
 588                 if (dummy_clk)
 589                         rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 590                                 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 591         }
 592
 593         writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
 594
 595         /* set device size */
 596         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 597         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 598         reg |= (addr_bytes - 1);
 599         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 600         return 0;
 601 }
 602
 603 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
 604 {
 605         u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
 606         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 607         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 608 }
 609
 610 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
 611 {
 612         unsigned int timeout = 10000;
 613         u32 reg;
 614
 615         while (timeout--) {
 616                 reg = cadence_qspi_get_rd_sram_level(plat);
 617                 if (reg)
 618                         return reg;
 619                 udelay(1);
 620         }
 621
 622         return -ETIMEDOUT;
 623 }
 624
 625 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
 626         unsigned int n_rx, u8 *rxbuf)
 627 {
 628         unsigned int remaining = n_rx;
 629         unsigned int bytes_to_read = 0;
 630         int ret;
 631
 632         writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
 633
 634         /* Start the indirect read transfer */
 635         writel(CQSPI_REG_INDIRECTRD_START,
 636                plat->regbase + CQSPI_REG_INDIRECTRD);
 637
 638         while (remaining > 0) {
 639                 ret = cadence_qspi_wait_for_data(plat);
 640                 if (ret < 0) {
 641                         printf("Indirect write timed out (%i)\n", ret);
 642                         goto failrd;
 643                 }
 644
 645                 bytes_to_read = ret;
 646
 647                 while (bytes_to_read != 0) {
 648                         bytes_to_read *= plat->fifo_width;
 649                         bytes_to_read = bytes_to_read > remaining ?
 650                                         remaining : bytes_to_read;
 651                         /*
 652                          * Handle non-4-byte aligned access to avoid
 653                          * data abort.
 654                          */
 655                         if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
 656                                 readsb(plat->ahbbase, rxbuf, bytes_to_read);
 657                         else
 658                                 readsl(plat->ahbbase, rxbuf,
 659                                        bytes_to_read >> 2);
 660                         rxbuf += bytes_to_read;
 661                         remaining -= bytes_to_read;
 662                         bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
 663                 }
 664         }
 665
 666         /* Check indirect done status */
 667         ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
 668                                 CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
 669         if (ret) {
 670                 printf("Indirect read completion error (%i)\n", ret);
 671                 goto failrd;
 672         }
 673
 674         /* Clear indirect completion status */
 675         writel(CQSPI_REG_INDIRECTRD_DONE,
 676                plat->regbase + CQSPI_REG_INDIRECTRD);
 677
 678         return 0;
 679
 680 failrd:
 681         /* Cancel the indirect read */
 682         writel(CQSPI_REG_INDIRECTRD_CANCEL,
 683                plat->regbase + CQSPI_REG_INDIRECTRD);
 684         return ret;
 685 }
 686
 687 /* Opcode + Address (3/4 bytes) */
 688 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
 689         unsigned int cmdlen, const u8 *cmdbuf)
 690 {
 691         unsigned int reg;
 692         unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
 693
 694         if (cmdlen < 4 || cmdbuf == NULL) {
 695                 printf("QSPI: Invalid input argument, len %d cmdbuf %p\n",
 696                        cmdlen, cmdbuf);
 697                 return -EINVAL;
 698         }
 699         /* Setup the indirect trigger address */
 700         writel(plat->trigger_address,
 701                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 702
 703         /* Configure the opcode */
 704         reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 705         writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
 706
 707         /* Setup write address. */
 708         reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
 709         writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
 710
 711         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 712         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 713         reg |= (addr_bytes - 1);
 714         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 715         return 0;
 716 }
 717
 718 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
 719         unsigned int n_tx, const u8 *txbuf)
 720 {
 721         unsigned int page_size = plat->page_size;
 722         unsigned int remaining = n_tx;
 723         const u8 *bb_txbuf = txbuf;
 724         void *bounce_buf = NULL;
 725         unsigned int write_bytes;
 726         int ret;
 727
 728         /*
 729          * Use bounce buffer for non 32 bit aligned txbuf to avoid data
 730          * aborts
 731          */
 732         if ((uintptr_t)txbuf % 4) {
 733                 bounce_buf = malloc(n_tx);
 734                 if (!bounce_buf)
 735                         return -ENOMEM;
 736                 memcpy(bounce_buf, txbuf, n_tx);
 737                 bb_txbuf = bounce_buf;
 738         }
 739
 740         /* Configure the indirect read transfer bytes */
 741         writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
 742
 743         /* Start the indirect write transfer */
 744         writel(CQSPI_REG_INDIRECTWR_START,
 745                plat->regbase + CQSPI_REG_INDIRECTWR);
 746
 747         while (remaining > 0) {
 748                 write_bytes = remaining > page_size ? page_size : remaining;
 749                 writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
 750                 if (write_bytes % 4)
 751                         writesb(plat->ahbbase,
 752                                 bb_txbuf + rounddown(write_bytes, 4),
 753                                 write_bytes % 4);
 754
 755                 ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,
 756                                         CQSPI_REG_SDRAMLEVEL_WR_MASK <<
 757                                         CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
 758                 if (ret) {
 759                         printf("Indirect write timed out (%i)\n", ret);
 760                         goto failwr;
 761                 }
 762
 763                 bb_txbuf += write_bytes;
 764                 remaining -= write_bytes;
 765         }
 766
 767         /* Check indirect done status */
 768         ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
 769                                 CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
 770         if (ret) {
 771                 printf("Indirect write completion error (%i)\n", ret);
 772                 goto failwr;
 773         }
 774
 775         /* Clear indirect completion status */
 776         writel(CQSPI_REG_INDIRECTWR_DONE,
 777                plat->regbase + CQSPI_REG_INDIRECTWR);
 778         if (bounce_buf)
 779                 free(bounce_buf);
 780         return 0;
 781
 782 failwr:
 783         /* Cancel the indirect write */
 784         writel(CQSPI_REG_INDIRECTWR_CANCEL,
 785                plat->regbase + CQSPI_REG_INDIRECTWR);
 786         if (bounce_buf)
 787                 free(bounce_buf);
 788         return ret;
 789 }
 790
 791 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
 792 {
 793         unsigned int reg;
 794
 795         /* enter XiP mode immediately and enable direct mode */
 796         reg = readl(reg_base + CQSPI_REG_CONFIG);
 797         reg |= CQSPI_REG_CONFIG_ENABLE;
 798         reg |= CQSPI_REG_CONFIG_DIRECT;
 799         reg |= CQSPI_REG_CONFIG_XIP_IMM;
 800         writel(reg, reg_base + CQSPI_REG_CONFIG);
 801
 802         /* keep the XiP mode */
 803         writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
 804
 805         /* Enable mode bit at devrd */
 806         reg = readl(reg_base + CQSPI_REG_RD_INSTR);
 807         reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 808         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 809 }