2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * - Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * - Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * - Neither the name of the Altera Corporation nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include <linux/bitops.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
39 #include "cadence_qspi.h"
41 __weak void cadence_qspi_apb_enable_linear_mode(bool enable)
46 void cadence_qspi_apb_controller_enable(void *reg_base)
49 reg = readl(reg_base + CQSPI_REG_CONFIG);
50 reg |= CQSPI_REG_CONFIG_ENABLE;
51 writel(reg, reg_base + CQSPI_REG_CONFIG);
54 void cadence_qspi_apb_controller_disable(void *reg_base)
57 reg = readl(reg_base + CQSPI_REG_CONFIG);
58 reg &= ~CQSPI_REG_CONFIG_ENABLE;
59 writel(reg, reg_base + CQSPI_REG_CONFIG);
62 void cadence_qspi_apb_dac_mode_enable(void *reg_base)
66 reg = readl(reg_base + CQSPI_REG_CONFIG);
67 reg |= CQSPI_REG_CONFIG_DIRECT;
68 writel(reg, reg_base + CQSPI_REG_CONFIG);
71 static unsigned int cadence_qspi_calc_dummy(const struct spi_mem_op *op,
74 unsigned int dummy_clk;
76 if (!op->dummy.nbytes || !op->dummy.buswidth)
79 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
86 static u32 cadence_qspi_calc_rdreg(struct cadence_spi_priv *priv)
90 rdreg |= priv->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
91 rdreg |= priv->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
92 rdreg |= priv->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
97 static int cadence_qspi_buswidth_to_inst_type(u8 buswidth)
102 return CQSPI_INST_TYPE_SINGLE;
105 return CQSPI_INST_TYPE_DUAL;
108 return CQSPI_INST_TYPE_QUAD;
111 return CQSPI_INST_TYPE_OCTAL;
118 static int cadence_qspi_set_protocol(struct cadence_spi_priv *priv,
119 const struct spi_mem_op *op)
123 priv->dtr = op->data.dtr && op->cmd.dtr && op->addr.dtr;
125 ret = cadence_qspi_buswidth_to_inst_type(op->cmd.buswidth);
128 priv->inst_width = ret;
130 ret = cadence_qspi_buswidth_to_inst_type(op->addr.buswidth);
133 priv->addr_width = ret;
135 ret = cadence_qspi_buswidth_to_inst_type(op->data.buswidth);
138 priv->data_width = ret;
143 /* Return 1 if idle, otherwise return 0 (busy). */
144 static unsigned int cadence_qspi_wait_idle(void *reg_base)
146 unsigned int start, count = 0;
147 /* timeout in unit of ms */
148 unsigned int timeout = 5000;
150 start = get_timer(0);
151 for ( ; get_timer(start) < timeout ; ) {
152 if (CQSPI_REG_IS_IDLE(reg_base))
157 * Ensure the QSPI controller is in true idle state after
158 * reading back the same idle status consecutively
160 if (count >= CQSPI_POLL_IDLE_RETRY)
164 /* Timeout, still in busy mode. */
165 printf("QSPI: QSPI is still busy after poll for %d times.\n",
170 void cadence_qspi_apb_readdata_capture(void *reg_base,
171 unsigned int bypass, unsigned int delay)
174 cadence_qspi_apb_controller_disable(reg_base);
176 reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
179 reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
181 reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
183 reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
184 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
186 reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
187 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
189 writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
191 cadence_qspi_apb_controller_enable(reg_base);
194 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
195 unsigned int ref_clk_hz, unsigned int sclk_hz)
200 cadence_qspi_apb_controller_disable(reg_base);
201 reg = readl(reg_base + CQSPI_REG_CONFIG);
202 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
205 * The baud_div field in the config reg is 4 bits, and the ref clock is
206 * divided by 2 * (baud_div + 1). Round up the divider to ensure the
207 * SPI clock rate is less than or equal to the requested clock rate.
209 div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
211 /* ensure the baud rate doesn't exceed the max value */
212 if (div > CQSPI_REG_CONFIG_BAUD_MASK)
213 div = CQSPI_REG_CONFIG_BAUD_MASK;
215 debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
216 ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
218 reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
219 writel(reg, reg_base + CQSPI_REG_CONFIG);
221 cadence_qspi_apb_controller_enable(reg_base);
224 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
228 cadence_qspi_apb_controller_disable(reg_base);
229 reg = readl(reg_base + CQSPI_REG_CONFIG);
230 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
233 reg |= CQSPI_REG_CONFIG_CLK_POL;
235 reg |= CQSPI_REG_CONFIG_CLK_PHA;
237 writel(reg, reg_base + CQSPI_REG_CONFIG);
239 cadence_qspi_apb_controller_enable(reg_base);
242 void cadence_qspi_apb_chipselect(void *reg_base,
243 unsigned int chip_select, unsigned int decoder_enable)
247 cadence_qspi_apb_controller_disable(reg_base);
249 debug("%s : chipselect %d decode %d\n", __func__, chip_select,
252 reg = readl(reg_base + CQSPI_REG_CONFIG);
254 if (decoder_enable) {
255 reg |= CQSPI_REG_CONFIG_DECODE;
257 reg &= ~CQSPI_REG_CONFIG_DECODE;
258 /* Convert CS if without decoder.
264 chip_select = 0xF & ~(1 << chip_select);
267 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
268 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
269 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
270 << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
271 writel(reg, reg_base + CQSPI_REG_CONFIG);
273 cadence_qspi_apb_controller_enable(reg_base);
276 void cadence_qspi_apb_delay(void *reg_base,
277 unsigned int ref_clk, unsigned int sclk_hz,
278 unsigned int tshsl_ns, unsigned int tsd2d_ns,
279 unsigned int tchsh_ns, unsigned int tslch_ns)
281 unsigned int ref_clk_ns;
282 unsigned int sclk_ns;
283 unsigned int tshsl, tchsh, tslch, tsd2d;
286 cadence_qspi_apb_controller_disable(reg_base);
289 ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
292 sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
294 /* The controller adds additional delay to that programmed in the reg */
295 if (tshsl_ns >= sclk_ns + ref_clk_ns)
296 tshsl_ns -= sclk_ns + ref_clk_ns;
297 if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
298 tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
299 tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
300 tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
301 tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
302 tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
304 reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
305 << CQSPI_REG_DELAY_TSHSL_LSB);
306 reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
307 << CQSPI_REG_DELAY_TCHSH_LSB);
308 reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
309 << CQSPI_REG_DELAY_TSLCH_LSB);
310 reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
311 << CQSPI_REG_DELAY_TSD2D_LSB);
312 writel(reg, reg_base + CQSPI_REG_DELAY);
314 cadence_qspi_apb_controller_enable(reg_base);
317 void cadence_qspi_apb_controller_init(struct cadence_spi_priv *priv)
321 cadence_qspi_apb_controller_disable(priv->regbase);
323 /* Configure the device size and address bytes */
324 reg = readl(priv->regbase + CQSPI_REG_SIZE);
325 /* Clear the previous value */
326 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
327 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
328 reg |= (priv->page_size << CQSPI_REG_SIZE_PAGE_LSB);
329 reg |= (priv->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
330 writel(reg, priv->regbase + CQSPI_REG_SIZE);
332 /* Configure the remap address register, no remap */
333 writel(0, priv->regbase + CQSPI_REG_REMAP);
335 /* Indirect mode configurations */
336 writel(priv->fifo_depth / 2, priv->regbase + CQSPI_REG_SRAMPARTITION);
338 /* Disable all interrupts */
339 writel(0, priv->regbase + CQSPI_REG_IRQMASK);
341 cadence_qspi_apb_controller_enable(priv->regbase);
344 int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg)
346 unsigned int retry = CQSPI_REG_RETRY;
348 /* Write the CMDCTRL without start execution. */
349 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
351 reg |= CQSPI_REG_CMDCTRL_EXECUTE;
352 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
355 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
356 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
362 printf("QSPI: flash command execution timeout\n");
366 /* Polling QSPI idle status. */
367 if (!cadence_qspi_wait_idle(reg_base))
373 static int cadence_qspi_setup_opcode_ext(struct cadence_spi_priv *priv,
374 const struct spi_mem_op *op,
380 if (op->cmd.nbytes != 2)
383 /* Opcode extension is the LSB. */
384 ext = op->cmd.opcode & 0xff;
386 reg = readl(priv->regbase + CQSPI_REG_OP_EXT_LOWER);
387 reg &= ~(0xff << shift);
389 writel(reg, priv->regbase + CQSPI_REG_OP_EXT_LOWER);
394 static int cadence_qspi_enable_dtr(struct cadence_spi_priv *priv,
395 const struct spi_mem_op *op,
402 reg = readl(priv->regbase + CQSPI_REG_CONFIG);
405 reg |= CQSPI_REG_CONFIG_DTR_PROTO;
406 reg |= CQSPI_REG_CONFIG_DUAL_OPCODE;
408 /* Set up command opcode extension. */
409 ret = cadence_qspi_setup_opcode_ext(priv, op, shift);
413 reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
414 reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
417 writel(reg, priv->regbase + CQSPI_REG_CONFIG);
422 int cadence_qspi_apb_command_read_setup(struct cadence_spi_priv *priv,
423 const struct spi_mem_op *op)
428 ret = cadence_qspi_set_protocol(priv, op);
432 ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_STIG_LSB,
437 reg = cadence_qspi_calc_rdreg(priv);
438 writel(reg, priv->regbase + CQSPI_REG_RD_INSTR);
443 /* For command RDID, RDSR. */
444 int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv,
445 const struct spi_mem_op *op)
447 void *reg_base = priv->regbase;
449 unsigned int read_len;
451 unsigned int rxlen = op->data.nbytes;
452 void *rxbuf = op->data.buf.in;
453 unsigned int dummy_clk;
456 if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
457 printf("QSPI: Invalid input arguments rxlen %u\n", rxlen);
462 opcode = op->cmd.opcode >> 8;
464 opcode = op->cmd.opcode;
466 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
468 /* Set up dummy cycles. */
469 dummy_clk = cadence_qspi_calc_dummy(op, priv->dtr);
470 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
474 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
475 << CQSPI_REG_CMDCTRL_DUMMY_LSB;
477 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
479 /* 0 means 1 byte. */
480 reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
481 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
483 /* setup ADDR BIT field */
484 if (op->addr.nbytes) {
485 writel(op->addr.val, priv->regbase + CQSPI_REG_CMDADDRESS);
487 * address bytes are zero indexed
489 reg |= (((op->addr.nbytes - 1) &
490 CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) <<
491 CQSPI_REG_CMDCTRL_ADD_BYTES_LSB);
492 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
495 status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
499 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
501 /* Put the read value into rx_buf */
502 read_len = (rxlen > 4) ? 4 : rxlen;
503 memcpy(rxbuf, ®, read_len);
507 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
509 read_len = rxlen - read_len;
510 memcpy(rxbuf, ®, read_len);
515 int cadence_qspi_apb_command_write_setup(struct cadence_spi_priv *priv,
516 const struct spi_mem_op *op)
521 ret = cadence_qspi_set_protocol(priv, op);
525 ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_STIG_LSB,
530 reg = cadence_qspi_calc_rdreg(priv);
531 writel(reg, priv->regbase + CQSPI_REG_RD_INSTR);
536 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
537 int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv,
538 const struct spi_mem_op *op)
540 unsigned int reg = 0;
541 unsigned int wr_data;
543 unsigned int txlen = op->data.nbytes;
544 const void *txbuf = op->data.buf.out;
545 void *reg_base = priv->regbase;
549 /* Reorder address to SPI bus order if only transferring address */
551 addr = cpu_to_be32(op->addr.val);
552 if (op->addr.nbytes == 3)
555 txlen = op->addr.nbytes;
558 if (txlen > CQSPI_STIG_DATA_LEN_MAX) {
559 printf("QSPI: Invalid input arguments txlen %u\n", txlen);
564 opcode = op->cmd.opcode >> 8;
566 opcode = op->cmd.opcode;
568 reg |= opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
571 /* writing data = yes */
572 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
573 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
574 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
576 wr_len = txlen > 4 ? 4 : txlen;
577 memcpy(&wr_data, txbuf, wr_len);
578 writel(wr_data, reg_base +
579 CQSPI_REG_CMDWRITEDATALOWER);
583 wr_len = txlen - wr_len;
584 memcpy(&wr_data, txbuf, wr_len);
585 writel(wr_data, reg_base +
586 CQSPI_REG_CMDWRITEDATAUPPER);
590 /* Execute the command */
591 return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
594 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
595 int cadence_qspi_apb_read_setup(struct cadence_spi_priv *priv,
596 const struct spi_mem_op *op)
600 unsigned int dummy_clk;
601 unsigned int dummy_bytes = op->dummy.nbytes;
605 ret = cadence_qspi_set_protocol(priv, op);
609 ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_READ_LSB,
614 /* Setup the indirect trigger address */
615 writel(priv->trigger_address,
616 priv->regbase + CQSPI_REG_INDIRECTTRIGGER);
618 /* Configure the opcode */
620 opcode = op->cmd.opcode >> 8;
622 opcode = op->cmd.opcode;
624 rd_reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
625 rd_reg |= cadence_qspi_calc_rdreg(priv);
627 writel(op->addr.val, priv->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
630 /* Convert to clock cycles. */
631 dummy_clk = cadence_qspi_calc_dummy(op, priv->dtr);
633 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
637 rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
638 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
641 writel(rd_reg, priv->regbase + CQSPI_REG_RD_INSTR);
643 /* set device size */
644 reg = readl(priv->regbase + CQSPI_REG_SIZE);
645 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
646 reg |= (op->addr.nbytes - 1);
647 writel(reg, priv->regbase + CQSPI_REG_SIZE);
651 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_priv *priv)
653 u32 reg = readl(priv->regbase + CQSPI_REG_SDRAMLEVEL);
654 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
655 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
658 static int cadence_qspi_wait_for_data(struct cadence_spi_priv *priv)
660 unsigned int timeout = 10000;
664 reg = cadence_qspi_get_rd_sram_level(priv);
674 cadence_qspi_apb_indirect_read_execute(struct cadence_spi_priv *priv,
675 unsigned int n_rx, u8 *rxbuf)
677 unsigned int remaining = n_rx;
678 unsigned int bytes_to_read = 0;
681 writel(n_rx, priv->regbase + CQSPI_REG_INDIRECTRDBYTES);
683 /* Start the indirect read transfer */
684 writel(CQSPI_REG_INDIRECTRD_START,
685 priv->regbase + CQSPI_REG_INDIRECTRD);
687 while (remaining > 0) {
688 ret = cadence_qspi_wait_for_data(priv);
690 printf("Indirect write timed out (%i)\n", ret);
696 while (bytes_to_read != 0) {
697 bytes_to_read *= priv->fifo_width;
698 bytes_to_read = bytes_to_read > remaining ?
699 remaining : bytes_to_read;
701 * Handle non-4-byte aligned access to avoid
704 if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
705 readsb(priv->ahbbase, rxbuf, bytes_to_read);
707 readsl(priv->ahbbase, rxbuf,
709 rxbuf += bytes_to_read;
710 remaining -= bytes_to_read;
711 bytes_to_read = cadence_qspi_get_rd_sram_level(priv);
715 /* Check indirect done status */
716 ret = wait_for_bit_le32(priv->regbase + CQSPI_REG_INDIRECTRD,
717 CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
719 printf("Indirect read completion error (%i)\n", ret);
723 /* Clear indirect completion status */
724 writel(CQSPI_REG_INDIRECTRD_DONE,
725 priv->regbase + CQSPI_REG_INDIRECTRD);
727 /* Check indirect done status */
728 ret = wait_for_bit_le32(priv->regbase + CQSPI_REG_INDIRECTRD,
729 CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0);
731 printf("Indirect read clear completion error (%i)\n", ret);
738 /* Cancel the indirect read */
739 writel(CQSPI_REG_INDIRECTRD_CANCEL,
740 priv->regbase + CQSPI_REG_INDIRECTRD);
744 int cadence_qspi_apb_read_execute(struct cadence_spi_priv *priv,
745 const struct spi_mem_op *op)
747 u64 from = op->addr.val;
748 void *buf = op->data.buf.in;
749 size_t len = op->data.nbytes;
751 cadence_qspi_apb_enable_linear_mode(true);
753 if (priv->use_dac_mode && (from + len < priv->ahbsize)) {
755 dma_memcpy(buf, priv->ahbbase + from, len) < 0) {
756 memcpy_fromio(buf, priv->ahbbase + from, len);
758 if (!cadence_qspi_wait_idle(priv->regbase))
763 return cadence_qspi_apb_indirect_read_execute(priv, len, buf);
766 /* Opcode + Address (3/4 bytes) */
767 int cadence_qspi_apb_write_setup(struct cadence_spi_priv *priv,
768 const struct spi_mem_op *op)
774 ret = cadence_qspi_set_protocol(priv, op);
778 ret = cadence_qspi_enable_dtr(priv, op, CQSPI_REG_OP_EXT_WRITE_LSB,
783 /* Setup the indirect trigger address */
784 writel(priv->trigger_address,
785 priv->regbase + CQSPI_REG_INDIRECTTRIGGER);
787 /* Configure the opcode */
789 opcode = op->cmd.opcode >> 8;
791 opcode = op->cmd.opcode;
793 reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
794 reg |= priv->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
795 reg |= priv->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
796 writel(reg, priv->regbase + CQSPI_REG_WR_INSTR);
798 reg = cadence_qspi_calc_rdreg(priv);
799 writel(reg, priv->regbase + CQSPI_REG_RD_INSTR);
801 writel(op->addr.val, priv->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
805 * Some flashes like the cypress Semper flash expect a 4-byte
806 * dummy address with the Read SR command in DTR mode, but this
807 * controller does not support sending address with the Read SR
808 * command. So, disable write completion polling on the
809 * controller's side. spi-nor will take care of polling the
812 reg = readl(priv->regbase + CQSPI_REG_WR_COMPLETION_CTRL);
813 reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
814 writel(reg, priv->regbase + CQSPI_REG_WR_COMPLETION_CTRL);
817 reg = readl(priv->regbase + CQSPI_REG_SIZE);
818 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
819 reg |= (op->addr.nbytes - 1);
820 writel(reg, priv->regbase + CQSPI_REG_SIZE);
825 cadence_qspi_apb_indirect_write_execute(struct cadence_spi_priv *priv,
826 unsigned int n_tx, const u8 *txbuf)
828 unsigned int page_size = priv->page_size;
829 unsigned int remaining = n_tx;
830 const u8 *bb_txbuf = txbuf;
831 void *bounce_buf = NULL;
832 unsigned int write_bytes;
836 * Use bounce buffer for non 32 bit aligned txbuf to avoid data
839 if ((uintptr_t)txbuf % 4) {
840 bounce_buf = malloc(n_tx);
843 memcpy(bounce_buf, txbuf, n_tx);
844 bb_txbuf = bounce_buf;
847 /* Configure the indirect read transfer bytes */
848 writel(n_tx, priv->regbase + CQSPI_REG_INDIRECTWRBYTES);
850 /* Start the indirect write transfer */
851 writel(CQSPI_REG_INDIRECTWR_START,
852 priv->regbase + CQSPI_REG_INDIRECTWR);
855 * Some delay is required for the above bit to be internally
856 * synchronized by the QSPI module.
858 ndelay(priv->wr_delay);
860 while (remaining > 0) {
861 write_bytes = remaining > page_size ? page_size : remaining;
862 writesl(priv->ahbbase, bb_txbuf, write_bytes >> 2);
864 writesb(priv->ahbbase,
865 bb_txbuf + rounddown(write_bytes, 4),
868 ret = wait_for_bit_le32(priv->regbase + CQSPI_REG_SDRAMLEVEL,
869 CQSPI_REG_SDRAMLEVEL_WR_MASK <<
870 CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
872 printf("Indirect write timed out (%i)\n", ret);
876 bb_txbuf += write_bytes;
877 remaining -= write_bytes;
880 /* Check indirect done status */
881 ret = wait_for_bit_le32(priv->regbase + CQSPI_REG_INDIRECTWR,
882 CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
884 printf("Indirect write completion error (%i)\n", ret);
888 /* Clear indirect completion status */
889 writel(CQSPI_REG_INDIRECTWR_DONE,
890 priv->regbase + CQSPI_REG_INDIRECTWR);
892 /* Check indirect done status */
893 ret = wait_for_bit_le32(priv->regbase + CQSPI_REG_INDIRECTWR,
894 CQSPI_REG_INDIRECTWR_DONE, 0, 10, 0);
896 printf("Indirect write clear completion error (%i)\n", ret);
905 /* Cancel the indirect write */
906 writel(CQSPI_REG_INDIRECTWR_CANCEL,
907 priv->regbase + CQSPI_REG_INDIRECTWR);
913 int cadence_qspi_apb_write_execute(struct cadence_spi_priv *priv,
914 const struct spi_mem_op *op)
916 u32 to = op->addr.val;
917 const void *buf = op->data.buf.out;
918 size_t len = op->data.nbytes;
921 * Some flashes like the Cypress Semper flash expect a dummy 4-byte
922 * address (all 0s) with the read status register command in DTR mode.
923 * But this controller does not support sending dummy address bytes to
924 * the flash when it is polling the write completion register in DTR
925 * mode. So, we can not use direct mode when in DTR mode for writing
928 cadence_qspi_apb_enable_linear_mode(true);
929 if (!priv->dtr && priv->use_dac_mode && (to + len < priv->ahbsize)) {
930 memcpy_toio(priv->ahbbase + to, buf, len);
931 if (!cadence_qspi_wait_idle(priv->regbase))
936 return cadence_qspi_apb_indirect_write_execute(priv, len, buf);
939 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
943 /* enter XiP mode immediately and enable direct mode */
944 reg = readl(reg_base + CQSPI_REG_CONFIG);
945 reg |= CQSPI_REG_CONFIG_ENABLE;
946 reg |= CQSPI_REG_CONFIG_DIRECT;
947 reg |= CQSPI_REG_CONFIG_XIP_IMM;
948 writel(reg, reg_base + CQSPI_REG_CONFIG);
950 /* keep the XiP mode */
951 writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
953 /* Enable mode bit at devrd */
954 reg = readl(reg_base + CQSPI_REG_RD_INSTR);
955 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
956 writel(reg, reg_base + CQSPI_REG_RD_INSTR);