1 // SPDX-License-Identifier: GPL-2.0+
4 * Altera Corporation <www.altera.com>
9 #include <asm-generic/io.h>
16 #include <linux/errno.h>
17 #include <linux/sizes.h>
18 #include "cadence_qspi.h"
20 #define CQSPI_STIG_READ 0
21 #define CQSPI_STIG_WRITE 1
25 static int cadence_spi_write_speed(struct udevice *bus, uint hz)
27 struct cadence_spi_platdata *plat = bus->platdata;
28 struct cadence_spi_priv *priv = dev_get_priv(bus);
30 cadence_qspi_apb_config_baudrate_div(priv->regbase,
31 plat->ref_clk_hz, hz);
33 /* Reconfigure delay timing if speed is changed. */
34 cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
35 plat->tshsl_ns, plat->tsd2d_ns,
36 plat->tchsh_ns, plat->tslch_ns);
41 static int cadence_spi_read_id(void *reg_base, u8 len, u8 *idcode)
43 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
46 SPI_MEM_OP_DATA_IN(len, idcode, 1));
48 return cadence_qspi_apb_command_read(reg_base, &op);
51 /* Calibration sequence to determine the read data capture delay register */
52 static int spi_calibration(struct udevice *bus, uint hz)
54 struct cadence_spi_priv *priv = dev_get_priv(bus);
55 void *base = priv->regbase;
56 unsigned int idcode = 0, temp = 0;
57 int err = 0, i, range_lo = -1, range_hi = -1;
59 /* start with slowest clock (1 MHz) */
60 cadence_spi_write_speed(bus, 1000000);
62 /* configure the read data capture delay register to 0 */
63 cadence_qspi_apb_readdata_capture(base, 1, 0);
66 cadence_qspi_apb_controller_enable(base);
68 /* read the ID which will be our golden value */
69 err = cadence_spi_read_id(base, 3, (u8 *)&idcode);
71 puts("SF: Calibration failed (read)\n");
75 /* use back the intended clock and find low range */
76 cadence_spi_write_speed(bus, hz);
77 for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
79 cadence_qspi_apb_controller_disable(base);
81 /* reconfigure the read data capture delay register */
82 cadence_qspi_apb_readdata_capture(base, 1, i);
84 /* Enable back QSPI */
85 cadence_qspi_apb_controller_enable(base);
87 /* issue a RDID to get the ID value */
88 err = cadence_spi_read_id(base, 3, (u8 *)&temp);
90 puts("SF: Calibration failed (read)\n");
94 /* search for range lo */
95 if (range_lo == -1 && temp == idcode) {
100 /* search for range hi */
101 if (range_lo != -1 && temp != idcode) {
108 if (range_lo == -1) {
109 puts("SF: Calibration failed (low range)\n");
113 /* Disable QSPI for subsequent initialization */
114 cadence_qspi_apb_controller_disable(base);
116 /* configure the final value for read data capture delay register */
117 cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
118 debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
119 (range_hi + range_lo) / 2, range_lo, range_hi);
121 /* just to ensure we do once only when speed or chip select change */
122 priv->qspi_calibrated_hz = hz;
123 priv->qspi_calibrated_cs = spi_chip_select(bus);
128 static int cadence_spi_set_speed(struct udevice *bus, uint hz)
130 struct cadence_spi_platdata *plat = bus->platdata;
131 struct cadence_spi_priv *priv = dev_get_priv(bus);
134 if (hz > plat->max_hz)
138 cadence_qspi_apb_controller_disable(priv->regbase);
141 * Calibration required for different current SCLK speed, requested
142 * SCLK speed or chip select
144 if (priv->previous_hz != hz ||
145 priv->qspi_calibrated_hz != hz ||
146 priv->qspi_calibrated_cs != spi_chip_select(bus)) {
147 err = spi_calibration(bus, hz);
151 /* prevent calibration run when same as previous request */
152 priv->previous_hz = hz;
156 cadence_qspi_apb_controller_enable(priv->regbase);
158 debug("%s: speed=%d\n", __func__, hz);
163 static int cadence_spi_probe(struct udevice *bus)
165 struct cadence_spi_platdata *plat = bus->platdata;
166 struct cadence_spi_priv *priv = dev_get_priv(bus);
169 priv->regbase = plat->regbase;
170 priv->ahbbase = plat->ahbbase;
172 ret = reset_get_bulk(bus, &priv->resets);
174 dev_warn(bus, "Can't get reset: %d\n", ret);
176 reset_deassert_bulk(&priv->resets);
178 if (!priv->qspi_is_init) {
179 cadence_qspi_apb_controller_init(plat);
180 priv->qspi_is_init = 1;
186 static int cadence_spi_remove(struct udevice *dev)
188 struct cadence_spi_priv *priv = dev_get_priv(dev);
190 return reset_release_bulk(&priv->resets);
193 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
195 struct cadence_spi_platdata *plat = bus->platdata;
196 struct cadence_spi_priv *priv = dev_get_priv(bus);
199 cadence_qspi_apb_controller_disable(priv->regbase);
202 cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
204 /* Enable Direct Access Controller */
205 if (plat->use_dac_mode)
206 cadence_qspi_apb_dac_mode_enable(priv->regbase);
209 cadence_qspi_apb_controller_enable(priv->regbase);
214 static int cadence_spi_mem_exec_op(struct spi_slave *spi,
215 const struct spi_mem_op *op)
217 struct udevice *bus = spi->dev->parent;
218 struct cadence_spi_platdata *plat = bus->platdata;
219 struct cadence_spi_priv *priv = dev_get_priv(bus);
220 void *base = priv->regbase;
224 /* Set Chip select */
225 cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
226 plat->is_decoded_cs);
228 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
229 if (!op->addr.nbytes)
230 mode = CQSPI_STIG_READ;
234 if (!op->addr.nbytes || !op->data.buf.out)
235 mode = CQSPI_STIG_WRITE;
241 case CQSPI_STIG_READ:
242 err = cadence_qspi_apb_command_read(base, op);
244 case CQSPI_STIG_WRITE:
245 err = cadence_qspi_apb_command_write(base, op);
248 err = cadence_qspi_apb_read_setup(plat, op);
250 err = cadence_qspi_apb_read_execute(plat, op);
253 err = cadence_qspi_apb_write_setup(plat, op);
255 err = cadence_qspi_apb_write_execute(plat, op);
265 static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
267 struct cadence_spi_platdata *plat = bus->platdata;
272 plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
273 plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
275 plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
276 plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
277 plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
278 plat->trigger_address = dev_read_u32_default(bus,
279 "cdns,trigger-address",
281 /* Use DAC mode only when MMIO window is at least 8M wide */
282 if (plat->ahbsize >= SZ_8M)
283 plat->use_dac_mode = true;
285 /* All other paramters are embedded in the child node */
286 subnode = dev_read_first_subnode(bus);
287 if (!ofnode_valid(subnode)) {
288 printf("Error: subnode with SPI flash config missing!\n");
292 /* Use 500 KHz as a suitable default */
293 plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
296 /* Read other parameters from DT */
297 plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
298 plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
299 plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
301 plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
303 plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
304 plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
306 ret = clk_get_by_index(bus, 0, &clk);
308 #ifdef CONFIG_CQSPI_REF_CLK
309 plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
314 plat->ref_clk_hz = clk_get_rate(&clk);
316 if (IS_ERR_VALUE(plat->ref_clk_hz))
317 return plat->ref_clk_hz;
320 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
321 __func__, plat->regbase, plat->ahbbase, plat->max_hz,
327 static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
328 .exec_op = cadence_spi_mem_exec_op,
331 static const struct dm_spi_ops cadence_spi_ops = {
332 .set_speed = cadence_spi_set_speed,
333 .set_mode = cadence_spi_set_mode,
334 .mem_ops = &cadence_spi_mem_ops,
336 * cs_info is not needed, since we require all chip selects to be
337 * in the device tree explicitly
341 static const struct udevice_id cadence_spi_ids[] = {
342 { .compatible = "cdns,qspi-nor" },
343 { .compatible = "ti,am654-ospi" },
347 U_BOOT_DRIVER(cadence_spi) = {
348 .name = "cadence_spi",
350 .of_match = cadence_spi_ids,
351 .ops = &cadence_spi_ops,
352 .ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
353 .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
354 .priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
355 .probe = cadence_spi_probe,
356 .remove = cadence_spi_remove,
357 .flags = DM_FLAG_OS_PREPARE,