1 // SPDX-License-Identifier: GPL-2.0+
4 * Altera Corporation <www.altera.com>
10 #include <asm-generic/io.h>
17 #include <dm/device_compat.h>
18 #include <linux/err.h>
19 #include <linux/errno.h>
20 #include <linux/sizes.h>
21 #include <zynqmp_firmware.h>
22 #include "cadence_qspi.h"
23 #include <dt-bindings/power/xlnx-versal-power.h>
25 #define NSEC_PER_SEC 1000000000L
27 #define CQSPI_STIG_READ 0
28 #define CQSPI_STIG_WRITE 1
32 __weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
33 const struct spi_mem_op *op)
38 __weak int cadence_qspi_versal_flash_reset(struct udevice *dev)
43 static int cadence_spi_write_speed(struct udevice *bus, uint hz)
45 struct cadence_spi_priv *priv = dev_get_priv(bus);
47 cadence_qspi_apb_config_baudrate_div(priv->regbase,
48 priv->ref_clk_hz, hz);
50 /* Reconfigure delay timing if speed is changed. */
51 cadence_qspi_apb_delay(priv->regbase, priv->ref_clk_hz, hz,
52 priv->tshsl_ns, priv->tsd2d_ns,
53 priv->tchsh_ns, priv->tslch_ns);
58 static int cadence_spi_read_id(struct cadence_spi_priv *priv, u8 len,
63 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
66 SPI_MEM_OP_DATA_IN(len, idcode, 1));
68 err = cadence_qspi_apb_command_read_setup(priv, &op);
70 err = cadence_qspi_apb_command_read(priv, &op);
75 /* Calibration sequence to determine the read data capture delay register */
76 static int spi_calibration(struct udevice *bus, uint hz)
78 struct cadence_spi_priv *priv = dev_get_priv(bus);
79 void *base = priv->regbase;
80 unsigned int idcode = 0, temp = 0;
81 int err = 0, i, range_lo = -1, range_hi = -1;
83 /* start with slowest clock (1 MHz) */
84 cadence_spi_write_speed(bus, 1000000);
86 /* configure the read data capture delay register to 0 */
87 cadence_qspi_apb_readdata_capture(base, 1, 0);
90 cadence_qspi_apb_controller_enable(base);
92 /* read the ID which will be our golden value */
93 err = cadence_spi_read_id(priv, 3, (u8 *)&idcode);
95 puts("SF: Calibration failed (read)\n");
99 /* use back the intended clock and find low range */
100 cadence_spi_write_speed(bus, hz);
101 for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
103 cadence_qspi_apb_controller_disable(base);
105 /* reconfigure the read data capture delay register */
106 cadence_qspi_apb_readdata_capture(base, 1, i);
108 /* Enable back QSPI */
109 cadence_qspi_apb_controller_enable(base);
111 /* issue a RDID to get the ID value */
112 err = cadence_spi_read_id(priv, 3, (u8 *)&temp);
114 puts("SF: Calibration failed (read)\n");
118 /* search for range lo */
119 if (range_lo == -1 && temp == idcode) {
124 /* search for range hi */
125 if (range_lo != -1 && temp != idcode) {
132 if (range_lo == -1) {
133 puts("SF: Calibration failed (low range)\n");
137 /* Disable QSPI for subsequent initialization */
138 cadence_qspi_apb_controller_disable(base);
140 /* configure the final value for read data capture delay register */
141 cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
142 debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
143 (range_hi + range_lo) / 2, range_lo, range_hi);
145 /* just to ensure we do once only when speed or chip select change */
146 priv->qspi_calibrated_hz = hz;
147 priv->qspi_calibrated_cs = spi_chip_select(bus);
152 static int cadence_spi_set_speed(struct udevice *bus, uint hz)
154 struct cadence_spi_priv *priv = dev_get_priv(bus);
157 if (!hz || hz > priv->max_hz)
160 cadence_qspi_apb_controller_disable(priv->regbase);
163 * If the device tree already provides a read delay value, use that
164 * instead of calibrating.
166 if (priv->read_delay >= 0) {
167 cadence_spi_write_speed(bus, hz);
168 cadence_qspi_apb_readdata_capture(priv->regbase, 1,
170 } else if (priv->previous_hz != hz ||
171 priv->qspi_calibrated_hz != hz ||
172 priv->qspi_calibrated_cs != spi_chip_select(bus)) {
174 * Calibration required for different current SCLK speed,
175 * requested SCLK speed or chip select
177 err = spi_calibration(bus, hz);
181 /* prevent calibration run when same as previous request */
182 priv->previous_hz = hz;
186 cadence_qspi_apb_controller_enable(priv->regbase);
188 debug("%s: speed=%d\n", __func__, hz);
193 static int cadence_spi_probe(struct udevice *bus)
195 struct cadence_spi_plat *plat = dev_get_plat(bus);
196 struct cadence_spi_priv *priv = dev_get_priv(bus);
200 priv->regbase = plat->regbase;
201 priv->ahbbase = plat->ahbbase;
202 priv->is_dma = plat->is_dma;
203 priv->is_decoded_cs = plat->is_decoded_cs;
204 priv->fifo_depth = plat->fifo_depth;
205 priv->fifo_width = plat->fifo_width;
206 priv->trigger_address = plat->trigger_address;
207 priv->read_delay = plat->read_delay;
208 priv->ahbsize = plat->ahbsize;
209 priv->max_hz = plat->max_hz;
211 priv->page_size = plat->page_size;
212 priv->block_size = plat->block_size;
213 priv->tshsl_ns = plat->tshsl_ns;
214 priv->tsd2d_ns = plat->tsd2d_ns;
215 priv->tchsh_ns = plat->tchsh_ns;
216 priv->tslch_ns = plat->tslch_ns;
218 if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE))
219 xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI,
220 ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS,
221 ZYNQMP_PM_REQUEST_ACK_NO, NULL);
223 if (priv->ref_clk_hz == 0) {
224 ret = clk_get_by_index(bus, 0, &clk);
226 #ifdef CONFIG_HAS_CQSPI_REF_CLK
227 priv->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
228 #elif defined(CONFIG_ARCH_SOCFPGA)
229 priv->ref_clk_hz = cm_get_qspi_controller_clk_hz();
234 priv->ref_clk_hz = clk_get_rate(&clk);
236 if (IS_ERR_VALUE(priv->ref_clk_hz))
237 return priv->ref_clk_hz;
241 priv->resets = devm_reset_bulk_get_optional(bus);
243 reset_deassert_bulk(priv->resets);
245 if (!priv->qspi_is_init) {
246 cadence_qspi_apb_controller_init(priv);
247 priv->qspi_is_init = 1;
250 priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);
252 /* Versal and Versal-NET use spi calibration to set read delay */
253 if (CONFIG_IS_ENABLED(ARCH_VERSAL) ||
254 CONFIG_IS_ENABLED(ARCH_VERSAL_NET))
255 if (priv->read_delay >= 0)
256 priv->read_delay = -1;
258 /* Reset ospi flash device */
259 return cadence_qspi_versal_flash_reset(bus);
262 static int cadence_spi_remove(struct udevice *dev)
264 struct cadence_spi_priv *priv = dev_get_priv(dev);
268 ret = reset_release_bulk(priv->resets);
273 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
275 struct cadence_spi_priv *priv = dev_get_priv(bus);
278 cadence_qspi_apb_controller_disable(priv->regbase);
281 cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
283 /* Enable Direct Access Controller */
284 if (priv->use_dac_mode)
285 cadence_qspi_apb_dac_mode_enable(priv->regbase);
288 cadence_qspi_apb_controller_enable(priv->regbase);
293 static int cadence_spi_mem_exec_op(struct spi_slave *spi,
294 const struct spi_mem_op *op)
296 struct udevice *bus = spi->dev->parent;
297 struct cadence_spi_priv *priv = dev_get_priv(bus);
298 void *base = priv->regbase;
302 /* Set Chip select */
303 cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
304 priv->is_decoded_cs);
306 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
308 * Performing reads in DAC mode forces to read minimum 4 bytes
309 * which is unsupported on some flash devices during register
310 * reads, prefer STIG mode for such small reads.
312 if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
313 mode = CQSPI_STIG_READ;
317 if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
318 mode = CQSPI_STIG_WRITE;
324 case CQSPI_STIG_READ:
325 err = cadence_qspi_apb_command_read_setup(priv, op);
327 err = cadence_qspi_apb_command_read(priv, op);
329 case CQSPI_STIG_WRITE:
330 err = cadence_qspi_apb_command_write_setup(priv, op);
332 err = cadence_qspi_apb_command_write(priv, op);
335 err = cadence_qspi_apb_read_setup(priv, op);
338 err = cadence_qspi_apb_dma_read(priv, op);
340 err = cadence_qspi_apb_read_execute(priv, op);
344 err = cadence_qspi_apb_write_setup(priv, op);
346 err = cadence_qspi_apb_write_execute(priv, op);
356 static bool cadence_spi_mem_supports_op(struct spi_slave *slave,
357 const struct spi_mem_op *op)
359 bool all_true, all_false;
362 * op->dummy.dtr is required for converting nbytes into ncycles.
363 * Also, don't check the dtr field of the op phase having zero nbytes.
365 all_true = op->cmd.dtr &&
366 (!op->addr.nbytes || op->addr.dtr) &&
367 (!op->dummy.nbytes || op->dummy.dtr) &&
368 (!op->data.nbytes || op->data.dtr);
370 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
373 /* Mixed DTR modes not supported. */
374 if (!(all_true || all_false))
378 return spi_mem_dtr_supports_op(slave, op);
380 return spi_mem_default_supports_op(slave, op);
383 static int cadence_spi_of_to_plat(struct udevice *bus)
385 struct cadence_spi_plat *plat = dev_get_plat(bus);
386 struct cadence_spi_priv *priv = dev_get_priv(bus);
389 plat->regbase = devfdt_get_addr_index_ptr(bus, 0);
390 plat->ahbbase = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahbsize);
391 plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
392 plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
393 plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
394 plat->trigger_address = dev_read_u32_default(bus,
395 "cdns,trigger-address",
397 /* Use DAC mode only when MMIO window is at least 8M wide */
398 if (plat->ahbsize >= SZ_8M)
399 priv->use_dac_mode = true;
401 plat->is_dma = dev_read_bool(bus, "cdns,is-dma");
403 /* All other parameters are embedded in the child node */
404 subnode = dev_read_first_subnode(bus);
405 if (!ofnode_valid(subnode)) {
406 printf("Error: subnode with SPI flash config missing!\n");
410 /* Use 500 KHz as a suitable default */
411 plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
414 /* Read other parameters from DT */
415 plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
416 plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
417 plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
419 plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
421 plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
422 plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
424 * Read delay should be an unsigned value but we use a signed integer
425 * so that negative values can indicate that the device tree did not
426 * specify any signed values and we need to perform the calibration
427 * sequence to find it out.
429 plat->read_delay = ofnode_read_s32_default(subnode, "cdns,read-delay",
432 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
433 __func__, plat->regbase, plat->ahbbase, plat->max_hz,
439 static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
440 .exec_op = cadence_spi_mem_exec_op,
441 .supports_op = cadence_spi_mem_supports_op,
444 static const struct dm_spi_ops cadence_spi_ops = {
445 .set_speed = cadence_spi_set_speed,
446 .set_mode = cadence_spi_set_mode,
447 .mem_ops = &cadence_spi_mem_ops,
449 * cs_info is not needed, since we require all chip selects to be
450 * in the device tree explicitly
454 static const struct udevice_id cadence_spi_ids[] = {
455 { .compatible = "cdns,qspi-nor" },
456 { .compatible = "ti,am654-ospi" },
460 U_BOOT_DRIVER(cadence_spi) = {
461 .name = "cadence_spi",
463 .of_match = cadence_spi_ids,
464 .ops = &cadence_spi_ops,
465 .of_to_plat = cadence_spi_of_to_plat,
466 .plat_auto = sizeof(struct cadence_spi_plat),
467 .priv_auto = sizeof(struct cadence_spi_priv),
468 .probe = cadence_spi_probe,
469 .remove = cadence_spi_remove,
470 .flags = DM_FLAG_OS_PREPARE,