drivers/spi/cadence_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012
   4  * Altera Corporation <www.altera.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <log.h>
  10 #include <asm-generic/io.h>
  11 #include <dm.h>
  12 #include <fdtdec.h>
  13 #include <malloc.h>
  14 #include <reset.h>
  15 #include <spi.h>
  16 #include <spi-mem.h>
  17 #include <dm/device_compat.h>
  18 #include <linux/err.h>
  19 #include <linux/errno.h>
  20 #include <linux/sizes.h>
  21 #include <zynqmp_firmware.h>
  22 #include "cadence_qspi.h"
  23 #include <dt-bindings/power/xlnx-versal-power.h>
  24
  25 #define NSEC_PER_SEC                    1000000000L
  26
  27 #define CQSPI_STIG_READ                 0
  28 #define CQSPI_STIG_WRITE                1
  29 #define CQSPI_READ                      2
  30 #define CQSPI_WRITE                     3
  31
  32 __weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
  33                                      const struct spi_mem_op *op)
  34 {
  35         return 0;
  36 }
  37
  38 __weak int cadence_qspi_versal_flash_reset(struct udevice *dev)
  39 {
  40         return 0;
  41 }
  42
  43 static int cadence_spi_write_speed(struct udevice *bus, uint hz)
  44 {
  45         struct cadence_spi_priv *priv = dev_get_priv(bus);
  46
  47         cadence_qspi_apb_config_baudrate_div(priv->regbase,
  48                                              priv->ref_clk_hz, hz);
  49
  50         /* Reconfigure delay timing if speed is changed. */
  51         cadence_qspi_apb_delay(priv->regbase, priv->ref_clk_hz, hz,
  52                                priv->tshsl_ns, priv->tsd2d_ns,
  53                                priv->tchsh_ns, priv->tslch_ns);
  54
  55         return 0;
  56 }
  57
  58 static int cadence_spi_read_id(struct cadence_spi_priv *priv, u8 len,
  59                                u8 *idcode)
  60 {
  61         int err;
  62
  63         struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
  64                                           SPI_MEM_OP_NO_ADDR,
  65                                           SPI_MEM_OP_NO_DUMMY,
  66                                           SPI_MEM_OP_DATA_IN(len, idcode, 1));
  67
  68         err = cadence_qspi_apb_command_read_setup(priv, &op);
  69         if (!err)
  70                 err = cadence_qspi_apb_command_read(priv, &op);
  71
  72         return err;
  73 }
  74
  75 /* Calibration sequence to determine the read data capture delay register */
  76 static int spi_calibration(struct udevice *bus, uint hz)
  77 {
  78         struct cadence_spi_priv *priv = dev_get_priv(bus);
  79         void *base = priv->regbase;
  80         unsigned int idcode = 0, temp = 0;
  81         int err = 0, i, range_lo = -1, range_hi = -1;
  82
  83         /* start with slowest clock (1 MHz) */
  84         cadence_spi_write_speed(bus, 1000000);
  85
  86         /* configure the read data capture delay register to 0 */
  87         cadence_qspi_apb_readdata_capture(base, 1, 0);
  88
  89         /* Enable QSPI */
  90         cadence_qspi_apb_controller_enable(base);
  91
  92         /* read the ID which will be our golden value */
  93         err = cadence_spi_read_id(priv, 3, (u8 *)&idcode);
  94         if (err) {
  95                 puts("SF: Calibration failed (read)\n");
  96                 return err;
  97         }
  98
  99         /* use back the intended clock and find low range */
 100         cadence_spi_write_speed(bus, hz);
 101         for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
 102                 /* Disable QSPI */
 103                 cadence_qspi_apb_controller_disable(base);
 104
 105                 /* reconfigure the read data capture delay register */
 106                 cadence_qspi_apb_readdata_capture(base, 1, i);
 107
 108                 /* Enable back QSPI */
 109                 cadence_qspi_apb_controller_enable(base);
 110
 111                 /* issue a RDID to get the ID value */
 112                 err = cadence_spi_read_id(priv, 3, (u8 *)&temp);
 113                 if (err) {
 114                         puts("SF: Calibration failed (read)\n");
 115                         return err;
 116                 }
 117
 118                 /* search for range lo */
 119                 if (range_lo == -1 && temp == idcode) {
 120                         range_lo = i;
 121                         continue;
 122                 }
 123
 124                 /* search for range hi */
 125                 if (range_lo != -1 && temp != idcode) {
 126                         range_hi = i - 1;
 127                         break;
 128                 }
 129                 range_hi = i;
 130         }
 131
 132         if (range_lo == -1) {
 133                 puts("SF: Calibration failed (low range)\n");
 134                 return err;
 135         }
 136
 137         /* Disable QSPI for subsequent initialization */
 138         cadence_qspi_apb_controller_disable(base);
 139
 140         /* configure the final value for read data capture delay register */
 141         cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
 142         debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
 143               (range_hi + range_lo) / 2, range_lo, range_hi);
 144
 145         /* just to ensure we do once only when speed or chip select change */
 146         priv->qspi_calibrated_hz = hz;
 147         priv->qspi_calibrated_cs = spi_chip_select(bus);
 148
 149         return 0;
 150 }
 151
 152 static int cadence_spi_set_speed(struct udevice *bus, uint hz)
 153 {
 154         struct cadence_spi_priv *priv = dev_get_priv(bus);
 155         int err;
 156
 157         if (!hz || hz > priv->max_hz)
 158                 hz = priv->max_hz;
 159         /* Disable QSPI */
 160         cadence_qspi_apb_controller_disable(priv->regbase);
 161
 162         /*
 163          * If the device tree already provides a read delay value, use that
 164          * instead of calibrating.
 165          */
 166         if (priv->read_delay >= 0) {
 167                 cadence_spi_write_speed(bus, hz);
 168                 cadence_qspi_apb_readdata_capture(priv->regbase, 1,
 169                                                   priv->read_delay);
 170         } else if (priv->previous_hz != hz ||
 171                    priv->qspi_calibrated_hz != hz ||
 172                    priv->qspi_calibrated_cs != spi_chip_select(bus)) {
 173                 /*
 174                  * Calibration required for different current SCLK speed,
 175                  * requested SCLK speed or chip select
 176                  */
 177                 err = spi_calibration(bus, hz);
 178                 if (err)
 179                         return err;
 180
 181                 /* prevent calibration run when same as previous request */
 182                 priv->previous_hz = hz;
 183         }
 184
 185         /* Enable QSPI */
 186         cadence_qspi_apb_controller_enable(priv->regbase);
 187
 188         debug("%s: speed=%d\n", __func__, hz);
 189
 190         return 0;
 191 }
 192
 193 static int cadence_spi_probe(struct udevice *bus)
 194 {
 195         struct cadence_spi_plat *plat = dev_get_plat(bus);
 196         struct cadence_spi_priv *priv = dev_get_priv(bus);
 197         struct clk clk;
 198         int ret;
 199
 200         priv->regbase           = plat->regbase;
 201         priv->ahbbase           = plat->ahbbase;
 202         priv->is_dma            = plat->is_dma;
 203         priv->is_decoded_cs     = plat->is_decoded_cs;
 204         priv->fifo_depth        = plat->fifo_depth;
 205         priv->fifo_width        = plat->fifo_width;
 206         priv->trigger_address   = plat->trigger_address;
 207         priv->read_delay        = plat->read_delay;
 208         priv->ahbsize           = plat->ahbsize;
 209         priv->max_hz            = plat->max_hz;
 210
 211         priv->page_size         = plat->page_size;
 212         priv->block_size        = plat->block_size;
 213         priv->tshsl_ns          = plat->tshsl_ns;
 214         priv->tsd2d_ns          = plat->tsd2d_ns;
 215         priv->tchsh_ns          = plat->tchsh_ns;
 216         priv->tslch_ns          = plat->tslch_ns;
 217
 218         if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE))
 219                 xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI,
 220                                   ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS,
 221                                   ZYNQMP_PM_REQUEST_ACK_NO, NULL);
 222
 223         if (priv->ref_clk_hz == 0) {
 224                 ret = clk_get_by_index(bus, 0, &clk);
 225                 if (ret) {
 226 #ifdef CONFIG_HAS_CQSPI_REF_CLK
 227                         priv->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
 228 #elif defined(CONFIG_ARCH_SOCFPGA)
 229                         priv->ref_clk_hz = cm_get_qspi_controller_clk_hz();
 230 #else
 231                         return ret;
 232 #endif
 233                 } else {
 234                         priv->ref_clk_hz = clk_get_rate(&clk);
 235                         clk_free(&clk);
 236                         if (IS_ERR_VALUE(priv->ref_clk_hz))
 237                                 return priv->ref_clk_hz;
 238                 }
 239         }
 240
 241         priv->resets = devm_reset_bulk_get_optional(bus);
 242         if (priv->resets)
 243                 reset_deassert_bulk(priv->resets);
 244
 245         if (!priv->qspi_is_init) {
 246                 cadence_qspi_apb_controller_init(priv);
 247                 priv->qspi_is_init = 1;
 248         }
 249
 250         priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);
 251
 252         /* Versal and Versal-NET use spi calibration to set read delay */
 253         if (CONFIG_IS_ENABLED(ARCH_VERSAL) ||
 254             CONFIG_IS_ENABLED(ARCH_VERSAL_NET))
 255                 if (priv->read_delay >= 0)
 256                         priv->read_delay = -1;
 257
 258         /* Reset ospi flash device */
 259         return cadence_qspi_versal_flash_reset(bus);
 260 }
 261
 262 static int cadence_spi_remove(struct udevice *dev)
 263 {
 264         struct cadence_spi_priv *priv = dev_get_priv(dev);
 265         int ret = 0;
 266
 267         if (priv->resets)
 268                 ret = reset_release_bulk(priv->resets);
 269
 270         return ret;
 271 }
 272
 273 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
 274 {
 275         struct cadence_spi_priv *priv = dev_get_priv(bus);
 276
 277         /* Disable QSPI */
 278         cadence_qspi_apb_controller_disable(priv->regbase);
 279
 280         /* Set SPI mode */
 281         cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
 282
 283         /* Enable Direct Access Controller */
 284         if (priv->use_dac_mode)
 285                 cadence_qspi_apb_dac_mode_enable(priv->regbase);
 286
 287         /* Enable QSPI */
 288         cadence_qspi_apb_controller_enable(priv->regbase);
 289
 290         return 0;
 291 }
 292
 293 static int cadence_spi_mem_exec_op(struct spi_slave *spi,
 294                                    const struct spi_mem_op *op)
 295 {
 296         struct udevice *bus = spi->dev->parent;
 297         struct cadence_spi_priv *priv = dev_get_priv(bus);
 298         void *base = priv->regbase;
 299         int err = 0;
 300         u32 mode;
 301
 302         /* Set Chip select */
 303         cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
 304                                     priv->is_decoded_cs);
 305
 306         if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
 307                 /*
 308                  * Performing reads in DAC mode forces to read minimum 4 bytes
 309                  * which is unsupported on some flash devices during register
 310                  * reads, prefer STIG mode for such small reads.
 311                  */
 312                 if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
 313                         mode = CQSPI_STIG_READ;
 314                 else
 315                         mode = CQSPI_READ;
 316         } else {
 317                 if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
 318                         mode = CQSPI_STIG_WRITE;
 319                 else
 320                         mode = CQSPI_WRITE;
 321         }
 322
 323         switch (mode) {
 324         case CQSPI_STIG_READ:
 325                 err = cadence_qspi_apb_command_read_setup(priv, op);
 326                 if (!err)
 327                         err = cadence_qspi_apb_command_read(priv, op);
 328                 break;
 329         case CQSPI_STIG_WRITE:
 330                 err = cadence_qspi_apb_command_write_setup(priv, op);
 331                 if (!err)
 332                         err = cadence_qspi_apb_command_write(priv, op);
 333                 break;
 334         case CQSPI_READ:
 335                 err = cadence_qspi_apb_read_setup(priv, op);
 336                 if (!err) {
 337                         if (priv->is_dma)
 338                                 err = cadence_qspi_apb_dma_read(priv, op);
 339                         else
 340                                 err = cadence_qspi_apb_read_execute(priv, op);
 341                 }
 342                 break;
 343         case CQSPI_WRITE:
 344                 err = cadence_qspi_apb_write_setup(priv, op);
 345                 if (!err)
 346                         err = cadence_qspi_apb_write_execute(priv, op);
 347                 break;
 348         default:
 349                 err = -1;
 350                 break;
 351         }
 352
 353         return err;
 354 }
 355
 356 static bool cadence_spi_mem_supports_op(struct spi_slave *slave,
 357                                         const struct spi_mem_op *op)
 358 {
 359         bool all_true, all_false;
 360
 361         /*
 362          * op->dummy.dtr is required for converting nbytes into ncycles.
 363          * Also, don't check the dtr field of the op phase having zero nbytes.
 364          */
 365         all_true = op->cmd.dtr &&
 366                    (!op->addr.nbytes || op->addr.dtr) &&
 367                    (!op->dummy.nbytes || op->dummy.dtr) &&
 368                    (!op->data.nbytes || op->data.dtr);
 369
 370         all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
 371                     !op->data.dtr;
 372
 373         /* Mixed DTR modes not supported. */
 374         if (!(all_true || all_false))
 375                 return false;
 376
 377         if (all_true)
 378                 return spi_mem_dtr_supports_op(slave, op);
 379         else
 380                 return spi_mem_default_supports_op(slave, op);
 381 }
 382
 383 static int cadence_spi_of_to_plat(struct udevice *bus)
 384 {
 385         struct cadence_spi_plat *plat = dev_get_plat(bus);
 386         struct cadence_spi_priv *priv = dev_get_priv(bus);
 387         ofnode subnode;
 388
 389         plat->regbase = devfdt_get_addr_index_ptr(bus, 0);
 390         plat->ahbbase = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahbsize);
 391         plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
 392         plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
 393         plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
 394         plat->trigger_address = dev_read_u32_default(bus,
 395                                                      "cdns,trigger-address",
 396                                                      0);
 397         /* Use DAC mode only when MMIO window is at least 8M wide */
 398         if (plat->ahbsize >= SZ_8M)
 399                 priv->use_dac_mode = true;
 400
 401         plat->is_dma = dev_read_bool(bus, "cdns,is-dma");
 402
 403         /* All other parameters are embedded in the child node */
 404         subnode = dev_read_first_subnode(bus);
 405         if (!ofnode_valid(subnode)) {
 406                 printf("Error: subnode with SPI flash config missing!\n");
 407                 return -ENODEV;
 408         }
 409
 410         /* Use 500 KHz as a suitable default */
 411         plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
 412                                                500000);
 413
 414         /* Read other parameters from DT */
 415         plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
 416         plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
 417         plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
 418                                                  200);
 419         plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
 420                                                  255);
 421         plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
 422         plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
 423         /*
 424          * Read delay should be an unsigned value but we use a signed integer
 425          * so that negative values can indicate that the device tree did not
 426          * specify any signed values and we need to perform the calibration
 427          * sequence to find it out.
 428          */
 429         plat->read_delay = ofnode_read_s32_default(subnode, "cdns,read-delay",
 430                                                    -1);
 431
 432         debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
 433               __func__, plat->regbase, plat->ahbbase, plat->max_hz,
 434               plat->page_size);
 435
 436         return 0;
 437 }
 438
 439 static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
 440         .exec_op = cadence_spi_mem_exec_op,
 441         .supports_op = cadence_spi_mem_supports_op,
 442 };
 443
 444 static const struct dm_spi_ops cadence_spi_ops = {
 445         .set_speed      = cadence_spi_set_speed,
 446         .set_mode       = cadence_spi_set_mode,
 447         .mem_ops        = &cadence_spi_mem_ops,
 448         /*
 449          * cs_info is not needed, since we require all chip selects to be
 450          * in the device tree explicitly
 451          */
 452 };
 453
 454 static const struct udevice_id cadence_spi_ids[] = {
 455         { .compatible = "cdns,qspi-nor" },
 456         { .compatible = "ti,am654-ospi" },
 457         { }
 458 };
 459
 460 U_BOOT_DRIVER(cadence_spi) = {
 461         .name = "cadence_spi",
 462         .id = UCLASS_SPI,
 463         .of_match = cadence_spi_ids,
 464         .ops = &cadence_spi_ops,
 465         .of_to_plat = cadence_spi_of_to_plat,
 466         .plat_auto      = sizeof(struct cadence_spi_plat),
 467         .priv_auto      = sizeof(struct cadence_spi_priv),
 468         .probe = cadence_spi_probe,
 469         .remove = cadence_spi_remove,
 470         .flags = DM_FLAG_OS_PREPARE,
 471 };