drivers/spi/cadence_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012
   4  * Altera Corporation <www.altera.com>
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <fdtdec.h>
  10 #include <malloc.h>
  11 #include <reset.h>
  12 #include <spi.h>
  13 #include <linux/errno.h>
  14 #include "cadence_qspi.h"
  15
  16 #define CQSPI_STIG_READ                 0
  17 #define CQSPI_STIG_WRITE                1
  18 #define CQSPI_INDIRECT_READ             2
  19 #define CQSPI_INDIRECT_WRITE            3
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 static int cadence_spi_write_speed(struct udevice *bus, uint hz)
  24 {
  25         struct cadence_spi_platdata *plat = bus->platdata;
  26         struct cadence_spi_priv *priv = dev_get_priv(bus);
  27
  28         cadence_qspi_apb_config_baudrate_div(priv->regbase,
  29                                              CONFIG_CQSPI_REF_CLK, hz);
  30
  31         /* Reconfigure delay timing if speed is changed. */
  32         cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
  33                                plat->tshsl_ns, plat->tsd2d_ns,
  34                                plat->tchsh_ns, plat->tslch_ns);
  35
  36         return 0;
  37 }
  38
  39 /* Calibration sequence to determine the read data capture delay register */
  40 static int spi_calibration(struct udevice *bus, uint hz)
  41 {
  42         struct cadence_spi_priv *priv = dev_get_priv(bus);
  43         void *base = priv->regbase;
  44         u8 opcode_rdid = 0x9F;
  45         unsigned int idcode = 0, temp = 0;
  46         int err = 0, i, range_lo = -1, range_hi = -1;
  47
  48         /* start with slowest clock (1 MHz) */
  49         cadence_spi_write_speed(bus, 1000000);
  50
  51         /* configure the read data capture delay register to 0 */
  52         cadence_qspi_apb_readdata_capture(base, 1, 0);
  53
  54         /* Enable QSPI */
  55         cadence_qspi_apb_controller_enable(base);
  56
  57         /* read the ID which will be our golden value */
  58         err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
  59                 3, (u8 *)&idcode);
  60         if (err) {
  61                 puts("SF: Calibration failed (read)\n");
  62                 return err;
  63         }
  64
  65         /* use back the intended clock and find low range */
  66         cadence_spi_write_speed(bus, hz);
  67         for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
  68                 /* Disable QSPI */
  69                 cadence_qspi_apb_controller_disable(base);
  70
  71                 /* reconfigure the read data capture delay register */
  72                 cadence_qspi_apb_readdata_capture(base, 1, i);
  73
  74                 /* Enable back QSPI */
  75                 cadence_qspi_apb_controller_enable(base);
  76
  77                 /* issue a RDID to get the ID value */
  78                 err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
  79                         3, (u8 *)&temp);
  80                 if (err) {
  81                         puts("SF: Calibration failed (read)\n");
  82                         return err;
  83                 }
  84
  85                 /* search for range lo */
  86                 if (range_lo == -1 && temp == idcode) {
  87                         range_lo = i;
  88                         continue;
  89                 }
  90
  91                 /* search for range hi */
  92                 if (range_lo != -1 && temp != idcode) {
  93                         range_hi = i - 1;
  94                         break;
  95                 }
  96                 range_hi = i;
  97         }
  98
  99         if (range_lo == -1) {
 100                 puts("SF: Calibration failed (low range)\n");
 101                 return err;
 102         }
 103
 104         /* Disable QSPI for subsequent initialization */
 105         cadence_qspi_apb_controller_disable(base);
 106
 107         /* configure the final value for read data capture delay register */
 108         cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
 109         debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
 110               (range_hi + range_lo) / 2, range_lo, range_hi);
 111
 112         /* just to ensure we do once only when speed or chip select change */
 113         priv->qspi_calibrated_hz = hz;
 114         priv->qspi_calibrated_cs = spi_chip_select(bus);
 115
 116         return 0;
 117 }
 118
 119 static int cadence_spi_set_speed(struct udevice *bus, uint hz)
 120 {
 121         struct cadence_spi_platdata *plat = bus->platdata;
 122         struct cadence_spi_priv *priv = dev_get_priv(bus);
 123         int err;
 124
 125         if (hz > plat->max_hz)
 126                 hz = plat->max_hz;
 127
 128         /* Disable QSPI */
 129         cadence_qspi_apb_controller_disable(priv->regbase);
 130
 131         /*
 132          * Calibration required for different current SCLK speed, requested
 133          * SCLK speed or chip select
 134          */
 135         if (priv->previous_hz != hz ||
 136             priv->qspi_calibrated_hz != hz ||
 137             priv->qspi_calibrated_cs != spi_chip_select(bus)) {
 138                 err = spi_calibration(bus, hz);
 139                 if (err)
 140                         return err;
 141
 142                 /* prevent calibration run when same as previous request */
 143                 priv->previous_hz = hz;
 144         }
 145
 146         /* Enable QSPI */
 147         cadence_qspi_apb_controller_enable(priv->regbase);
 148
 149         debug("%s: speed=%d\n", __func__, hz);
 150
 151         return 0;
 152 }
 153
 154 static int cadence_spi_probe(struct udevice *bus)
 155 {
 156         struct cadence_spi_platdata *plat = bus->platdata;
 157         struct cadence_spi_priv *priv = dev_get_priv(bus);
 158         int ret;
 159
 160         priv->regbase = plat->regbase;
 161         priv->ahbbase = plat->ahbbase;
 162
 163         ret = reset_get_bulk(bus, &priv->resets);
 164         if (ret)
 165                 dev_warn(bus, "Can't get reset: %d\n", ret);
 166         else
 167                 reset_deassert_bulk(&priv->resets);
 168
 169         if (!priv->qspi_is_init) {
 170                 cadence_qspi_apb_controller_init(plat);
 171                 priv->qspi_is_init = 1;
 172         }
 173
 174         return 0;
 175 }
 176
 177 static int cadence_spi_remove(struct udevice *dev)
 178 {
 179         struct cadence_spi_priv *priv = dev_get_priv(dev);
 180
 181         return reset_release_bulk(&priv->resets);
 182 }
 183
 184 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
 185 {
 186         struct cadence_spi_priv *priv = dev_get_priv(bus);
 187
 188         /* Disable QSPI */
 189         cadence_qspi_apb_controller_disable(priv->regbase);
 190
 191         /* Set SPI mode */
 192         cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
 193
 194         /* Enable QSPI */
 195         cadence_qspi_apb_controller_enable(priv->regbase);
 196
 197         return 0;
 198 }
 199
 200 static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
 201                             const void *dout, void *din, unsigned long flags)
 202 {
 203         struct udevice *bus = dev->parent;
 204         struct cadence_spi_platdata *plat = bus->platdata;
 205         struct cadence_spi_priv *priv = dev_get_priv(bus);
 206         struct dm_spi_slave_platdata *dm_plat = dev_get_parent_platdata(dev);
 207         void *base = priv->regbase;
 208         u8 *cmd_buf = priv->cmd_buf;
 209         size_t data_bytes;
 210         int err = 0;
 211         u32 mode = CQSPI_STIG_WRITE;
 212
 213         if (flags & SPI_XFER_BEGIN) {
 214                 /* copy command to local buffer */
 215                 priv->cmd_len = bitlen / 8;
 216                 memcpy(cmd_buf, dout, priv->cmd_len);
 217         }
 218
 219         if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) {
 220                 /* if start and end bit are set, the data bytes is 0. */
 221                 data_bytes = 0;
 222         } else {
 223                 data_bytes = bitlen / 8;
 224         }
 225         debug("%s: len=%zu [bytes]\n", __func__, data_bytes);
 226
 227         /* Set Chip select */
 228         cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
 229                                     plat->is_decoded_cs);
 230
 231         if ((flags & SPI_XFER_END) || (flags == 0)) {
 232                 if (priv->cmd_len == 0) {
 233                         printf("QSPI: Error, command is empty.\n");
 234                         return -1;
 235                 }
 236
 237                 if (din && data_bytes) {
 238                         /* read */
 239                         /* Use STIG if no address. */
 240                         if (!CQSPI_IS_ADDR(priv->cmd_len))
 241                                 mode = CQSPI_STIG_READ;
 242                         else
 243                                 mode = CQSPI_INDIRECT_READ;
 244                 } else if (dout && !(flags & SPI_XFER_BEGIN)) {
 245                         /* write */
 246                         if (!CQSPI_IS_ADDR(priv->cmd_len))
 247                                 mode = CQSPI_STIG_WRITE;
 248                         else
 249                                 mode = CQSPI_INDIRECT_WRITE;
 250                 }
 251
 252                 switch (mode) {
 253                 case CQSPI_STIG_READ:
 254                         err = cadence_qspi_apb_command_read(
 255                                 base, priv->cmd_len, cmd_buf,
 256                                 data_bytes, din);
 257
 258                 break;
 259                 case CQSPI_STIG_WRITE:
 260                         err = cadence_qspi_apb_command_write(base,
 261                                 priv->cmd_len, cmd_buf,
 262                                 data_bytes, dout);
 263                 break;
 264                 case CQSPI_INDIRECT_READ:
 265                         err = cadence_qspi_apb_indirect_read_setup(plat,
 266                                 priv->cmd_len, dm_plat->mode, cmd_buf);
 267                         if (!err) {
 268                                 err = cadence_qspi_apb_indirect_read_execute
 269                                 (plat, data_bytes, din);
 270                         }
 271                 break;
 272                 case CQSPI_INDIRECT_WRITE:
 273                         err = cadence_qspi_apb_indirect_write_setup
 274                                 (plat, priv->cmd_len, dm_plat->mode, cmd_buf);
 275                         if (!err) {
 276                                 err = cadence_qspi_apb_indirect_write_execute
 277                                 (plat, data_bytes, dout);
 278                         }
 279                 break;
 280                 default:
 281                         err = -1;
 282                         break;
 283                 }
 284
 285                 if (flags & SPI_XFER_END) {
 286                         /* clear command buffer */
 287                         memset(cmd_buf, 0, sizeof(priv->cmd_buf));
 288                         priv->cmd_len = 0;
 289                 }
 290         }
 291
 292         return err;
 293 }
 294
 295 static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
 296 {
 297         struct cadence_spi_platdata *plat = bus->platdata;
 298         const void *blob = gd->fdt_blob;
 299         int node = dev_of_offset(bus);
 300         int subnode;
 301
 302         plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
 303         plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1);
 304         plat->is_decoded_cs = fdtdec_get_bool(blob, node, "cdns,is-decoded-cs");
 305         plat->fifo_depth = fdtdec_get_uint(blob, node, "cdns,fifo-depth", 128);
 306         plat->fifo_width = fdtdec_get_uint(blob, node, "cdns,fifo-width", 4);
 307         plat->trigger_address = fdtdec_get_uint(blob, node,
 308                                                 "cdns,trigger-address", 0);
 309
 310         /* All other paramters are embedded in the child node */
 311         subnode = fdt_first_subnode(blob, node);
 312         if (subnode < 0) {
 313                 printf("Error: subnode with SPI flash config missing!\n");
 314                 return -ENODEV;
 315         }
 316
 317         /* Use 500 KHz as a suitable default */
 318         plat->max_hz = fdtdec_get_uint(blob, subnode, "spi-max-frequency",
 319                                        500000);
 320
 321         /* Read other parameters from DT */
 322         plat->page_size = fdtdec_get_uint(blob, subnode, "page-size", 256);
 323         plat->block_size = fdtdec_get_uint(blob, subnode, "block-size", 16);
 324         plat->tshsl_ns = fdtdec_get_uint(blob, subnode, "cdns,tshsl-ns", 200);
 325         plat->tsd2d_ns = fdtdec_get_uint(blob, subnode, "cdns,tsd2d-ns", 255);
 326         plat->tchsh_ns = fdtdec_get_uint(blob, subnode, "cdns,tchsh-ns", 20);
 327         plat->tslch_ns = fdtdec_get_uint(blob, subnode, "cdns,tslch-ns", 20);
 328
 329         debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
 330               __func__, plat->regbase, plat->ahbbase, plat->max_hz,
 331               plat->page_size);
 332
 333         return 0;
 334 }
 335
 336 static const struct dm_spi_ops cadence_spi_ops = {
 337         .xfer           = cadence_spi_xfer,
 338         .set_speed      = cadence_spi_set_speed,
 339         .set_mode       = cadence_spi_set_mode,
 340         /*
 341          * cs_info is not needed, since we require all chip selects to be
 342          * in the device tree explicitly
 343          */
 344 };
 345
 346 static const struct udevice_id cadence_spi_ids[] = {
 347         { .compatible = "cdns,qspi-nor" },
 348         { }
 349 };
 350
 351 U_BOOT_DRIVER(cadence_spi) = {
 352         .name = "cadence_spi",
 353         .id = UCLASS_SPI,
 354         .of_match = cadence_spi_ids,
 355         .ops = &cadence_spi_ops,
 356         .ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
 357         .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
 358         .priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
 359         .probe = cadence_spi_probe,
 360         .remove = cadence_spi_remove,
 361         .flags = DM_FLAG_OS_PREPARE,
 362 };