1 // SPDX-License-Identifier: GPL-2.0+
4 * Altera Corporation <www.altera.com>
10 #include <asm-generic/io.h>
17 #include <dm/device_compat.h>
18 #include <linux/err.h>
19 #include <linux/errno.h>
20 #include <linux/sizes.h>
21 #include "cadence_qspi.h"
23 #define NSEC_PER_SEC 1000000000L
25 #define CQSPI_STIG_READ 0
26 #define CQSPI_STIG_WRITE 1
30 static int cadence_spi_write_speed(struct udevice *bus, uint hz)
32 struct cadence_spi_plat *plat = dev_get_plat(bus);
33 struct cadence_spi_priv *priv = dev_get_priv(bus);
35 cadence_qspi_apb_config_baudrate_div(priv->regbase,
36 plat->ref_clk_hz, hz);
38 /* Reconfigure delay timing if speed is changed. */
39 cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
40 plat->tshsl_ns, plat->tsd2d_ns,
41 plat->tchsh_ns, plat->tslch_ns);
46 static int cadence_spi_read_id(struct cadence_spi_plat *plat, u8 len,
49 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
52 SPI_MEM_OP_DATA_IN(len, idcode, 1));
54 return cadence_qspi_apb_command_read(plat, &op);
57 /* Calibration sequence to determine the read data capture delay register */
58 static int spi_calibration(struct udevice *bus, uint hz)
60 struct cadence_spi_priv *priv = dev_get_priv(bus);
61 struct cadence_spi_plat *plat = dev_get_plat(bus);
62 void *base = priv->regbase;
63 unsigned int idcode = 0, temp = 0;
64 int err = 0, i, range_lo = -1, range_hi = -1;
66 /* start with slowest clock (1 MHz) */
67 cadence_spi_write_speed(bus, 1000000);
69 /* configure the read data capture delay register to 0 */
70 cadence_qspi_apb_readdata_capture(base, 1, 0);
73 cadence_qspi_apb_controller_enable(base);
75 /* read the ID which will be our golden value */
76 err = cadence_spi_read_id(plat, 3, (u8 *)&idcode);
78 puts("SF: Calibration failed (read)\n");
82 /* use back the intended clock and find low range */
83 cadence_spi_write_speed(bus, hz);
84 for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
86 cadence_qspi_apb_controller_disable(base);
88 /* reconfigure the read data capture delay register */
89 cadence_qspi_apb_readdata_capture(base, 1, i);
91 /* Enable back QSPI */
92 cadence_qspi_apb_controller_enable(base);
94 /* issue a RDID to get the ID value */
95 err = cadence_spi_read_id(plat, 3, (u8 *)&temp);
97 puts("SF: Calibration failed (read)\n");
101 /* search for range lo */
102 if (range_lo == -1 && temp == idcode) {
107 /* search for range hi */
108 if (range_lo != -1 && temp != idcode) {
115 if (range_lo == -1) {
116 puts("SF: Calibration failed (low range)\n");
120 /* Disable QSPI for subsequent initialization */
121 cadence_qspi_apb_controller_disable(base);
123 /* configure the final value for read data capture delay register */
124 cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
125 debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
126 (range_hi + range_lo) / 2, range_lo, range_hi);
128 /* just to ensure we do once only when speed or chip select change */
129 priv->qspi_calibrated_hz = hz;
130 priv->qspi_calibrated_cs = spi_chip_select(bus);
135 static int cadence_spi_set_speed(struct udevice *bus, uint hz)
137 struct cadence_spi_plat *plat = dev_get_plat(bus);
138 struct cadence_spi_priv *priv = dev_get_priv(bus);
141 if (hz > plat->max_hz)
145 cadence_qspi_apb_controller_disable(priv->regbase);
148 * If the device tree already provides a read delay value, use that
149 * instead of calibrating.
151 if (plat->read_delay >= 0) {
152 cadence_spi_write_speed(bus, hz);
153 cadence_qspi_apb_readdata_capture(priv->regbase, 1,
155 } else if (priv->previous_hz != hz ||
156 priv->qspi_calibrated_hz != hz ||
157 priv->qspi_calibrated_cs != spi_chip_select(bus)) {
159 * Calibration required for different current SCLK speed,
160 * requested SCLK speed or chip select
162 err = spi_calibration(bus, hz);
166 /* prevent calibration run when same as previous request */
167 priv->previous_hz = hz;
171 cadence_qspi_apb_controller_enable(priv->regbase);
173 debug("%s: speed=%d\n", __func__, hz);
178 static int cadence_spi_probe(struct udevice *bus)
180 struct cadence_spi_plat *plat = dev_get_plat(bus);
181 struct cadence_spi_priv *priv = dev_get_priv(bus);
185 priv->regbase = plat->regbase;
186 priv->ahbbase = plat->ahbbase;
188 if (plat->ref_clk_hz == 0) {
189 ret = clk_get_by_index(bus, 0, &clk);
191 #ifdef CONFIG_HAS_CQSPI_REF_CLK
192 plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
193 #elif defined(CONFIG_ARCH_SOCFPGA)
194 plat->ref_clk_hz = cm_get_qspi_controller_clk_hz();
199 plat->ref_clk_hz = clk_get_rate(&clk);
201 if (IS_ERR_VALUE(plat->ref_clk_hz))
202 return plat->ref_clk_hz;
206 priv->resets = devm_reset_bulk_get_optional(bus);
208 reset_deassert_bulk(priv->resets);
210 if (!priv->qspi_is_init) {
211 cadence_qspi_apb_controller_init(plat);
212 priv->qspi_is_init = 1;
215 plat->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, plat->ref_clk_hz);
220 static int cadence_spi_remove(struct udevice *dev)
222 struct cadence_spi_priv *priv = dev_get_priv(dev);
226 ret = reset_release_bulk(priv->resets);
231 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
233 struct cadence_spi_plat *plat = dev_get_plat(bus);
234 struct cadence_spi_priv *priv = dev_get_priv(bus);
237 cadence_qspi_apb_controller_disable(priv->regbase);
240 cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
242 /* Enable Direct Access Controller */
243 if (plat->use_dac_mode)
244 cadence_qspi_apb_dac_mode_enable(priv->regbase);
247 cadence_qspi_apb_controller_enable(priv->regbase);
252 static int cadence_spi_mem_exec_op(struct spi_slave *spi,
253 const struct spi_mem_op *op)
255 struct udevice *bus = spi->dev->parent;
256 struct cadence_spi_plat *plat = dev_get_plat(bus);
257 struct cadence_spi_priv *priv = dev_get_priv(bus);
258 void *base = priv->regbase;
262 /* Set Chip select */
263 cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
264 plat->is_decoded_cs);
266 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
267 if (!op->addr.nbytes)
268 mode = CQSPI_STIG_READ;
272 if (!op->addr.nbytes || !op->data.buf.out)
273 mode = CQSPI_STIG_WRITE;
279 case CQSPI_STIG_READ:
280 err = cadence_qspi_apb_command_read_setup(plat, op);
282 err = cadence_qspi_apb_command_read(plat, op);
284 case CQSPI_STIG_WRITE:
285 err = cadence_qspi_apb_command_write_setup(plat, op);
287 err = cadence_qspi_apb_command_write(plat, op);
290 err = cadence_qspi_apb_read_setup(plat, op);
292 err = cadence_qspi_apb_read_execute(plat, op);
295 err = cadence_qspi_apb_write_setup(plat, op);
297 err = cadence_qspi_apb_write_execute(plat, op);
307 static bool cadence_spi_mem_supports_op(struct spi_slave *slave,
308 const struct spi_mem_op *op)
310 bool all_true, all_false;
312 all_true = op->cmd.dtr && op->addr.dtr && op->dummy.dtr &&
314 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
317 /* Mixed DTR modes not supported. */
318 if (!(all_true || all_false))
322 return spi_mem_dtr_supports_op(slave, op);
324 return spi_mem_default_supports_op(slave, op);
327 static int cadence_spi_of_to_plat(struct udevice *bus)
329 struct cadence_spi_plat *plat = dev_get_plat(bus);
332 plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
333 plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
335 plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
336 plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
337 plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
338 plat->trigger_address = dev_read_u32_default(bus,
339 "cdns,trigger-address",
341 /* Use DAC mode only when MMIO window is at least 8M wide */
342 if (plat->ahbsize >= SZ_8M)
343 plat->use_dac_mode = true;
345 /* All other paramters are embedded in the child node */
346 subnode = dev_read_first_subnode(bus);
347 if (!ofnode_valid(subnode)) {
348 printf("Error: subnode with SPI flash config missing!\n");
352 /* Use 500 KHz as a suitable default */
353 plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
356 /* Read other parameters from DT */
357 plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
358 plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
359 plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
361 plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
363 plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
364 plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
366 * Read delay should be an unsigned value but we use a signed integer
367 * so that negative values can indicate that the device tree did not
368 * specify any signed values and we need to perform the calibration
369 * sequence to find it out.
371 plat->read_delay = ofnode_read_s32_default(subnode, "cdns,read-delay",
374 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
375 __func__, plat->regbase, plat->ahbbase, plat->max_hz,
381 static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
382 .exec_op = cadence_spi_mem_exec_op,
383 .supports_op = cadence_spi_mem_supports_op,
386 static const struct dm_spi_ops cadence_spi_ops = {
387 .set_speed = cadence_spi_set_speed,
388 .set_mode = cadence_spi_set_mode,
389 .mem_ops = &cadence_spi_mem_ops,
391 * cs_info is not needed, since we require all chip selects to be
392 * in the device tree explicitly
396 static const struct udevice_id cadence_spi_ids[] = {
397 { .compatible = "cdns,qspi-nor" },
398 { .compatible = "ti,am654-ospi" },
402 U_BOOT_DRIVER(cadence_spi) = {
403 .name = "cadence_spi",
405 .of_match = cadence_spi_ids,
406 .ops = &cadence_spi_ops,
407 .of_to_plat = cadence_spi_of_to_plat,
408 .plat_auto = sizeof(struct cadence_spi_plat),
409 .priv_auto = sizeof(struct cadence_spi_priv),
410 .probe = cadence_spi_probe,
411 .remove = cadence_spi_remove,
412 .flags = DM_FLAG_OS_PREPARE,