1 // SPDX-License-Identifier: GPL-2.0+
4 * Altera Corporation <www.altera.com>
15 #include <linux/errno.h>
16 #include <linux/sizes.h>
17 #include "cadence_qspi.h"
19 #define CQSPI_STIG_READ 0
20 #define CQSPI_STIG_WRITE 1
24 static int cadence_spi_write_speed(struct udevice *bus, uint hz)
26 struct cadence_spi_platdata *plat = bus->platdata;
27 struct cadence_spi_priv *priv = dev_get_priv(bus);
29 cadence_qspi_apb_config_baudrate_div(priv->regbase,
30 plat->ref_clk_hz, hz);
32 /* Reconfigure delay timing if speed is changed. */
33 cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
34 plat->tshsl_ns, plat->tsd2d_ns,
35 plat->tchsh_ns, plat->tslch_ns);
40 static int cadence_spi_read_id(void *reg_base, u8 len, u8 *idcode)
42 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
45 SPI_MEM_OP_DATA_IN(len, idcode, 1));
47 return cadence_qspi_apb_command_read(reg_base, &op);
50 /* Calibration sequence to determine the read data capture delay register */
51 static int spi_calibration(struct udevice *bus, uint hz)
53 struct cadence_spi_priv *priv = dev_get_priv(bus);
54 void *base = priv->regbase;
55 unsigned int idcode = 0, temp = 0;
56 int err = 0, i, range_lo = -1, range_hi = -1;
58 /* start with slowest clock (1 MHz) */
59 cadence_spi_write_speed(bus, 1000000);
61 /* configure the read data capture delay register to 0 */
62 cadence_qspi_apb_readdata_capture(base, 1, 0);
65 cadence_qspi_apb_controller_enable(base);
67 /* read the ID which will be our golden value */
68 err = cadence_spi_read_id(base, 3, (u8 *)&idcode);
70 puts("SF: Calibration failed (read)\n");
74 /* use back the intended clock and find low range */
75 cadence_spi_write_speed(bus, hz);
76 for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
78 cadence_qspi_apb_controller_disable(base);
80 /* reconfigure the read data capture delay register */
81 cadence_qspi_apb_readdata_capture(base, 1, i);
83 /* Enable back QSPI */
84 cadence_qspi_apb_controller_enable(base);
86 /* issue a RDID to get the ID value */
87 err = cadence_spi_read_id(base, 3, (u8 *)&temp);
89 puts("SF: Calibration failed (read)\n");
93 /* search for range lo */
94 if (range_lo == -1 && temp == idcode) {
99 /* search for range hi */
100 if (range_lo != -1 && temp != idcode) {
107 if (range_lo == -1) {
108 puts("SF: Calibration failed (low range)\n");
112 /* Disable QSPI for subsequent initialization */
113 cadence_qspi_apb_controller_disable(base);
115 /* configure the final value for read data capture delay register */
116 cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
117 debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
118 (range_hi + range_lo) / 2, range_lo, range_hi);
120 /* just to ensure we do once only when speed or chip select change */
121 priv->qspi_calibrated_hz = hz;
122 priv->qspi_calibrated_cs = spi_chip_select(bus);
127 static int cadence_spi_set_speed(struct udevice *bus, uint hz)
129 struct cadence_spi_platdata *plat = bus->platdata;
130 struct cadence_spi_priv *priv = dev_get_priv(bus);
133 if (hz > plat->max_hz)
137 cadence_qspi_apb_controller_disable(priv->regbase);
140 * Calibration required for different current SCLK speed, requested
141 * SCLK speed or chip select
143 if (priv->previous_hz != hz ||
144 priv->qspi_calibrated_hz != hz ||
145 priv->qspi_calibrated_cs != spi_chip_select(bus)) {
146 err = spi_calibration(bus, hz);
150 /* prevent calibration run when same as previous request */
151 priv->previous_hz = hz;
155 cadence_qspi_apb_controller_enable(priv->regbase);
157 debug("%s: speed=%d\n", __func__, hz);
162 static int cadence_spi_probe(struct udevice *bus)
164 struct cadence_spi_platdata *plat = bus->platdata;
165 struct cadence_spi_priv *priv = dev_get_priv(bus);
168 priv->regbase = plat->regbase;
169 priv->ahbbase = plat->ahbbase;
171 ret = reset_get_bulk(bus, &priv->resets);
173 dev_warn(bus, "Can't get reset: %d\n", ret);
175 reset_deassert_bulk(&priv->resets);
177 if (!priv->qspi_is_init) {
178 cadence_qspi_apb_controller_init(plat);
179 priv->qspi_is_init = 1;
185 static int cadence_spi_remove(struct udevice *dev)
187 struct cadence_spi_priv *priv = dev_get_priv(dev);
189 return reset_release_bulk(&priv->resets);
192 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
194 struct cadence_spi_platdata *plat = bus->platdata;
195 struct cadence_spi_priv *priv = dev_get_priv(bus);
198 cadence_qspi_apb_controller_disable(priv->regbase);
201 cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
203 /* Enable Direct Access Controller */
204 if (plat->use_dac_mode)
205 cadence_qspi_apb_dac_mode_enable(priv->regbase);
208 cadence_qspi_apb_controller_enable(priv->regbase);
213 static int cadence_spi_mem_exec_op(struct spi_slave *spi,
214 const struct spi_mem_op *op)
216 struct udevice *bus = spi->dev->parent;
217 struct cadence_spi_platdata *plat = bus->platdata;
218 struct cadence_spi_priv *priv = dev_get_priv(bus);
219 void *base = priv->regbase;
223 /* Set Chip select */
224 cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
225 plat->is_decoded_cs);
227 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
228 if (!op->addr.nbytes)
229 mode = CQSPI_STIG_READ;
233 if (!op->addr.nbytes || !op->data.buf.out)
234 mode = CQSPI_STIG_WRITE;
240 case CQSPI_STIG_READ:
241 err = cadence_qspi_apb_command_read(base, op);
243 case CQSPI_STIG_WRITE:
244 err = cadence_qspi_apb_command_write(base, op);
247 err = cadence_qspi_apb_read_setup(plat, op);
249 err = cadence_qspi_apb_read_execute(plat, op);
252 err = cadence_qspi_apb_write_setup(plat, op);
254 err = cadence_qspi_apb_write_execute(plat, op);
264 static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
266 struct cadence_spi_platdata *plat = bus->platdata;
271 plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
272 plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
274 plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
275 plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
276 plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
277 plat->trigger_address = dev_read_u32_default(bus,
278 "cdns,trigger-address",
280 /* Use DAC mode only when MMIO window is at least 8M wide */
281 if (plat->ahbsize >= SZ_8M)
282 plat->use_dac_mode = true;
284 /* All other paramters are embedded in the child node */
285 subnode = dev_read_first_subnode(bus);
286 if (!ofnode_valid(subnode)) {
287 printf("Error: subnode with SPI flash config missing!\n");
291 /* Use 500 KHz as a suitable default */
292 plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
295 /* Read other parameters from DT */
296 plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
297 plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
298 plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
300 plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
302 plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
303 plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
305 ret = clk_get_by_index(bus, 0, &clk);
307 #ifdef CONFIG_CQSPI_REF_CLK
308 plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
313 plat->ref_clk_hz = clk_get_rate(&clk);
315 if (IS_ERR_VALUE(plat->ref_clk_hz))
316 return plat->ref_clk_hz;
319 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
320 __func__, plat->regbase, plat->ahbbase, plat->max_hz,
326 static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
327 .exec_op = cadence_spi_mem_exec_op,
330 static const struct dm_spi_ops cadence_spi_ops = {
331 .set_speed = cadence_spi_set_speed,
332 .set_mode = cadence_spi_set_mode,
333 .mem_ops = &cadence_spi_mem_ops,
335 * cs_info is not needed, since we require all chip selects to be
336 * in the device tree explicitly
340 static const struct udevice_id cadence_spi_ids[] = {
341 { .compatible = "cdns,qspi-nor" },
345 U_BOOT_DRIVER(cadence_spi) = {
346 .name = "cadence_spi",
348 .of_match = cadence_spi_ids,
349 .ops = &cadence_spi_ops,
350 .ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
351 .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
352 .priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
353 .probe = cadence_spi_probe,
354 .remove = cadence_spi_remove,
355 .flags = DM_FLAG_OS_PREPARE,