drivers/spi/cadence_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012
   4  * Altera Corporation <www.altera.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <fdtdec.h>
  11 #include <malloc.h>
  12 #include <reset.h>
  13 #include <spi.h>
  14 #include <spi-mem.h>
  15 #include <linux/errno.h>
  16 #include <linux/sizes.h>
  17 #include "cadence_qspi.h"
  18
  19 #define CQSPI_STIG_READ                 0
  20 #define CQSPI_STIG_WRITE                1
  21 #define CQSPI_READ                      2
  22 #define CQSPI_WRITE                     3
  23
  24 static int cadence_spi_write_speed(struct udevice *bus, uint hz)
  25 {
  26         struct cadence_spi_platdata *plat = bus->platdata;
  27         struct cadence_spi_priv *priv = dev_get_priv(bus);
  28
  29         cadence_qspi_apb_config_baudrate_div(priv->regbase,
  30                                              plat->ref_clk_hz, hz);
  31
  32         /* Reconfigure delay timing if speed is changed. */
  33         cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
  34                                plat->tshsl_ns, plat->tsd2d_ns,
  35                                plat->tchsh_ns, plat->tslch_ns);
  36
  37         return 0;
  38 }
  39
  40 static int cadence_spi_read_id(void *reg_base, u8 len, u8 *idcode)
  41 {
  42         struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
  43                                           SPI_MEM_OP_NO_ADDR,
  44                                           SPI_MEM_OP_NO_DUMMY,
  45                                           SPI_MEM_OP_DATA_IN(len, idcode, 1));
  46
  47         return cadence_qspi_apb_command_read(reg_base, &op);
  48 }
  49
  50 /* Calibration sequence to determine the read data capture delay register */
  51 static int spi_calibration(struct udevice *bus, uint hz)
  52 {
  53         struct cadence_spi_priv *priv = dev_get_priv(bus);
  54         void *base = priv->regbase;
  55         unsigned int idcode = 0, temp = 0;
  56         int err = 0, i, range_lo = -1, range_hi = -1;
  57
  58         /* start with slowest clock (1 MHz) */
  59         cadence_spi_write_speed(bus, 1000000);
  60
  61         /* configure the read data capture delay register to 0 */
  62         cadence_qspi_apb_readdata_capture(base, 1, 0);
  63
  64         /* Enable QSPI */
  65         cadence_qspi_apb_controller_enable(base);
  66
  67         /* read the ID which will be our golden value */
  68         err = cadence_spi_read_id(base, 3, (u8 *)&idcode);
  69         if (err) {
  70                 puts("SF: Calibration failed (read)\n");
  71                 return err;
  72         }
  73
  74         /* use back the intended clock and find low range */
  75         cadence_spi_write_speed(bus, hz);
  76         for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
  77                 /* Disable QSPI */
  78                 cadence_qspi_apb_controller_disable(base);
  79
  80                 /* reconfigure the read data capture delay register */
  81                 cadence_qspi_apb_readdata_capture(base, 1, i);
  82
  83                 /* Enable back QSPI */
  84                 cadence_qspi_apb_controller_enable(base);
  85
  86                 /* issue a RDID to get the ID value */
  87                 err = cadence_spi_read_id(base, 3, (u8 *)&temp);
  88                 if (err) {
  89                         puts("SF: Calibration failed (read)\n");
  90                         return err;
  91                 }
  92
  93                 /* search for range lo */
  94                 if (range_lo == -1 && temp == idcode) {
  95                         range_lo = i;
  96                         continue;
  97                 }
  98
  99                 /* search for range hi */
 100                 if (range_lo != -1 && temp != idcode) {
 101                         range_hi = i - 1;
 102                         break;
 103                 }
 104                 range_hi = i;
 105         }
 106
 107         if (range_lo == -1) {
 108                 puts("SF: Calibration failed (low range)\n");
 109                 return err;
 110         }
 111
 112         /* Disable QSPI for subsequent initialization */
 113         cadence_qspi_apb_controller_disable(base);
 114
 115         /* configure the final value for read data capture delay register */
 116         cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
 117         debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
 118               (range_hi + range_lo) / 2, range_lo, range_hi);
 119
 120         /* just to ensure we do once only when speed or chip select change */
 121         priv->qspi_calibrated_hz = hz;
 122         priv->qspi_calibrated_cs = spi_chip_select(bus);
 123
 124         return 0;
 125 }
 126
 127 static int cadence_spi_set_speed(struct udevice *bus, uint hz)
 128 {
 129         struct cadence_spi_platdata *plat = bus->platdata;
 130         struct cadence_spi_priv *priv = dev_get_priv(bus);
 131         int err;
 132
 133         if (hz > plat->max_hz)
 134                 hz = plat->max_hz;
 135
 136         /* Disable QSPI */
 137         cadence_qspi_apb_controller_disable(priv->regbase);
 138
 139         /*
 140          * Calibration required for different current SCLK speed, requested
 141          * SCLK speed or chip select
 142          */
 143         if (priv->previous_hz != hz ||
 144             priv->qspi_calibrated_hz != hz ||
 145             priv->qspi_calibrated_cs != spi_chip_select(bus)) {
 146                 err = spi_calibration(bus, hz);
 147                 if (err)
 148                         return err;
 149
 150                 /* prevent calibration run when same as previous request */
 151                 priv->previous_hz = hz;
 152         }
 153
 154         /* Enable QSPI */
 155         cadence_qspi_apb_controller_enable(priv->regbase);
 156
 157         debug("%s: speed=%d\n", __func__, hz);
 158
 159         return 0;
 160 }
 161
 162 static int cadence_spi_probe(struct udevice *bus)
 163 {
 164         struct cadence_spi_platdata *plat = bus->platdata;
 165         struct cadence_spi_priv *priv = dev_get_priv(bus);
 166         int ret;
 167
 168         priv->regbase = plat->regbase;
 169         priv->ahbbase = plat->ahbbase;
 170
 171         ret = reset_get_bulk(bus, &priv->resets);
 172         if (ret)
 173                 dev_warn(bus, "Can't get reset: %d\n", ret);
 174         else
 175                 reset_deassert_bulk(&priv->resets);
 176
 177         if (!priv->qspi_is_init) {
 178                 cadence_qspi_apb_controller_init(plat);
 179                 priv->qspi_is_init = 1;
 180         }
 181
 182         return 0;
 183 }
 184
 185 static int cadence_spi_remove(struct udevice *dev)
 186 {
 187         struct cadence_spi_priv *priv = dev_get_priv(dev);
 188
 189         return reset_release_bulk(&priv->resets);
 190 }
 191
 192 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
 193 {
 194         struct cadence_spi_platdata *plat = bus->platdata;
 195         struct cadence_spi_priv *priv = dev_get_priv(bus);
 196
 197         /* Disable QSPI */
 198         cadence_qspi_apb_controller_disable(priv->regbase);
 199
 200         /* Set SPI mode */
 201         cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
 202
 203         /* Enable Direct Access Controller */
 204         if (plat->use_dac_mode)
 205                 cadence_qspi_apb_dac_mode_enable(priv->regbase);
 206
 207         /* Enable QSPI */
 208         cadence_qspi_apb_controller_enable(priv->regbase);
 209
 210         return 0;
 211 }
 212
 213 static int cadence_spi_mem_exec_op(struct spi_slave *spi,
 214                                    const struct spi_mem_op *op)
 215 {
 216         struct udevice *bus = spi->dev->parent;
 217         struct cadence_spi_platdata *plat = bus->platdata;
 218         struct cadence_spi_priv *priv = dev_get_priv(bus);
 219         void *base = priv->regbase;
 220         int err = 0;
 221         u32 mode;
 222
 223         /* Set Chip select */
 224         cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
 225                                     plat->is_decoded_cs);
 226
 227         if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
 228                 if (!op->addr.nbytes)
 229                         mode = CQSPI_STIG_READ;
 230                 else
 231                         mode = CQSPI_READ;
 232         } else {
 233                 if (!op->addr.nbytes || !op->data.buf.out)
 234                         mode = CQSPI_STIG_WRITE;
 235                 else
 236                         mode = CQSPI_WRITE;
 237         }
 238
 239         switch (mode) {
 240         case CQSPI_STIG_READ:
 241                 err = cadence_qspi_apb_command_read(base, op);
 242                 break;
 243         case CQSPI_STIG_WRITE:
 244                 err = cadence_qspi_apb_command_write(base, op);
 245                 break;
 246         case CQSPI_READ:
 247                 err = cadence_qspi_apb_read_setup(plat, op);
 248                 if (!err)
 249                         err = cadence_qspi_apb_read_execute(plat, op);
 250                 break;
 251         case CQSPI_WRITE:
 252                 err = cadence_qspi_apb_write_setup(plat, op);
 253                 if (!err)
 254                         err = cadence_qspi_apb_write_execute(plat, op);
 255                 break;
 256         default:
 257                 err = -1;
 258                 break;
 259         }
 260
 261         return err;
 262 }
 263
 264 static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
 265 {
 266         struct cadence_spi_platdata *plat = bus->platdata;
 267         ofnode subnode;
 268         struct clk clk;
 269         int ret;
 270
 271         plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
 272         plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
 273                         &plat->ahbsize);
 274         plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
 275         plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
 276         plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
 277         plat->trigger_address = dev_read_u32_default(bus,
 278                                                      "cdns,trigger-address",
 279                                                      0);
 280         /* Use DAC mode only when MMIO window is at least 8M wide */
 281         if (plat->ahbsize >= SZ_8M)
 282                 plat->use_dac_mode = true;
 283
 284         /* All other paramters are embedded in the child node */
 285         subnode = dev_read_first_subnode(bus);
 286         if (!ofnode_valid(subnode)) {
 287                 printf("Error: subnode with SPI flash config missing!\n");
 288                 return -ENODEV;
 289         }
 290
 291         /* Use 500 KHz as a suitable default */
 292         plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
 293                                                500000);
 294
 295         /* Read other parameters from DT */
 296         plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
 297         plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
 298         plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
 299                                                  200);
 300         plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
 301                                                  255);
 302         plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
 303         plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
 304
 305         ret = clk_get_by_index(bus, 0, &clk);
 306         if (ret) {
 307 #ifdef CONFIG_CQSPI_REF_CLK
 308                 plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
 309 #else
 310                 return ret;
 311 #endif
 312         } else {
 313                 plat->ref_clk_hz = clk_get_rate(&clk);
 314                 clk_free(&clk);
 315                 if (IS_ERR_VALUE(plat->ref_clk_hz))
 316                         return plat->ref_clk_hz;
 317         }
 318
 319         debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
 320               __func__, plat->regbase, plat->ahbbase, plat->max_hz,
 321               plat->page_size);
 322
 323         return 0;
 324 }
 325
 326 static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
 327         .exec_op = cadence_spi_mem_exec_op,
 328 };
 329
 330 static const struct dm_spi_ops cadence_spi_ops = {
 331         .set_speed      = cadence_spi_set_speed,
 332         .set_mode       = cadence_spi_set_mode,
 333         .mem_ops        = &cadence_spi_mem_ops,
 334         /*
 335          * cs_info is not needed, since we require all chip selects to be
 336          * in the device tree explicitly
 337          */
 338 };
 339
 340 static const struct udevice_id cadence_spi_ids[] = {
 341         { .compatible = "cdns,qspi-nor" },
 342         { }
 343 };
 344
 345 U_BOOT_DRIVER(cadence_spi) = {
 346         .name = "cadence_spi",
 347         .id = UCLASS_SPI,
 348         .of_match = cadence_spi_ids,
 349         .ops = &cadence_spi_ops,
 350         .ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
 351         .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
 352         .priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
 353         .probe = cadence_spi_probe,
 354         .remove = cadence_spi_remove,
 355         .flags = DM_FLAG_OS_PREPARE,
 356 };