drivers/spi/cadence_ospi_versal.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2018 Xilinx
   4  *
   5  * Cadence QSPI controller DMA operations
   6  */
   7
   8 #include <clk.h>
   9 #include <common.h>
  10 #include <memalign.h>
  11 #include <wait_bit.h>
  12 #include <asm/io.h>
  13 #include <asm/gpio.h>
  14 #include <asm/cache.h>
  15 #include <cpu_func.h>
  16 #include <zynqmp_firmware.h>
  17 #include <asm/arch/hardware.h>
  18 #include "cadence_qspi.h"
  19 #include <dt-bindings/power/xlnx-versal-power.h>
  20
  21 #define CMD_4BYTE_READ  0x13
  22 #define CMD_4BYTE_FAST_READ  0x0C
  23
  24 int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
  25                               const struct spi_mem_op *op)
  26 {
  27         u32 reg, ret, rx_rem, n_rx, bytes_to_dma, data;
  28         u8 opcode, addr_bytes, *rxbuf, dummy_cycles;
  29
  30         n_rx = op->data.nbytes;
  31         rxbuf = op->data.buf.in;
  32         rx_rem = n_rx % 4;
  33         bytes_to_dma = n_rx - rx_rem;
  34
  35         if (bytes_to_dma) {
  36                 cadence_qspi_apb_enable_linear_mode(false);
  37                 reg = readl(priv->regbase + CQSPI_REG_CONFIG);
  38                 reg |= CQSPI_REG_CONFIG_ENBL_DMA;
  39                 writel(reg, priv->regbase + CQSPI_REG_CONFIG);
  40
  41                 writel(bytes_to_dma, priv->regbase + CQSPI_REG_INDIRECTRDBYTES);
  42
  43                 writel(CQSPI_DFLT_INDIR_TRIG_ADDR_RANGE,
  44                        priv->regbase + CQSPI_REG_INDIR_TRIG_ADDR_RANGE);
  45                 writel(CQSPI_DFLT_DMA_PERIPH_CFG,
  46                        priv->regbase + CQSPI_REG_DMA_PERIPH_CFG);
  47                 writel((unsigned long)rxbuf, priv->regbase +
  48                        CQSPI_DMA_DST_ADDR_REG);
  49                 writel(priv->trigger_address, priv->regbase +
  50                        CQSPI_DMA_SRC_RD_ADDR_REG);
  51                 writel(bytes_to_dma, priv->regbase +
  52                        CQSPI_DMA_DST_SIZE_REG);
  53                 flush_dcache_range((unsigned long)rxbuf,
  54                                    (unsigned long)rxbuf + bytes_to_dma);
  55                 writel(CQSPI_DFLT_DST_CTRL_REG_VAL,
  56                        priv->regbase + CQSPI_DMA_DST_CTRL_REG);
  57
  58                 /* Start the indirect read transfer */
  59                 writel(CQSPI_REG_INDIRECTRD_START, priv->regbase +
  60                        CQSPI_REG_INDIRECTRD);
  61                 /* Wait for dma to complete transfer */
  62                 ret = cadence_qspi_apb_wait_for_dma_cmplt(priv);
  63                 if (ret)
  64                         return ret;
  65
  66                 /* Clear indirect completion status */
  67                 writel(CQSPI_REG_INDIRECTRD_DONE, priv->regbase +
  68                        CQSPI_REG_INDIRECTRD);
  69                 rxbuf += bytes_to_dma;
  70         }
  71
  72         if (rx_rem) {
  73                 reg = readl(priv->regbase + CQSPI_REG_CONFIG);
  74                 reg &= ~CQSPI_REG_CONFIG_ENBL_DMA;
  75                 writel(reg, priv->regbase + CQSPI_REG_CONFIG);
  76
  77                 reg = readl(priv->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
  78                 reg += bytes_to_dma;
  79                 writel(reg, priv->regbase + CQSPI_REG_CMDADDRESS);
  80
  81                 addr_bytes = readl(priv->regbase + CQSPI_REG_SIZE) &
  82                                    CQSPI_REG_SIZE_ADDRESS_MASK;
  83
  84                 opcode = CMD_4BYTE_FAST_READ;
  85                 dummy_cycles = 8;
  86                 writel((dummy_cycles << CQSPI_REG_RD_INSTR_DUMMY_LSB) | opcode,
  87                        priv->regbase + CQSPI_REG_RD_INSTR);
  88
  89                 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
  90                 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
  91                 reg |= (addr_bytes & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) <<
  92                         CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
  93                 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
  94                 dummy_cycles = (readl(priv->regbase + CQSPI_REG_RD_INSTR) >>
  95                                 CQSPI_REG_RD_INSTR_DUMMY_LSB) &
  96                                 CQSPI_REG_RD_INSTR_DUMMY_MASK;
  97                 reg |= (dummy_cycles & CQSPI_REG_CMDCTRL_DUMMY_MASK) <<
  98                         CQSPI_REG_CMDCTRL_DUMMY_LSB;
  99                 reg |= (((rx_rem - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) <<
 100                         CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 101                 ret = cadence_qspi_apb_exec_flash_cmd(priv->regbase, reg);
 102                 if (ret)
 103                         return ret;
 104
 105                 data = readl(priv->regbase + CQSPI_REG_CMDREADDATALOWER);
 106                 memcpy(rxbuf, &data, rx_rem);
 107         }
 108
 109         return 0;
 110 }
 111
 112 int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv)
 113 {
 114         u32 timeout = CQSPI_DMA_TIMEOUT;
 115
 116         while (!(readl(priv->regbase + CQSPI_DMA_DST_I_STS_REG) &
 117                  CQSPI_DMA_DST_I_STS_DONE) && timeout--)
 118                 udelay(1);
 119
 120         if (!timeout) {
 121                 printf("DMA timeout\n");
 122                 return -ETIMEDOUT;
 123         }
 124
 125         writel(readl(priv->regbase + CQSPI_DMA_DST_I_STS_REG),
 126                priv->regbase + CQSPI_DMA_DST_I_STS_REG);
 127         return 0;
 128 }
 129
 130 #if defined(CONFIG_DM_GPIO)
 131 int cadence_qspi_versal_flash_reset(struct udevice *dev)
 132 {
 133 #ifndef CONFIG_ARCH_VERSAL_NET
 134         struct gpio_desc gpio;
 135         u32 reset_gpio;
 136         int ret;
 137
 138         /* request gpio and set direction as output set to 1 */
 139         ret = gpio_request_by_name(dev, "reset-gpios", 0, &gpio,
 140                                    GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 141         if (ret) {
 142                 printf("%s: unable to reset ospi flash device", __func__);
 143                 return ret;
 144         }
 145
 146         reset_gpio = PMIO_NODE_ID_BASE + gpio.offset;
 147
 148         /* Request for pin */
 149         xilinx_pm_request(PM_PINCTRL_REQUEST, reset_gpio, 0, 0, 0, NULL);
 150
 151         /* Enable hysteresis in cmos receiver */
 152         xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio,
 153                           PM_PINCTRL_CONFIG_SCHMITT_CMOS,
 154                           PM_PINCTRL_INPUT_TYPE_SCHMITT, 0, NULL);
 155
 156         /* Disable Tri-state */
 157         xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio,
 158                           PM_PINCTRL_CONFIG_TRI_STATE,
 159                           PM_PINCTRL_TRI_STATE_DISABLE, 0, NULL);
 160         udelay(1);
 161
 162         /* Set value 0 to pin */
 163         dm_gpio_set_value(&gpio, 0);
 164         udelay(1);
 165
 166         /* Set value 1 to pin */
 167         dm_gpio_set_value(&gpio, 1);
 168         udelay(1);
 169 #endif
 170         return 0;
 171 }
 172 #else
 173 int cadence_qspi_versal_flash_reset(struct udevice *dev)
 174 {
 175         /* CRP WPROT */
 176         writel(0, WPROT_CRP);
 177         /* GPIO Reset */
 178         writel(0, RST_GPIO);
 179
 180         /* disable IOU write protection */
 181         writel(0, WPROT_LPD_MIO);
 182
 183         /* set direction as output */
 184         writel((readl(BOOT_MODE_DIR) | BIT(FLASH_RESET_GPIO)),
 185                BOOT_MODE_DIR);
 186
 187         /* Data output enable */
 188         writel((readl(BOOT_MODE_OUT) | BIT(FLASH_RESET_GPIO)),
 189                BOOT_MODE_OUT);
 190
 191         /* IOU SLCR write enable */
 192         writel(0, WPROT_PMC_MIO);
 193
 194         /* set MIO as GPIO */
 195         writel(0x60, MIO_PIN_12);
 196
 197         /* Set value 1 to pin */
 198         writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
 199         udelay(10);
 200
 201         /* Disable Tri-state */
 202         writel((readl(BANK0_TRI) & ~BIT(FLASH_RESET_GPIO)), BANK0_TRI);
 203         udelay(1);
 204
 205         /* Set value 0 to pin */
 206         writel((readl(BANK0_OUTPUT) & ~BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
 207         udelay(10);
 208
 209         /* Set value 1 to pin */
 210         writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
 211         udelay(10);
 212
 213         return 0;
 214 }
 215 #endif
 216
 217 void cadence_qspi_apb_enable_linear_mode(bool enable)
 218 {
 219         if (CONFIG_IS_ENABLED(ZYNQMP_FIRMWARE)) {
 220                 if (enable)
 221                         /* ahb read mode */
 222                         xilinx_pm_request(PM_IOCTL, PM_DEV_OSPI,
 223                                           IOCTL_OSPI_MUX_SELECT,
 224                                           PM_OSPI_MUX_SEL_LINEAR, 0, NULL);
 225                 else
 226                         /* DMA mode */
 227                         xilinx_pm_request(PM_IOCTL, PM_DEV_OSPI,
 228                                           IOCTL_OSPI_MUX_SELECT,
 229                                           PM_OSPI_MUX_SEL_DMA, 0, NULL);
 230         } else {
 231                 if (enable)
 232                         writel(readl(VERSAL_AXI_MUX_SEL) |
 233                                VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL);
 234                 else
 235                         writel(readl(VERSAL_AXI_MUX_SEL) &
 236                                ~VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL);
 237         }
 238 }