2 * Driver for Blackfin On-Chip SPI device
4 * Copyright (c) 2005-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
15 #include <asm/blackfin.h>
16 #include <asm/portmux.h>
17 #include <asm/mach-common/bits/spi.h>
19 struct bfin_spi_slave {
20 struct spi_slave slave;
25 #define MAKE_SPI_FUNC(mmr, off) \
26 static inline void write_##mmr(struct bfin_spi_slave *bss, u16 val) { bfin_write16(bss->mmr_base + off, val); } \
27 static inline u16 read_##mmr(struct bfin_spi_slave *bss) { return bfin_read16(bss->mmr_base + off); }
28 MAKE_SPI_FUNC(SPI_CTL, 0x00)
29 MAKE_SPI_FUNC(SPI_FLG, 0x04)
30 MAKE_SPI_FUNC(SPI_STAT, 0x08)
31 MAKE_SPI_FUNC(SPI_TDBR, 0x0c)
32 MAKE_SPI_FUNC(SPI_RDBR, 0x10)
33 MAKE_SPI_FUNC(SPI_BAUD, 0x14)
35 #define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
38 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
40 #if defined(__ADSPBF538__) || defined(__ADSPBF539__)
41 /* The SPI1/SPI2 buses are weird ... only 1 CS */
42 if (bus > 0 && cs != 1)
45 return (cs >= 1 && cs <= 7);
49 void spi_cs_activate(struct spi_slave *slave)
51 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
54 ~((!bss->flg << 8) << slave->cs)) |
57 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
61 void spi_cs_deactivate(struct spi_slave *slave)
63 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
66 /* make sure we force the cs to deassert rather than let the
67 * pin float back up. otherwise, exact timings may not be
68 * met some of the time leading to random behavior (ugh).
70 flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
71 write_SPI_FLG(bss, flg);
73 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
75 flg &= ~(1 << slave->cs);
76 write_SPI_FLG(bss, flg);
78 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
86 # define SPI0_CTL SPI_CTL
90 [n] = { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
91 static unsigned short pins[][5] = {
103 #define SPI_CS_PINS(n) \
105 P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
106 P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
109 static const unsigned short cs_pins[][7] = {
121 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
122 unsigned int max_hz, unsigned int mode)
124 struct bfin_spi_slave *bss;
129 if (!spi_cs_is_valid(bus, cs))
132 if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) {
133 debug("%s: invalid bus %u\n", __func__, bus);
138 case 0: mmr_base = SPI0_CTL; break;
141 case 1: mmr_base = SPI1_CTL; break;
144 case 2: mmr_base = SPI2_CTL; break;
146 default: return NULL;
150 baud = sclk / (2 * max_hz);
151 /* baud should be rounded up */
152 if (sclk % (2 * max_hz))
156 else if (baud > (u16)-1)
159 bss = malloc(sizeof(*bss));
163 bss->slave.bus = bus;
165 bss->mmr_base = (void *)mmr_base;
166 bss->ctl = SPE | MSTR | TDBR_CORE;
167 if (mode & SPI_CPHA) bss->ctl |= CPHA;
168 if (mode & SPI_CPOL) bss->ctl |= CPOL;
169 if (mode & SPI_LSB_FIRST) bss->ctl |= LSBF;
171 bss->flg = mode & SPI_CS_HIGH ? 1 : 0;
173 debug("%s: bus:%i cs:%i mmr:%x ctl:%x baud:%i flg:%i\n", __func__,
174 bus, cs, mmr_base, bss->ctl, baud, bss->flg);
179 void spi_free_slave(struct spi_slave *slave)
181 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
185 int spi_claim_bus(struct spi_slave *slave)
187 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
189 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
191 pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
192 peripheral_request_list(pins[slave->bus], "bfin-spi");
194 write_SPI_CTL(bss, bss->ctl);
195 write_SPI_BAUD(bss, bss->baud);
201 void spi_release_bus(struct spi_slave *slave)
203 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
205 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
207 peripheral_free_list(pins[slave->bus]);
209 write_SPI_CTL(bss, 0);
213 #ifndef CONFIG_BFIN_SPI_IDLE_VAL
214 # define CONFIG_BFIN_SPI_IDLE_VAL 0xff
217 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
218 void *din, unsigned long flags)
220 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
223 uint bytes = bitlen / 8;
226 debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
227 slave->bus, slave->cs, bitlen, bytes, flags);
232 /* we can only do 8 bit transfers */
234 flags |= SPI_XFER_END;
238 if (flags & SPI_XFER_BEGIN)
239 spi_cs_activate(slave);
241 /* todo: take advantage of hardware fifos and setup RX dma */
243 u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
244 debug("%s: tx:%x ", __func__, value);
245 write_SPI_TDBR(bss, value);
247 while ((read_SPI_STAT(bss) & TXS))
252 while (!(read_SPI_STAT(bss) & SPIF))
257 while (!(read_SPI_STAT(bss) & RXS))
262 value = read_SPI_RDBR(bss);
265 debug("rx:%x\n", value);
269 if (flags & SPI_XFER_END)
270 spi_cs_deactivate(slave);