2 * Driver for Blackfin On-Chip SPI device
4 * Copyright (c) 2005-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
15 #include <asm/blackfin.h>
17 #include <asm/portmux.h>
18 #include <asm/mach-common/bits/spi.h>
20 struct bfin_spi_slave {
21 struct spi_slave slave;
26 #define MAKE_SPI_FUNC(mmr, off) \
27 static inline void write_##mmr(struct bfin_spi_slave *bss, u16 val) { bfin_write16(bss->mmr_base + off, val); } \
28 static inline u16 read_##mmr(struct bfin_spi_slave *bss) { return bfin_read16(bss->mmr_base + off); }
29 MAKE_SPI_FUNC(SPI_CTL, 0x00)
30 MAKE_SPI_FUNC(SPI_FLG, 0x04)
31 MAKE_SPI_FUNC(SPI_STAT, 0x08)
32 MAKE_SPI_FUNC(SPI_TDBR, 0x0c)
33 MAKE_SPI_FUNC(SPI_RDBR, 0x10)
34 MAKE_SPI_FUNC(SPI_BAUD, 0x14)
36 #define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
38 #define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
39 #ifdef CONFIG_BFIN_SPI_GPIO_CS
40 # define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
42 # define is_gpio_cs(cs) 0
45 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
48 return gpio_is_valid(gpio_cs(cs));
50 return (cs >= 1 && cs <= MAX_CTRL_CS);
53 void spi_cs_activate(struct spi_slave *slave)
55 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
57 if (is_gpio_cs(slave->cs)) {
58 unsigned int cs = gpio_cs(slave->cs);
59 gpio_set_value(cs, bss->flg);
60 debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
64 ~((!bss->flg << 8) << slave->cs)) |
66 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
72 void spi_cs_deactivate(struct spi_slave *slave)
74 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
76 if (is_gpio_cs(slave->cs)) {
77 unsigned int cs = gpio_cs(slave->cs);
78 gpio_set_value(cs, !bss->flg);
79 debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
83 /* make sure we force the cs to deassert rather than let the
84 * pin float back up. otherwise, exact timings may not be
85 * met some of the time leading to random behavior (ugh).
87 flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
88 write_SPI_FLG(bss, flg);
90 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
92 flg &= ~(1 << slave->cs);
93 write_SPI_FLG(bss, flg);
94 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
105 # define SPI0_CTL SPI_CTL
108 #define SPI_PINS(n) \
109 [n] = { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
110 static unsigned short pins[][5] = {
122 #define SPI_CS_PINS(n) \
124 P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
125 P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
128 static const unsigned short cs_pins[][7] = {
140 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
141 unsigned int max_hz, unsigned int mode)
143 struct bfin_spi_slave *bss;
148 if (!spi_cs_is_valid(bus, cs))
151 if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) {
152 debug("%s: invalid bus %u\n", __func__, bus);
157 case 0: mmr_base = SPI0_CTL; break;
160 case 1: mmr_base = SPI1_CTL; break;
163 case 2: mmr_base = SPI2_CTL; break;
165 default: return NULL;
169 baud = sclk / (2 * max_hz);
170 /* baud should be rounded up */
171 if (sclk % (2 * max_hz))
175 else if (baud > (u16)-1)
178 bss = malloc(sizeof(*bss));
182 bss->slave.bus = bus;
184 bss->mmr_base = (void *)mmr_base;
185 bss->ctl = SPE | MSTR | TDBR_CORE;
186 if (mode & SPI_CPHA) bss->ctl |= CPHA;
187 if (mode & SPI_CPOL) bss->ctl |= CPOL;
188 if (mode & SPI_LSB_FIRST) bss->ctl |= LSBF;
190 bss->flg = mode & SPI_CS_HIGH ? 1 : 0;
192 debug("%s: bus:%i cs:%i mmr:%x ctl:%x baud:%i flg:%i\n", __func__,
193 bus, cs, mmr_base, bss->ctl, baud, bss->flg);
198 void spi_free_slave(struct spi_slave *slave)
200 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
204 int spi_claim_bus(struct spi_slave *slave)
206 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
208 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
210 if (is_gpio_cs(slave->cs)) {
211 unsigned int cs = gpio_cs(slave->cs);
212 gpio_request(cs, "bfin-spi");
213 gpio_direction_output(cs, !bss->flg);
214 pins[slave->bus][0] = P_DONTCARE;
216 pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
217 peripheral_request_list(pins[slave->bus], "bfin-spi");
219 write_SPI_CTL(bss, bss->ctl);
220 write_SPI_BAUD(bss, bss->baud);
226 void spi_release_bus(struct spi_slave *slave)
228 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
230 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
232 peripheral_free_list(pins[slave->bus]);
233 if (is_gpio_cs(slave->cs))
234 gpio_free(gpio_cs(slave->cs));
236 write_SPI_CTL(bss, 0);
240 #ifndef CONFIG_BFIN_SPI_IDLE_VAL
241 # define CONFIG_BFIN_SPI_IDLE_VAL 0xff
244 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
245 void *din, unsigned long flags)
247 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
250 uint bytes = bitlen / 8;
253 debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
254 slave->bus, slave->cs, bitlen, bytes, flags);
259 /* we can only do 8 bit transfers */
261 flags |= SPI_XFER_END;
265 if (flags & SPI_XFER_BEGIN)
266 spi_cs_activate(slave);
268 /* todo: take advantage of hardware fifos and setup RX dma */
270 u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
271 debug("%s: tx:%x ", __func__, value);
272 write_SPI_TDBR(bss, value);
274 while ((read_SPI_STAT(bss) & TXS))
279 while (!(read_SPI_STAT(bss) & SPIF))
284 while (!(read_SPI_STAT(bss) & RXS))
289 value = read_SPI_RDBR(bss);
292 debug("rx:%x\n", value);
296 if (flags & SPI_XFER_END)
297 spi_cs_deactivate(slave);