1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2018 Cisco Systems, Inc.
5 * Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
8 #include <asm/global_data.h>
15 #include <linux/bitops.h>
16 #include <linux/delay.h>
22 DECLARE_GLOBAL_DATA_PTR;
25 #define BITS_PER_WORD 8
31 /* hif_mspi register structure. */
32 struct bcmstb_hif_mspi_regs {
33 u32 spcr0_lsb; /* 0x000 */
34 u32 spcr0_msb; /* 0x004 */
35 u32 spcr1_lsb; /* 0x008 */
36 u32 spcr1_msb; /* 0x00c */
37 u32 newqp; /* 0x010 */
38 u32 endqp; /* 0x014 */
39 u32 spcr2; /* 0x018 */
40 u32 reserved0; /* 0x01c */
41 u32 mspi_status; /* 0x020 */
42 u32 cptqp; /* 0x024 */
43 u32 spcr3; /* 0x028 */
44 u32 revision; /* 0x02c */
45 u32 reserved1[4]; /* 0x030 */
46 u32 txram[NUM_TXRAM]; /* 0x040 */
47 u32 rxram[NUM_RXRAM]; /* 0x0c0 */
48 u32 cdram[NUM_CDRAM]; /* 0x140 */
49 u32 write_lock; /* 0x180 */
53 #define HIF_MSPI_SPCR2_CONT_AFTER_CMD_MASK 0x00000080
54 #define HIF_MSPI_SPCR2_SPE_MASK 0x00000040
55 #define HIF_MSPI_SPCR2_SPIFIE_MASK 0x00000020
56 #define HIF_MSPI_WRITE_LOCK_WRITE_LOCK_MASK 0x00000001
59 #define BSPI_MAST_N_BOOT_CTRL 0x008
61 /* bspi_raf is not used in this driver. */
63 /* hif_spi_intr2 offsets and masks. */
64 #define HIF_SPI_INTR2_CPU_CLEAR 0x08
65 #define HIF_SPI_INTR2_CPU_MASK_SET 0x10
66 #define HIF_SPI_INTR2_CPU_MASK_CLEAR 0x14
67 #define HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK 0x00000020
69 /* SPI transfer timeout in milliseconds. */
70 #define HIF_MSPI_WAIT 10
72 enum bcmstb_base_type {
80 struct bcmstb_spi_plat {
84 struct bcmstb_spi_priv {
85 struct bcmstb_hif_mspi_regs *regs;
93 u8 saved_cmd[NUM_CDRAM];
98 static int bcmstb_spi_of_to_plat(struct udevice *bus)
100 struct bcmstb_spi_plat *plat = dev_get_plat(bus);
101 const void *fdt = gd->fdt_blob;
102 int node = dev_of_offset(bus);
105 struct fdt_resource resource = { 0 };
106 char *names[BASE_LAST] = { "hif_mspi", "bspi", "hif_spi_intr2",
108 const phys_addr_t defaults[BASE_LAST] = { BCMSTB_HIF_MSPI_BASE,
110 BCMSTB_HIF_SPI_INTR2,
113 for (i = 0; i < BASE_LAST; i++) {
114 plat->base[i] = (void *)defaults[i];
116 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
117 names[i], &resource);
119 printf("%s: Assuming BCMSTB SPI %s address 0x0x%p\n",
120 __func__, names[i], (void *)defaults[i]);
122 plat->base[i] = (void *)resource.start;
123 debug("BCMSTB SPI %s address: 0x0x%p\n",
124 names[i], (void *)plat->base[i]);
131 static void bcmstb_spi_hw_set_parms(struct bcmstb_spi_priv *priv)
133 writel(SPBR_MIN, &priv->regs->spcr0_lsb);
134 writel(BITS_PER_WORD << 2 | SPI_MODE_3, &priv->regs->spcr0_msb);
137 static void bcmstb_spi_enable_interrupt(void *base, u32 mask)
139 void *reg = base + HIF_SPI_INTR2_CPU_MASK_CLEAR;
141 writel(readl(reg) | mask, reg);
145 static void bcmstb_spi_disable_interrupt(void *base, u32 mask)
147 void *reg = base + HIF_SPI_INTR2_CPU_MASK_SET;
149 writel(readl(reg) | mask, reg);
153 static void bcmstb_spi_clear_interrupt(void *base, u32 mask)
155 void *reg = base + HIF_SPI_INTR2_CPU_CLEAR;
157 writel(readl(reg) | mask, reg);
161 static int bcmstb_spi_probe(struct udevice *bus)
163 struct bcmstb_spi_plat *plat = dev_get_plat(bus);
164 struct bcmstb_spi_priv *priv = dev_get_priv(bus);
166 priv->regs = plat->base[HIF_MSPI];
167 priv->bspi = plat->base[BSPI];
168 priv->hif_spi_intr2 = plat->base[HIF_SPI_INTR2];
169 priv->cs_reg = plat->base[CS_REG];
170 priv->default_cs = 0;
174 memset(priv->saved_cmd, 0, NUM_CDRAM);
175 priv->saved_cmd_len = 0;
176 priv->saved_din_addr = NULL;
178 debug("spi_xfer: tx regs: 0x%p\n", &priv->regs->txram[0]);
179 debug("spi_xfer: rx regs: 0x%p\n", &priv->regs->rxram[0]);
182 writel(1, priv->bspi + BSPI_MAST_N_BOOT_CTRL);
183 readl(priv->bspi + BSPI_MAST_N_BOOT_CTRL);
185 /* Set up interrupts. */
186 bcmstb_spi_disable_interrupt(priv->hif_spi_intr2, 0xffffffff);
187 bcmstb_spi_clear_interrupt(priv->hif_spi_intr2, 0xffffffff);
188 bcmstb_spi_enable_interrupt(priv->hif_spi_intr2,
189 HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK);
191 /* Set up control registers. */
192 writel(0, &priv->regs->spcr1_lsb);
193 writel(0, &priv->regs->spcr1_msb);
194 writel(0, &priv->regs->newqp);
195 writel(0, &priv->regs->endqp);
196 writel(HIF_MSPI_SPCR2_SPIFIE_MASK, &priv->regs->spcr2);
197 writel(0, &priv->regs->spcr3);
199 bcmstb_spi_hw_set_parms(priv);
204 static void bcmstb_spi_submit(struct bcmstb_spi_priv *priv, bool done)
206 debug("WR NEWQP: %d\n", 0);
207 writel(0, &priv->regs->newqp);
209 debug("WR ENDQP: %d\n", priv->tx_slot - 1);
210 writel(priv->tx_slot - 1, &priv->regs->endqp);
213 debug("WR CDRAM[%d]: %02x\n", priv->tx_slot - 1,
214 readl(&priv->regs->cdram[priv->tx_slot - 1]) & ~0x80);
215 writel(readl(&priv->regs->cdram[priv->tx_slot - 1]) & ~0x80,
216 &priv->regs->cdram[priv->tx_slot - 1]);
219 /* Force chip select first time. */
220 if (priv->curr_cs != priv->default_cs) {
221 debug("spi_xfer: switching chip select to %d\n",
223 writel((readl(priv->cs_reg) & ~0xff) | (1 << priv->default_cs),
227 priv->curr_cs = priv->default_cs;
230 debug("WR WRITE_LOCK: %02x\n", 1);
231 writel((readl(&priv->regs->write_lock) &
232 ~HIF_MSPI_WRITE_LOCK_WRITE_LOCK_MASK) | 1,
233 &priv->regs->write_lock);
234 readl(&priv->regs->write_lock);
236 debug("WR SPCR2: %02x\n",
237 HIF_MSPI_SPCR2_SPIFIE_MASK |
238 HIF_MSPI_SPCR2_SPE_MASK |
239 HIF_MSPI_SPCR2_CONT_AFTER_CMD_MASK);
240 writel(HIF_MSPI_SPCR2_SPIFIE_MASK |
241 HIF_MSPI_SPCR2_SPE_MASK |
242 HIF_MSPI_SPCR2_CONT_AFTER_CMD_MASK,
246 static int bcmstb_spi_wait(struct bcmstb_spi_priv *priv)
248 u32 start_time = get_timer(0);
249 u32 status = readl(&priv->regs->mspi_status);
251 while (!(status & 1)) {
252 if (get_timer(start_time) > HIF_MSPI_WAIT)
254 status = readl(&priv->regs->mspi_status);
257 writel(readl(&priv->regs->mspi_status) & ~1, &priv->regs->mspi_status);
258 bcmstb_spi_clear_interrupt(priv->hif_spi_intr2,
259 HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK);
264 static int bcmstb_spi_xfer(struct udevice *dev, unsigned int bitlen,
265 const void *dout, void *din, unsigned long flags)
267 uint len = bitlen / 8;
270 const u8 *out_bytes = (u8 *)dout;
271 u8 *in_bytes = (u8 *)din;
272 struct udevice *bus = dev_get_parent(dev);
273 struct bcmstb_spi_priv *priv = dev_get_priv(bus);
274 struct bcmstb_hif_mspi_regs *regs = priv->regs;
276 debug("spi_xfer: %d, t: 0x%p, r: 0x%p, f: %lx\n",
277 len, dout, din, flags);
278 debug("spi_xfer: chip select: %x\n", readl(priv->cs_reg) & 0xff);
279 debug("spi_xfer: tx addr: 0x%p\n", ®s->txram[0]);
280 debug("spi_xfer: rx addr: 0x%p\n", ®s->rxram[0]);
281 debug("spi_xfer: cd addr: 0x%p\n", ®s->cdram[0]);
283 if (flags & SPI_XFER_END) {
284 debug("spi_xfer: clearing saved din address: 0x%p\n",
285 priv->saved_din_addr);
286 priv->saved_din_addr = NULL;
287 priv->saved_cmd_len = 0;
288 memset(priv->saved_cmd, 0, NUM_CDRAM);
295 printf("%s: Non-byte-aligned transfer\n", __func__);
299 if (flags & ~(SPI_XFER_BEGIN | SPI_XFER_END)) {
300 printf("%s: Unsupported flags: %lx\n", __func__, flags);
304 if (flags & SPI_XFER_BEGIN) {
308 if (out_bytes && len > NUM_CDRAM) {
309 printf("%s: Unable to save transfer\n", __func__);
313 if (out_bytes && !(flags & SPI_XFER_END)) {
315 * This is the start of a transmit operation
316 * that will need repeating if the calling
317 * code polls for the result. Save it for
318 * subsequent transmission.
320 debug("spi_xfer: saving command: %x, %d\n",
322 priv->saved_cmd_len = len;
323 memcpy(priv->saved_cmd, out_bytes, priv->saved_cmd_len);
327 if (!(flags & (SPI_XFER_BEGIN | SPI_XFER_END))) {
328 if (priv->saved_din_addr == din) {
330 * The caller is polling for status. Repeat
331 * the last transmission.
335 debug("spi_xfer: Making recursive call\n");
336 ret = bcmstb_spi_xfer(dev, priv->saved_cmd_len * 8,
337 priv->saved_cmd, NULL,
340 printf("%s: Recursive call failed\n", __func__);
344 debug("spi_xfer: saving din address: 0x%p\n", din);
345 priv->saved_din_addr = din;
350 priv->rx_slot = priv->tx_slot;
352 while (priv->tx_slot < NUM_CDRAM && tx_len > 0) {
353 bcmstb_spi_hw_set_parms(priv);
354 debug("WR TXRAM[%d]: %02x\n", priv->tx_slot,
355 out_bytes ? out_bytes[len - tx_len] : 0xff);
356 writel(out_bytes ? out_bytes[len - tx_len] : 0xff,
357 ®s->txram[priv->tx_slot << 1]);
358 debug("WR CDRAM[%d]: %02x\n", priv->tx_slot, 0x8e);
359 writel(0x8e, ®s->cdram[priv->tx_slot]);
366 debug("spi_xfer: early return clauses: %d, %d, %d\n",
369 (flags & (SPI_XFER_BEGIN |
370 SPI_XFER_END)) == SPI_XFER_BEGIN);
371 if (len <= NUM_CDRAM &&
373 (flags & (SPI_XFER_BEGIN | SPI_XFER_END)) == SPI_XFER_BEGIN)
376 bcmstb_spi_submit(priv, tx_len == 0);
378 if (bcmstb_spi_wait(priv) == -ETIMEDOUT) {
379 printf("%s: Timed out\n", __func__);
383 priv->tx_slot %= NUM_CDRAM;
386 while (priv->rx_slot < NUM_CDRAM && rx_len > 0) {
387 in_bytes[len - rx_len] =
388 readl(®s->rxram[(priv->rx_slot << 1)
391 debug("RD RXRAM[%d]: %02x\n",
392 priv->rx_slot, in_bytes[len - rx_len]);
399 if (flags & SPI_XFER_END) {
400 debug("WR WRITE_LOCK: %02x\n", 0);
401 writel((readl(&priv->regs->write_lock) &
402 ~HIF_MSPI_WRITE_LOCK_WRITE_LOCK_MASK) | 0,
403 &priv->regs->write_lock);
404 readl(&priv->regs->write_lock);
410 static int bcmstb_spi_set_speed(struct udevice *dev, uint speed)
415 static int bcmstb_spi_set_mode(struct udevice *dev, uint mode)
420 static const struct dm_spi_ops bcmstb_spi_ops = {
421 .xfer = bcmstb_spi_xfer,
422 .set_speed = bcmstb_spi_set_speed,
423 .set_mode = bcmstb_spi_set_mode,
426 static const struct udevice_id bcmstb_spi_id[] = {
427 { .compatible = "brcm,spi-brcmstb" },
431 U_BOOT_DRIVER(bcmstb_spi) = {
432 .name = "bcmstb_spi",
434 .of_match = bcmstb_spi_id,
435 .ops = &bcmstb_spi_ops,
436 .of_to_plat = bcmstb_spi_of_to_plat,
437 .probe = bcmstb_spi_probe,
438 .plat_auto = sizeof(struct bcmstb_spi_plat),
439 .priv_auto = sizeof(struct bcmstb_spi_priv),