1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2007 Atmel Corporation
15 #include <asm/arch/clk.h>
16 #include <asm/arch/hardware.h>
18 #include <asm/arch/at91_spi.h>
24 #include "atmel_spi.h"
28 static int spi_has_wdrbt(struct atmel_spi_slave *slave)
32 ver = spi_readl(slave, VERSION);
34 return (ATMEL_SPI_VERSION_REV(ver) >= 0x210);
42 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
43 unsigned int max_hz, unsigned int mode)
45 struct atmel_spi_slave *as;
50 if (!spi_cs_is_valid(bus, cs))
55 regs = (void *)ATMEL_BASE_SPI0;
57 #ifdef ATMEL_BASE_SPI1
59 regs = (void *)ATMEL_BASE_SPI1;
62 #ifdef ATMEL_BASE_SPI2
64 regs = (void *)ATMEL_BASE_SPI2;
67 #ifdef ATMEL_BASE_SPI3
69 regs = (void *)ATMEL_BASE_SPI3;
77 scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz;
78 if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
79 /* Too low max SCK rate */
84 csrx = ATMEL_SPI_CSRx_SCBR(scbr);
85 csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
86 if (!(mode & SPI_CPHA))
87 csrx |= ATMEL_SPI_CSRx_NCPHA;
89 csrx |= ATMEL_SPI_CSRx_CPOL;
91 as = spi_alloc_slave(struct atmel_spi_slave, bus, cs);
96 as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS
97 | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf);
98 if (spi_has_wdrbt(as))
99 as->mr |= ATMEL_SPI_MR_WDRBT;
101 spi_writel(as, CSR(cs), csrx);
106 void spi_free_slave(struct spi_slave *slave)
108 struct atmel_spi_slave *as = to_atmel_spi(slave);
113 int spi_claim_bus(struct spi_slave *slave)
115 struct atmel_spi_slave *as = to_atmel_spi(slave);
117 /* Enable the SPI hardware */
118 spi_writel(as, CR, ATMEL_SPI_CR_SPIEN);
121 * Select the slave. This should set SCK to the correct
122 * initial state, etc.
124 spi_writel(as, MR, as->mr);
129 void spi_release_bus(struct spi_slave *slave)
131 struct atmel_spi_slave *as = to_atmel_spi(slave);
133 /* Disable the SPI hardware */
134 spi_writel(as, CR, ATMEL_SPI_CR_SPIDIS);
137 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
138 const void *dout, void *din, unsigned long flags)
140 struct atmel_spi_slave *as = to_atmel_spi(slave);
145 const u8 *txp = dout;
150 /* Finish any previously submitted transfers */
154 * TODO: The controller can do non-multiple-of-8 bit
155 * transfers, but this driver currently doesn't support it.
157 * It's also not clear how such transfers are supposed to be
158 * represented as a stream of bytes...this is a limitation of
159 * the current SPI interface.
162 /* Errors always terminate an ongoing transfer */
163 flags |= SPI_XFER_END;
170 * The controller can do automatic CS control, but it is
171 * somewhat quirky, and it doesn't really buy us much anyway
172 * in the context of U-Boot.
174 if (flags & SPI_XFER_BEGIN) {
175 spi_cs_activate(slave);
177 * sometimes the RDR is not empty when we get here,
178 * in theory that should not happen, but it DOES happen.
179 * Read it here to be on the safe side.
180 * That also clears the OVRES flag. Required if the
181 * following loop exits due to OVRES!
186 for (len_tx = 0, len_rx = 0; len_rx < len; ) {
187 status = spi_readl(as, SR);
189 if (status & ATMEL_SPI_SR_OVRES)
192 if (len_tx < len && (status & ATMEL_SPI_SR_TDRE)) {
197 spi_writel(as, TDR, value);
200 if (status & ATMEL_SPI_SR_RDRF) {
201 value = spi_readl(as, RDR);
209 if (flags & SPI_XFER_END) {
211 * Wait until the transfer is completely done before
215 status = spi_readl(as, SR);
216 } while (!(status & ATMEL_SPI_SR_TXEMPTY));
218 spi_cs_deactivate(slave);
226 #define MAX_CS_COUNT 4
228 struct atmel_spi_platdata {
229 struct at91_spi *regs;
232 struct atmel_spi_priv {
233 unsigned int freq; /* Default frequency */
236 #ifdef CONFIG_DM_GPIO
237 struct gpio_desc cs_gpios[MAX_CS_COUNT];
241 static int atmel_spi_claim_bus(struct udevice *dev)
243 struct udevice *bus = dev_get_parent(dev);
244 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
245 struct atmel_spi_priv *priv = dev_get_priv(bus);
246 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
247 struct at91_spi *reg_base = bus_plat->regs;
248 u32 cs = slave_plat->cs;
249 u32 freq = priv->freq;
250 u32 scbr, csrx, mode;
252 scbr = (priv->bus_clk_rate + freq - 1) / freq;
253 if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
259 csrx = ATMEL_SPI_CSRx_SCBR(scbr);
260 csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
262 if (!(priv->mode & SPI_CPHA))
263 csrx |= ATMEL_SPI_CSRx_NCPHA;
264 if (priv->mode & SPI_CPOL)
265 csrx |= ATMEL_SPI_CSRx_CPOL;
267 writel(csrx, ®_base->csr[cs]);
269 mode = ATMEL_SPI_MR_MSTR |
270 ATMEL_SPI_MR_MODFDIS |
272 ATMEL_SPI_MR_PCS(~(1 << cs));
274 writel(mode, ®_base->mr);
276 writel(ATMEL_SPI_CR_SPIEN, ®_base->cr);
281 static int atmel_spi_release_bus(struct udevice *dev)
283 struct udevice *bus = dev_get_parent(dev);
284 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
286 writel(ATMEL_SPI_CR_SPIDIS, &bus_plat->regs->cr);
291 static void atmel_spi_cs_activate(struct udevice *dev)
293 #ifdef CONFIG_DM_GPIO
294 struct udevice *bus = dev_get_parent(dev);
295 struct atmel_spi_priv *priv = dev_get_priv(bus);
296 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
297 u32 cs = slave_plat->cs;
299 if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
302 dm_gpio_set_value(&priv->cs_gpios[cs], 0);
306 static void atmel_spi_cs_deactivate(struct udevice *dev)
308 #ifdef CONFIG_DM_GPIO
309 struct udevice *bus = dev_get_parent(dev);
310 struct atmel_spi_priv *priv = dev_get_priv(bus);
311 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
312 u32 cs = slave_plat->cs;
314 if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
317 dm_gpio_set_value(&priv->cs_gpios[cs], 1);
321 static int atmel_spi_xfer(struct udevice *dev, unsigned int bitlen,
322 const void *dout, void *din, unsigned long flags)
324 struct udevice *bus = dev_get_parent(dev);
325 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
326 struct at91_spi *reg_base = bus_plat->regs;
328 u32 len_tx, len_rx, len;
330 const u8 *txp = dout;
338 * The controller can do non-multiple-of-8 bit
339 * transfers, but this driver currently doesn't support it.
341 * It's also not clear how such transfers are supposed to be
342 * represented as a stream of bytes...this is a limitation of
343 * the current SPI interface.
346 /* Errors always terminate an ongoing transfer */
347 flags |= SPI_XFER_END;
354 * The controller can do automatic CS control, but it is
355 * somewhat quirky, and it doesn't really buy us much anyway
356 * in the context of U-Boot.
358 if (flags & SPI_XFER_BEGIN) {
359 atmel_spi_cs_activate(dev);
362 * sometimes the RDR is not empty when we get here,
363 * in theory that should not happen, but it DOES happen.
364 * Read it here to be on the safe side.
365 * That also clears the OVRES flag. Required if the
366 * following loop exits due to OVRES!
368 readl(®_base->rdr);
371 for (len_tx = 0, len_rx = 0; len_rx < len; ) {
372 status = readl(®_base->sr);
374 if (status & ATMEL_SPI_SR_OVRES)
377 if ((len_tx < len) && (status & ATMEL_SPI_SR_TDRE)) {
382 writel(value, ®_base->tdr);
386 if (status & ATMEL_SPI_SR_RDRF) {
387 value = readl(®_base->rdr);
395 if (flags & SPI_XFER_END) {
397 * Wait until the transfer is completely done before
400 wait_for_bit_le32(®_base->sr,
401 ATMEL_SPI_SR_TXEMPTY, true, 1000, false);
403 atmel_spi_cs_deactivate(dev);
409 static int atmel_spi_set_speed(struct udevice *bus, uint speed)
411 struct atmel_spi_priv *priv = dev_get_priv(bus);
418 static int atmel_spi_set_mode(struct udevice *bus, uint mode)
420 struct atmel_spi_priv *priv = dev_get_priv(bus);
427 static const struct dm_spi_ops atmel_spi_ops = {
428 .claim_bus = atmel_spi_claim_bus,
429 .release_bus = atmel_spi_release_bus,
430 .xfer = atmel_spi_xfer,
431 .set_speed = atmel_spi_set_speed,
432 .set_mode = atmel_spi_set_mode,
434 * cs_info is not needed, since we require all chip selects to be
435 * in the device tree explicitly
439 static int atmel_spi_enable_clk(struct udevice *bus)
441 struct atmel_spi_priv *priv = dev_get_priv(bus);
446 ret = clk_get_by_index(bus, 0, &clk);
450 ret = clk_enable(&clk);
454 clk_rate = clk_get_rate(&clk);
458 priv->bus_clk_rate = clk_rate;
465 static int atmel_spi_probe(struct udevice *bus)
467 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
470 ret = atmel_spi_enable_clk(bus);
474 bus_plat->regs = (struct at91_spi *)devfdt_get_addr(bus);
476 #ifdef CONFIG_DM_GPIO
477 struct atmel_spi_priv *priv = dev_get_priv(bus);
480 ret = gpio_request_list_by_name(bus, "cs-gpios", priv->cs_gpios,
481 ARRAY_SIZE(priv->cs_gpios), 0);
483 pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
487 for(i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
488 if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
491 dm_gpio_set_dir_flags(&priv->cs_gpios[i],
492 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
496 writel(ATMEL_SPI_CR_SWRST, &bus_plat->regs->cr);
501 static const struct udevice_id atmel_spi_ids[] = {
502 { .compatible = "atmel,at91rm9200-spi" },
506 U_BOOT_DRIVER(atmel_spi) = {
509 .of_match = atmel_spi_ids,
510 .ops = &atmel_spi_ops,
511 .platdata_auto_alloc_size = sizeof(struct atmel_spi_platdata),
512 .priv_auto_alloc_size = sizeof(struct atmel_spi_priv),
513 .probe = atmel_spi_probe,