1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Atmel QSPI Controller
5 * Copyright (C) 2015 Atmel Corporation
6 * Copyright (C) 2018 Cryptera A/S
8 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
9 * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
18 #include <linux/err.h>
20 #include <linux/iopoll.h>
21 #include <linux/ioport.h>
26 /* QSPI register offsets */
27 #define QSPI_CR 0x0000 /* Control Register */
28 #define QSPI_MR 0x0004 /* Mode Register */
29 #define QSPI_RD 0x0008 /* Receive Data Register */
30 #define QSPI_TD 0x000c /* Transmit Data Register */
31 #define QSPI_SR 0x0010 /* Status Register */
32 #define QSPI_IER 0x0014 /* Interrupt Enable Register */
33 #define QSPI_IDR 0x0018 /* Interrupt Disable Register */
34 #define QSPI_IMR 0x001c /* Interrupt Mask Register */
35 #define QSPI_SCR 0x0020 /* Serial Clock Register */
37 #define QSPI_IAR 0x0030 /* Instruction Address Register */
38 #define QSPI_ICR 0x0034 /* Instruction Code Register */
39 #define QSPI_WICR 0x0034 /* Write Instruction Code Register */
40 #define QSPI_IFR 0x0038 /* Instruction Frame Register */
41 #define QSPI_RICR 0x003C /* Read Instruction Code Register */
43 #define QSPI_SMR 0x0040 /* Scrambling Mode Register */
44 #define QSPI_SKR 0x0044 /* Scrambling Key Register */
46 #define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
47 #define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
49 #define QSPI_VERSION 0x00FC /* Version Register */
51 /* Bitfields in QSPI_CR (Control Register) */
52 #define QSPI_CR_QSPIEN BIT(0)
53 #define QSPI_CR_QSPIDIS BIT(1)
54 #define QSPI_CR_SWRST BIT(7)
55 #define QSPI_CR_LASTXFER BIT(24)
57 /* Bitfields in QSPI_MR (Mode Register) */
58 #define QSPI_MR_SMM BIT(0)
59 #define QSPI_MR_LLB BIT(1)
60 #define QSPI_MR_WDRBT BIT(2)
61 #define QSPI_MR_SMRM BIT(3)
62 #define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
63 #define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
64 #define QSPI_MR_CSMODE_LASTXFER (1 << 4)
65 #define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
66 #define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
67 #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
68 #define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
69 #define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
70 #define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
71 #define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
73 /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
74 #define QSPI_SR_RDRF BIT(0)
75 #define QSPI_SR_TDRE BIT(1)
76 #define QSPI_SR_TXEMPTY BIT(2)
77 #define QSPI_SR_OVRES BIT(3)
78 #define QSPI_SR_CSR BIT(8)
79 #define QSPI_SR_CSS BIT(9)
80 #define QSPI_SR_INSTRE BIT(10)
81 #define QSPI_SR_QSPIENS BIT(24)
83 #define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
85 /* Bitfields in QSPI_SCR (Serial Clock Register) */
86 #define QSPI_SCR_CPOL BIT(0)
87 #define QSPI_SCR_CPHA BIT(1)
88 #define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
89 #define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
90 #define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
91 #define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
93 /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
94 #define QSPI_ICR_INST_MASK GENMASK(7, 0)
95 #define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
96 #define QSPI_ICR_OPT_MASK GENMASK(23, 16)
97 #define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
99 /* Bitfields in QSPI_IFR (Instruction Frame Register) */
100 #define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
101 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
102 #define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
103 #define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
104 #define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
105 #define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
106 #define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
107 #define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
108 #define QSPI_IFR_INSTEN BIT(4)
109 #define QSPI_IFR_ADDREN BIT(5)
110 #define QSPI_IFR_OPTEN BIT(6)
111 #define QSPI_IFR_DATAEN BIT(7)
112 #define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
113 #define QSPI_IFR_OPTL_1BIT (0 << 8)
114 #define QSPI_IFR_OPTL_2BIT (1 << 8)
115 #define QSPI_IFR_OPTL_4BIT (2 << 8)
116 #define QSPI_IFR_OPTL_8BIT (3 << 8)
117 #define QSPI_IFR_ADDRL BIT(10)
118 #define QSPI_IFR_TFRTYP_MEM BIT(12)
119 #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
120 #define QSPI_IFR_CRM BIT(14)
121 #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
122 #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
123 #define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
125 /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
126 #define QSPI_SMR_SCREN BIT(0)
127 #define QSPI_SMR_RVDIS BIT(1)
129 /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
130 #define QSPI_WPMR_WPEN BIT(0)
131 #define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
132 #define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
134 /* Bitfields in QSPI_WPSR (Write Protection Status Register) */
135 #define QSPI_WPSR_WPVS BIT(0)
136 #define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
137 #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
139 struct atmel_qspi_caps {
147 const struct atmel_qspi_caps *caps;
152 struct atmel_qspi_mode {
159 static const struct atmel_qspi_mode atmel_qspi_modes[] = {
160 { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
161 { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
162 { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
163 { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
164 { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
165 { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
166 { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
169 static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
170 const struct atmel_qspi_mode *mode)
172 if (op->cmd.buswidth != mode->cmd_buswidth)
175 if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
178 if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
184 static int atmel_qspi_find_mode(const struct spi_mem_op *op)
188 for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
189 if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
195 static bool atmel_qspi_supports_op(struct spi_slave *slave,
196 const struct spi_mem_op *op)
198 if (atmel_qspi_find_mode(op) < 0)
201 /* special case not supported by hardware */
202 if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
203 op->dummy.nbytes == 0)
209 static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
210 const struct spi_mem_op *op, u32 *offset)
213 u32 dummy_cycles = 0;
217 icr = QSPI_ICR_INST(op->cmd.opcode);
218 ifr = QSPI_IFR_INSTEN;
220 mode = atmel_qspi_find_mode(op);
223 ifr |= atmel_qspi_modes[mode].config;
225 if (op->dummy.buswidth && op->dummy.nbytes)
226 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
229 * The controller allows 24 and 32-bit addressing while NAND-flash
230 * requires 16-bit long. Handling 8-bit long addresses is done using
231 * the option field. For the 16-bit addresses, the workaround depends
232 * of the number of requested dummy bits. If there are 8 or more dummy
233 * cycles, the address is shifted and sent with the first dummy byte.
234 * Otherwise opcode is disabled and the first byte of the address
235 * contains the command opcode (works only if the opcode and address
236 * use the same buswidth). The limitation is when the 16-bit address is
237 * used without enough dummy cycles and the opcode is using a different
238 * buswidth than the address.
240 if (op->addr.buswidth) {
241 switch (op->addr.nbytes) {
245 ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
246 icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
249 if (dummy_cycles < 8 / op->addr.buswidth) {
250 ifr &= ~QSPI_IFR_INSTEN;
251 ifr |= QSPI_IFR_ADDREN;
252 iar = (op->cmd.opcode << 16) |
253 (op->addr.val & 0xffff);
255 ifr |= QSPI_IFR_ADDREN;
256 iar = (op->addr.val << 8) & 0xffffff;
257 dummy_cycles -= 8 / op->addr.buswidth;
261 ifr |= QSPI_IFR_ADDREN;
262 iar = op->addr.val & 0xffffff;
265 ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
266 iar = op->addr.val & 0x7ffffff;
273 /* offset of the data access in the QSPI memory space */
276 /* Set number of dummy cycles */
278 ifr |= QSPI_IFR_NBDUM(dummy_cycles);
280 /* Set data enable */
282 ifr |= QSPI_IFR_DATAEN;
285 * If the QSPI controller is set in regular SPI mode, set it in
286 * Serial Memory Mode (SMM).
288 if (aq->mr != QSPI_MR_SMM) {
289 writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
290 aq->mr = QSPI_MR_SMM;
293 /* Clear pending interrupts */
294 (void)readl(aq->regs + QSPI_SR);
296 if (aq->caps->has_ricr) {
297 if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
298 ifr |= QSPI_IFR_APBTFRTYP_READ;
300 /* Set QSPI Instruction Frame registers */
301 writel(iar, aq->regs + QSPI_IAR);
302 if (op->data.dir == SPI_MEM_DATA_IN)
303 writel(icr, aq->regs + QSPI_RICR);
305 writel(icr, aq->regs + QSPI_WICR);
306 writel(ifr, aq->regs + QSPI_IFR);
308 if (op->data.dir == SPI_MEM_DATA_OUT)
309 ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
311 /* Set QSPI Instruction Frame registers */
312 writel(iar, aq->regs + QSPI_IAR);
313 writel(icr, aq->regs + QSPI_ICR);
314 writel(ifr, aq->regs + QSPI_IFR);
320 static int atmel_qspi_exec_op(struct spi_slave *slave,
321 const struct spi_mem_op *op)
323 struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
327 err = atmel_qspi_set_cfg(aq, op, &offset);
331 /* Skip to the final steps if there is no data */
332 if (op->data.nbytes) {
333 /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
334 (void)readl(aq->regs + QSPI_IFR);
336 /* Send/Receive data */
337 if (op->data.dir == SPI_MEM_DATA_IN)
338 memcpy_fromio(op->data.buf.in, aq->mem + offset,
341 memcpy_toio(aq->mem + offset, op->data.buf.out,
344 /* Release the chip-select */
345 writel(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
348 /* Poll INSTruction End and Chip Select Rise flags. */
349 imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
350 return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
354 static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
356 struct atmel_qspi *aq = dev_get_priv(bus);
357 u32 scr, scbr, mask, new_value;
359 /* Compute the QSPI baudrate */
360 scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
364 new_value = QSPI_SCR_SCBR(scbr);
365 mask = QSPI_SCR_SCBR_MASK;
367 scr = readl(aq->regs + QSPI_SCR);
368 if ((scr & mask) == new_value)
371 scr = (scr & ~mask) | new_value;
372 writel(scr, aq->regs + QSPI_SCR);
377 static int atmel_qspi_set_mode(struct udevice *bus, uint mode)
379 struct atmel_qspi *aq = dev_get_priv(bus);
380 u32 scr, mask, new_value = 0;
383 new_value = QSPI_SCR_CPOL;
385 new_value = QSPI_SCR_CPHA;
387 mask = QSPI_SCR_CPOL | QSPI_SCR_CPHA;
389 scr = readl(aq->regs + QSPI_SCR);
390 if ((scr & mask) == new_value)
393 scr = (scr & ~mask) | new_value;
394 writel(scr, aq->regs + QSPI_SCR);
399 static int atmel_qspi_enable_clk(struct udevice *dev)
401 struct atmel_qspi *aq = dev_get_priv(dev);
402 struct clk pclk, qspick;
405 ret = clk_get_by_name(dev, "pclk", &pclk);
407 ret = clk_get_by_index(dev, 0, &pclk);
410 dev_err(dev, "Missing QSPI peripheral clock\n");
414 ret = clk_enable(&pclk);
416 dev_err(dev, "Failed to enable QSPI peripheral clock\n");
420 if (aq->caps->has_qspick) {
421 /* Get the QSPI system clock */
422 ret = clk_get_by_name(dev, "qspick", &qspick);
424 dev_err(dev, "Missing QSPI peripheral clock\n");
428 ret = clk_enable(&qspick);
430 dev_err(dev, "Failed to enable QSPI system clock\n");
434 aq->bus_clk_rate = clk_get_rate(&pclk);
435 if (!aq->bus_clk_rate)
444 static void atmel_qspi_init(struct atmel_qspi *aq)
446 /* Reset the QSPI controller */
447 writel(QSPI_CR_SWRST, aq->regs + QSPI_CR);
449 /* Set the QSPI controller by default in Serial Memory Mode */
450 writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
451 aq->mr = QSPI_MR_SMM;
453 /* Enable the QSPI controller */
454 writel(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
457 static int atmel_qspi_probe(struct udevice *dev)
459 struct atmel_qspi *aq = dev_get_priv(dev);
463 aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
465 dev_err(dev, "Could not retrieve QSPI caps\n");
469 /* Map the registers */
470 ret = dev_read_resource_byname(dev, "qspi_base", &res);
472 dev_err(dev, "missing registers\n");
476 aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
477 if (IS_ERR(aq->regs))
478 return PTR_ERR(aq->regs);
480 /* Map the AHB memory */
481 ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
483 dev_err(dev, "missing AHB memory\n");
487 aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
489 return PTR_ERR(aq->mem);
491 ret = atmel_qspi_enable_clk(dev);
500 static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
501 .supports_op = atmel_qspi_supports_op,
502 .exec_op = atmel_qspi_exec_op,
505 static const struct dm_spi_ops atmel_qspi_ops = {
506 .set_speed = atmel_qspi_set_speed,
507 .set_mode = atmel_qspi_set_mode,
508 .mem_ops = &atmel_qspi_mem_ops,
511 static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
513 static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
518 static const struct udevice_id atmel_qspi_ids[] = {
520 .compatible = "atmel,sama5d2-qspi",
521 .data = (ulong)&atmel_sama5d2_qspi_caps,
524 .compatible = "microchip,sam9x60-qspi",
525 .data = (ulong)&atmel_sam9x60_qspi_caps,
530 U_BOOT_DRIVER(atmel_qspi) = {
531 .name = "atmel_qspi",
533 .of_match = atmel_qspi_ids,
534 .ops = &atmel_qspi_ops,
535 .priv_auto_alloc_size = sizeof(struct atmel_qspi),
536 .probe = atmel_qspi_probe,