1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Atmel QSPI Controller
5 * Copyright (C) 2015 Atmel Corporation
6 * Copyright (C) 2018 Cryptera A/S
8 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
9 * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
19 #include <dm/device_compat.h>
20 #include <linux/bitfield.h>
21 #include <linux/bitops.h>
22 #include <linux/err.h>
24 #include <linux/iopoll.h>
25 #include <linux/ioport.h>
30 /* QSPI register offsets */
31 #define QSPI_CR 0x0000 /* Control Register */
32 #define QSPI_MR 0x0004 /* Mode Register */
33 #define QSPI_RD 0x0008 /* Receive Data Register */
34 #define QSPI_TD 0x000c /* Transmit Data Register */
35 #define QSPI_SR 0x0010 /* Status Register */
36 #define QSPI_SR2 0x0024 /* SAMA7G5 Status Register */
37 #define QSPI_IER 0x0014 /* Interrupt Enable Register */
38 #define QSPI_IDR 0x0018 /* Interrupt Disable Register */
39 #define QSPI_IMR 0x001c /* Interrupt Mask Register */
40 #define QSPI_SCR 0x0020 /* Serial Clock Register */
42 #define QSPI_IAR 0x0030 /* Instruction Address Register */
43 #define QSPI_ICR 0x0034 /* Instruction Code Register */
44 #define QSPI_WICR 0x0034 /* Write Instruction Code Register */
45 #define QSPI_IFR 0x0038 /* Instruction Frame Register */
46 #define QSPI_RICR 0x003C /* Read Instruction Code Register */
48 #define QSPI_SMR 0x0040 /* Scrambling Mode Register */
49 #define QSPI_SKR 0x0044 /* Scrambling Key Register */
51 #define QSPI_REFRESH 0x0050 /* Refresh Register */
52 #define QSPI_WRACNT 0x0054 /* Write Access Counter Register */
53 #define QSPI_DLLCFG 0x0058 /* DLL Configuration Register */
54 #define QSPI_PCALCFG 0x005C /* Pad Calibration Configuration Register */
55 #define QSPI_PCALBP 0x0060 /* Pad Calibration Bypass Register */
56 #define QSPI_TOUT 0x0064 /* Timeout Register */
58 #define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
59 #define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
61 #define QSPI_VERSION 0x00FC /* Version Register */
63 /* Bitfields in QSPI_CR (Control Register) */
64 #define QSPI_CR_QSPIEN BIT(0)
65 #define QSPI_CR_QSPIDIS BIT(1)
66 #define QSPI_CR_DLLON BIT(2)
67 #define QSPI_CR_DLLOFF BIT(3)
68 #define QSPI_CR_STPCAL BIT(4)
69 #define QSPI_CR_SRFRSH BIT(5)
70 #define QSPI_CR_SWRST BIT(7)
71 #define QSPI_CR_UPDCFG BIT(8)
72 #define QSPI_CR_STTFR BIT(9)
73 #define QSPI_CR_RTOUT BIT(10)
74 #define QSPI_CR_LASTXFER BIT(24)
76 /* Bitfields in QSPI_MR (Mode Register) */
77 #define QSPI_MR_SMM BIT(0)
78 #define QSPI_MR_LLB BIT(1)
79 #define QSPI_MR_WDRBT BIT(2)
80 #define QSPI_MR_SMRM BIT(3)
81 #define QSPI_MR_DQSDLYEN BIT(3)
83 #define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
84 #define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
85 #define QSPI_MR_CSMODE_LASTXFER (1 << 4)
86 #define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
87 #define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
88 #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
89 #define QSPI_MR_OENSD BIT(15)
90 #define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
91 #define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
92 #define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
93 #define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
95 /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
96 #define QSPI_SR_RDRF BIT(0)
97 #define QSPI_SR_TDRE BIT(1)
98 #define QSPI_SR_TXEMPTY BIT(2)
99 #define QSPI_SR_OVRES BIT(3)
100 #define QSPI_SR_CSR BIT(8)
101 #define QSPI_SR_CSS BIT(9)
102 #define QSPI_SR_INSTRE BIT(10)
103 #define QSPI_SR_LWRA BIT(11)
104 #define QSPI_SR_QITF BIT(12)
105 #define QSPI_SR_QITR BIT(13)
106 #define QSPI_SR_CSFA BIT(14)
107 #define QSPI_SR_CSRA BIT(15)
108 #define QSPI_SR_RFRSHD BIT(16)
109 #define QSPI_SR_TOUT BIT(17)
110 #define QSPI_SR_QSPIENS BIT(24)
112 #define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
114 /* Bitfields in QSPI_SCR (Serial Clock Register) */
115 #define QSPI_SCR_CPOL BIT(0)
116 #define QSPI_SCR_CPHA BIT(1)
117 #define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
118 #define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
119 #define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
120 #define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
122 /* Bitfields in QSPI_SR2 (SAMA7G5 Status Register) */
123 #define QSPI_SR2_SYNCBSY BIT(0)
124 #define QSPI_SR2_QSPIENS BIT(1)
125 #define QSPI_SR2_CSS BIT(2)
126 #define QSPI_SR2_RBUSY BIT(3)
127 #define QSPI_SR2_HIDLE BIT(4)
128 #define QSPI_SR2_DLOCK BIT(5)
129 #define QSPI_SR2_CALBSY BIT(6)
131 /* Bitfields in QSPI_IAR (Instruction Address Register) */
132 #define QSPI_IAR_ADDR GENMASK(31, 0)
134 /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
135 #define QSPI_ICR_INST_MASK GENMASK(7, 0)
136 #define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
137 #define QSPI_ICR_INST_MASK_SAMA7G5 GENMASK(15, 0)
138 #define QSPI_ICR_OPT_MASK GENMASK(23, 16)
139 #define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
141 /* Bitfields in QSPI_IFR (Instruction Frame Register) */
142 #define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
143 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
144 #define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
145 #define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
146 #define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
147 #define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
148 #define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
149 #define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
150 #define QSPI_IFR_WIDTH_OCT_OUTPUT (7 << 0)
151 #define QSPI_IFR_WIDTH_OCT_IO (8 << 0)
152 #define QSPI_IFR_WIDTH_OCT_CMD (9 << 0)
153 #define QSPI_IFR_INSTEN BIT(4)
154 #define QSPI_IFR_ADDREN BIT(5)
155 #define QSPI_IFR_OPTEN BIT(6)
156 #define QSPI_IFR_DATAEN BIT(7)
157 #define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
158 #define QSPI_IFR_OPTL_1BIT (0 << 8)
159 #define QSPI_IFR_OPTL_2BIT (1 << 8)
160 #define QSPI_IFR_OPTL_4BIT (2 << 8)
161 #define QSPI_IFR_OPTL_8BIT (3 << 8)
162 #define QSPI_IFR_ADDRL BIT(10)
163 #define QSPI_IFR_ADDRL_SAMA7G5 GENMASK(11, 10)
164 #define QSPI_IFR_TFRTYP_MEM BIT(12)
165 #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
166 #define QSPI_IFR_CRM BIT(14)
167 #define QSPI_IFR_DDREN BIT(15)
168 #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
169 #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
170 #define QSPI_IFR_END BIT(22)
171 #define QSPI_IFR_SMRM BIT(23)
172 #define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
173 #define QSPI_IFR_DQSEN BIT(25)
174 #define QSPI_IFR_DDRCMDEN BIT(26)
175 #define QSPI_IFR_HFWBEN BIT(27)
176 #define QSPI_IFR_PROTTYP GENMASK(29, 28)
177 #define QSPI_IFR_PROTTYP_STD_SPI 0
178 #define QSPI_IFR_PROTTYP_TWIN_QUAD 1
179 #define QSPI_IFR_PROTTYP_OCTAFLASH 2
180 #define QSPI_IFR_PROTTYP_HYPERFLASH 3
182 /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
183 #define QSPI_SMR_SCREN BIT(0)
184 #define QSPI_SMR_RVDIS BIT(1)
185 #define QSPI_SMR_SCRKL BIT(2)
187 /* Bitfields in QSPI_REFRESH (Refresh Register) */
188 #define QSPI_REFRESH_DELAY_COUNTER GENMASK(31, 0)
190 /* Bitfields in QSPI_WRACNT (Write Access Counter Register) */
191 #define QSPI_WRACNT_NBWRA GENMASK(31, 0)
193 /* Bitfields in QSPI_DLLCFG (DLL Configuration Register) */
194 #define QSPI_DLLCFG_RANGE BIT(0)
196 /* Bitfields in QSPI_PCALCFG (DLL Pad Calibration Configuration Register) */
197 #define QSPI_PCALCFG_AAON BIT(0)
198 #define QSPI_PCALCFG_DAPCAL BIT(1)
199 #define QSPI_PCALCFG_DIFFPM BIT(2)
200 #define QSPI_PCALCFG_CLKDIV GENMASK(6, 4)
201 #define QSPI_PCALCFG_CALCNT GENMASK(16, 8)
202 #define QSPI_PCALCFG_CALP GENMASK(27, 24)
203 #define QSPI_PCALCFG_CALN GENMASK(31, 28)
205 /* Bitfields in QSPI_PCALBP (DLL Pad Calibration Bypass Register) */
206 #define QSPI_PCALBP_BPEN BIT(0)
207 #define QSPI_PCALBP_CALPBP GENMASK(11, 8)
208 #define QSPI_PCALBP_CALNBP GENMASK(19, 16)
210 /* Bitfields in QSPI_TOUT (Timeout Register) */
211 #define QSPI_TOUT_TCNTM GENMASK(15, 0)
213 /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
214 #define QSPI_WPMR_WPEN BIT(0)
215 #define QSPI_WPMR_WPITEN BIT(1)
216 #define QSPI_WPMR_WPCREN BIT(2)
217 #define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
218 #define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
220 /* Bitfields in QSPI_WPSR (Write Protection Status Register) */
221 #define QSPI_WPSR_WPVS BIT(0)
222 #define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
223 #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
225 #define ATMEL_QSPI_TIMEOUT 1000000 /* us */
226 #define ATMEL_QSPI_SYNC_TIMEOUT 300000 /* us */
227 #define QSPI_DLLCFG_THRESHOLD_FREQ 90000000U
228 #define QSPI_TOUT_MAX 0xffff
231 * struct atmel_qspi_pcal - Pad Calibration Clock Division
232 * @pclk_rate: peripheral clock rate.
233 * @pclkdiv: calibration clock division. The clock applied to the calibration
234 * cell is divided by pclkdiv + 1.
236 struct atmel_qspi_pcal {
241 #define ATMEL_QSPI_PCAL_ARRAY_SIZE 8
242 static const struct atmel_qspi_pcal pcal[ATMEL_QSPI_PCAL_ARRAY_SIZE] = {
253 struct atmel_qspi_caps {
260 struct atmel_qspi_priv_ops;
265 resource_size_t mmap_size;
266 const struct atmel_qspi_caps *caps;
267 const struct atmel_qspi_priv_ops *ops;
273 struct atmel_qspi_priv_ops {
274 int (*set_cfg)(struct atmel_qspi *aq, const struct spi_mem_op *op,
276 int (*transfer)(struct atmel_qspi *aq, const struct spi_mem_op *op,
280 struct atmel_qspi_mode {
287 static const struct atmel_qspi_mode atmel_qspi_modes[] = {
288 { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
289 { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
290 { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
291 { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
292 { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
293 { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
294 { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
297 static const struct atmel_qspi_mode atmel_qspi_sama7g5_modes[] = {
298 { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
299 { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
300 { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
301 { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
302 { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
303 { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
304 { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
305 { 1, 1, 8, QSPI_IFR_WIDTH_OCT_OUTPUT },
306 { 1, 8, 8, QSPI_IFR_WIDTH_OCT_IO },
307 { 8, 8, 8, QSPI_IFR_WIDTH_OCT_CMD },
311 static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz)
365 snprintf(tmp, sz, "0x%02x", offset);
371 #endif /* VERBOSE_DEBUG */
373 static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
375 u32 value = readl(aq->regs + offset);
380 dev_vdbg(aq->dev, "read 0x%08x from %s\n", value,
381 atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
382 #endif /* VERBOSE_DEBUG */
387 static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
392 dev_vdbg(aq->dev, "write 0x%08x into %s\n", value,
393 atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
394 #endif /* VERBOSE_DEBUG */
396 writel(value, aq->regs + offset);
399 static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
400 const struct atmel_qspi_mode *mode)
402 if (op->cmd.buswidth != mode->cmd_buswidth)
405 if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
408 if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
414 static int atmel_qspi_find_mode(const struct spi_mem_op *op)
418 for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
419 if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
425 static int atmel_qspi_sama7g5_find_mode(const struct spi_mem_op *op)
429 for (i = 0; i < ARRAY_SIZE(atmel_qspi_sama7g5_modes); i++)
430 if (atmel_qspi_is_compatible(op, &atmel_qspi_sama7g5_modes[i]))
436 static bool atmel_qspi_supports_op(struct spi_slave *slave,
437 const struct spi_mem_op *op)
439 struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
441 if (aq->caps->octal) {
442 if (atmel_qspi_sama7g5_find_mode(op) < 0)
448 if (atmel_qspi_find_mode(op) < 0)
451 /* special case not supported by hardware */
452 if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
453 op->dummy.nbytes == 0)
459 static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
460 const struct spi_mem_op *op, u32 *offset)
463 u32 dummy_cycles = 0;
467 icr = QSPI_ICR_INST(op->cmd.opcode);
468 ifr = QSPI_IFR_INSTEN;
470 mode = atmel_qspi_find_mode(op);
473 ifr |= atmel_qspi_modes[mode].config;
475 if (op->dummy.buswidth && op->dummy.nbytes)
476 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
479 * The controller allows 24 and 32-bit addressing while NAND-flash
480 * requires 16-bit long. Handling 8-bit long addresses is done using
481 * the option field. For the 16-bit addresses, the workaround depends
482 * of the number of requested dummy bits. If there are 8 or more dummy
483 * cycles, the address is shifted and sent with the first dummy byte.
484 * Otherwise opcode is disabled and the first byte of the address
485 * contains the command opcode (works only if the opcode and address
486 * use the same buswidth). The limitation is when the 16-bit address is
487 * used without enough dummy cycles and the opcode is using a different
488 * buswidth than the address.
490 if (op->addr.buswidth) {
491 switch (op->addr.nbytes) {
495 ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
496 icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
499 if (dummy_cycles < 8 / op->addr.buswidth) {
500 ifr &= ~QSPI_IFR_INSTEN;
501 ifr |= QSPI_IFR_ADDREN;
502 iar = (op->cmd.opcode << 16) |
503 (op->addr.val & 0xffff);
505 ifr |= QSPI_IFR_ADDREN;
506 iar = (op->addr.val << 8) & 0xffffff;
507 dummy_cycles -= 8 / op->addr.buswidth;
511 ifr |= QSPI_IFR_ADDREN;
512 iar = op->addr.val & 0xffffff;
515 ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
516 iar = op->addr.val & 0x7ffffff;
523 /* offset of the data access in the QSPI memory space */
526 /* Set number of dummy cycles */
528 ifr |= QSPI_IFR_NBDUM(dummy_cycles);
530 /* Set data enable */
532 ifr |= QSPI_IFR_DATAEN;
535 * If the QSPI controller is set in regular SPI mode, set it in
536 * Serial Memory Mode (SMM).
538 if (aq->mr != QSPI_MR_SMM) {
539 atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
540 aq->mr = QSPI_MR_SMM;
543 /* Clear pending interrupts */
544 (void)atmel_qspi_read(aq, QSPI_SR);
546 if (aq->caps->has_ricr) {
547 if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
548 ifr |= QSPI_IFR_APBTFRTYP_READ;
550 /* Set QSPI Instruction Frame registers */
551 atmel_qspi_write(iar, aq, QSPI_IAR);
552 if (op->data.dir == SPI_MEM_DATA_IN)
553 atmel_qspi_write(icr, aq, QSPI_RICR);
555 atmel_qspi_write(icr, aq, QSPI_WICR);
556 atmel_qspi_write(ifr, aq, QSPI_IFR);
558 if (op->data.dir == SPI_MEM_DATA_OUT)
559 ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
561 /* Set QSPI Instruction Frame registers */
562 atmel_qspi_write(iar, aq, QSPI_IAR);
563 atmel_qspi_write(icr, aq, QSPI_ICR);
564 atmel_qspi_write(ifr, aq, QSPI_IFR);
570 static int atmel_qspi_transfer(struct atmel_qspi *aq,
571 const struct spi_mem_op *op, u32 offset)
575 /* Skip to the final steps if there is no data */
576 if (op->data.nbytes) {
577 /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
578 (void)atmel_qspi_read(aq, QSPI_IFR);
580 /* Send/Receive data */
581 if (op->data.dir == SPI_MEM_DATA_IN)
582 memcpy_fromio(op->data.buf.in, aq->mem + offset,
585 memcpy_toio(aq->mem + offset, op->data.buf.out,
588 /* Release the chip-select */
589 atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
592 /* Poll INSTruction End and Chip Select Rise flags. */
593 imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
594 return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
598 static int atmel_qspi_reg_sync(struct atmel_qspi *aq)
602 return readl_poll_timeout(aq->regs + QSPI_SR2, val,
603 !(val & QSPI_SR2_SYNCBSY),
604 ATMEL_QSPI_SYNC_TIMEOUT);
607 static int atmel_qspi_update_config(struct atmel_qspi *aq)
611 ret = atmel_qspi_reg_sync(aq);
614 atmel_qspi_write(QSPI_CR_UPDCFG, aq, QSPI_CR);
615 return atmel_qspi_reg_sync(aq);
618 static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq,
619 const struct spi_mem_op *op, u32 *offset)
625 icr = FIELD_PREP(QSPI_ICR_INST_MASK_SAMA7G5, op->cmd.opcode);
626 ifr = QSPI_IFR_INSTEN;
628 mode = atmel_qspi_sama7g5_find_mode(op);
631 ifr |= atmel_qspi_sama7g5_modes[mode].config;
633 if (op->dummy.buswidth && op->dummy.nbytes) {
634 if (op->addr.dtr && op->dummy.dtr && op->data.dtr)
635 ifr |= QSPI_IFR_NBDUM(op->dummy.nbytes * 8 /
636 (2 * op->dummy.buswidth));
638 ifr |= QSPI_IFR_NBDUM(op->dummy.nbytes * 8 /
642 if (op->addr.buswidth && op->addr.nbytes) {
643 ifr |= FIELD_PREP(QSPI_IFR_ADDRL_SAMA7G5, op->addr.nbytes - 1) |
645 iar = FIELD_PREP(QSPI_IAR_ADDR, op->addr.val);
648 if (op->addr.dtr && op->dummy.dtr && op->data.dtr) {
649 ifr |= QSPI_IFR_DDREN;
651 ifr |= QSPI_IFR_DDRCMDEN;
652 ifr |= QSPI_IFR_DQSEN;
655 if (op->cmd.buswidth == 8 || op->addr.buswidth == 8 ||
656 op->data.buswidth == 8)
657 ifr |= FIELD_PREP(QSPI_IFR_PROTTYP, QSPI_IFR_PROTTYP_OCTAFLASH);
659 /* offset of the data access in the QSPI memory space */
662 /* Set data enable */
663 if (op->data.nbytes) {
664 ifr |= QSPI_IFR_DATAEN;
666 ifr |= QSPI_IFR_TFRTYP_MEM;
670 * If the QSPI controller is set in regular SPI mode, set it in
671 * Serial Memory Mode (SMM).
673 if (aq->mr != QSPI_MR_SMM) {
674 atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR);
675 ret = atmel_qspi_update_config(aq);
678 aq->mr = QSPI_MR_SMM;
681 /* Clear pending interrupts */
682 (void)atmel_qspi_read(aq, QSPI_SR);
684 /* Set QSPI Instruction Frame registers */
685 if (op->addr.nbytes && !op->data.nbytes)
686 atmel_qspi_write(iar, aq, QSPI_IAR);
688 if (op->data.dir == SPI_MEM_DATA_IN) {
689 atmel_qspi_write(icr, aq, QSPI_RICR);
691 atmel_qspi_write(icr, aq, QSPI_WICR);
693 atmel_qspi_write(FIELD_PREP(QSPI_WRACNT_NBWRA,
698 atmel_qspi_write(ifr, aq, QSPI_IFR);
700 return atmel_qspi_update_config(aq);
703 static int atmel_qspi_sama7g5_transfer(struct atmel_qspi *aq,
704 const struct spi_mem_op *op, u32 offset)
709 if (!op->data.nbytes) {
710 /* Start the transfer. */
711 err = atmel_qspi_reg_sync(aq);
714 atmel_qspi_write(QSPI_CR_STTFR, aq, QSPI_CR);
716 return readl_poll_timeout(aq->regs + QSPI_SR, val,
721 /* Send/Receive data. */
722 if (op->data.dir == SPI_MEM_DATA_IN) {
723 memcpy_fromio(op->data.buf.in, aq->mem + offset,
726 if (op->addr.nbytes) {
727 err = readl_poll_timeout(aq->regs + QSPI_SR2, val,
728 !(val & QSPI_SR2_RBUSY),
729 ATMEL_QSPI_SYNC_TIMEOUT);
734 memcpy_toio(aq->mem + offset, op->data.buf.out,
737 err = readl_poll_timeout(aq->regs + QSPI_SR, val,
744 /* Release the chip-select. */
745 err = atmel_qspi_reg_sync(aq);
748 atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
750 return readl_poll_timeout(aq->regs + QSPI_SR, val, val & QSPI_SR_CSRA,
754 static int atmel_qspi_exec_op(struct spi_slave *slave,
755 const struct spi_mem_op *op)
757 struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
762 * Check if the address exceeds the MMIO window size. An improvement
763 * would be to add support for regular SPI mode and fall back to it
764 * when the flash memories overrun the controller's memory space.
766 if (op->addr.val + op->data.nbytes > aq->mmap_size)
769 if (op->addr.nbytes > 4)
772 err = aq->ops->set_cfg(aq, op, &offset);
776 return aq->ops->transfer(aq, op, offset);
779 static int atmel_qspi_set_pad_calibration(struct udevice *bus, uint hz)
781 struct atmel_qspi *aq = dev_get_priv(bus);
786 for (i = 0; i < ATMEL_QSPI_PCAL_ARRAY_SIZE; i++) {
787 if (aq->bus_clk_rate <= pcal[i].pclk_rate) {
788 pclk_div = pcal[i].pclk_div;
794 * Use the biggest divider in case the peripheral clock exceeds
797 if (aq->bus_clk_rate > pcal[ATMEL_QSPI_PCAL_ARRAY_SIZE - 1].pclk_rate)
798 pclk_div = pcal[ATMEL_QSPI_PCAL_ARRAY_SIZE - 1].pclk_div;
800 /* Disable QSPI while configuring the pad calibration. */
801 status = atmel_qspi_read(aq, QSPI_SR2);
802 if (status & QSPI_SR2_QSPIENS) {
803 ret = atmel_qspi_reg_sync(aq);
806 atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
810 * The analog circuitry is not shut down at the end of the calibration
811 * and the start-up time is only required for the first calibration
812 * sequence, thus increasing performance. Set the delay between the Pad
813 * calibration analog circuitry and the calibration request to 2us.
815 atmel_qspi_write(QSPI_PCALCFG_AAON |
816 FIELD_PREP(QSPI_PCALCFG_CLKDIV, pclk_div) |
817 FIELD_PREP(QSPI_PCALCFG_CALCNT,
818 2 * (aq->bus_clk_rate / 1000000)),
821 /* DLL On + start calibration. */
822 atmel_qspi_write(QSPI_CR_DLLON | QSPI_CR_STPCAL, aq, QSPI_CR);
823 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
824 (val & QSPI_SR2_DLOCK) &&
825 !(val & QSPI_SR2_CALBSY),
828 /* Refresh analogic blocks every 1 ms.*/
829 atmel_qspi_write(FIELD_PREP(QSPI_REFRESH_DELAY_COUNTER, hz / 1000),
835 static int atmel_qspi_set_gclk(struct udevice *bus, uint hz)
837 struct atmel_qspi *aq = dev_get_priv(bus);
842 /* Disable DLL before setting GCLK */
843 status = atmel_qspi_read(aq, QSPI_SR2);
844 if (status & QSPI_SR2_DLOCK) {
845 atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR);
846 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
847 !(val & QSPI_SR2_DLOCK),
853 if (hz > QSPI_DLLCFG_THRESHOLD_FREQ)
854 atmel_qspi_write(QSPI_DLLCFG_RANGE, aq, QSPI_DLLCFG);
856 atmel_qspi_write(0, aq, QSPI_DLLCFG);
858 ret = clk_get_by_name(bus, "gclk", &gclk);
860 dev_err(bus, "Missing QSPI generic clock\n");
864 ret = clk_disable(&gclk);
866 dev_err(bus, "Failed to disable QSPI generic clock\n");
868 ret = clk_set_rate(&gclk, hz);
870 dev_err(bus, "Failed to set generic clock rate.\n");
874 ret = clk_enable(&gclk);
876 dev_err(bus, "Failed to enable QSPI generic clock\n");
882 static int atmel_qspi_sama7g5_set_speed(struct udevice *bus, uint hz)
884 struct atmel_qspi *aq = dev_get_priv(bus);
888 ret = atmel_qspi_set_gclk(bus, hz);
892 if (aq->caps->octal) {
893 ret = atmel_qspi_set_pad_calibration(bus, hz);
897 atmel_qspi_write(QSPI_CR_DLLON, aq, QSPI_CR);
898 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
899 val & QSPI_SR2_DLOCK,
903 /* Set the QSPI controller by default in Serial Memory Mode */
904 atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR);
905 ret = atmel_qspi_update_config(aq);
908 aq->mr = QSPI_MR_SMM;
910 /* Enable the QSPI controller. */
911 ret = atmel_qspi_reg_sync(aq);
914 atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
915 ret = readl_poll_timeout(aq->regs + QSPI_SR2, val,
916 val & QSPI_SR2_QSPIENS,
917 ATMEL_QSPI_SYNC_TIMEOUT);
922 ret = readl_poll_timeout(aq->regs + QSPI_SR, val,
923 val & QSPI_SR_RFRSHD,
926 atmel_qspi_write(FIELD_PREP(QSPI_TOUT_TCNTM, QSPI_TOUT_MAX),
932 static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
934 struct atmel_qspi *aq = dev_get_priv(bus);
935 u32 scr, scbr, mask, new_value;
937 if (aq->caps->has_gclk)
938 return atmel_qspi_sama7g5_set_speed(bus, hz);
940 /* Compute the QSPI baudrate */
941 scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
945 new_value = QSPI_SCR_SCBR(scbr);
946 mask = QSPI_SCR_SCBR_MASK;
948 scr = atmel_qspi_read(aq, QSPI_SCR);
949 if ((scr & mask) == new_value)
952 scr = (scr & ~mask) | new_value;
953 atmel_qspi_write(scr, aq, QSPI_SCR);
958 static int atmel_qspi_set_mode(struct udevice *bus, uint mode)
960 struct atmel_qspi *aq = dev_get_priv(bus);
961 u32 scr, mask, new_value = 0;
964 new_value = QSPI_SCR_CPOL;
966 new_value = QSPI_SCR_CPHA;
968 mask = QSPI_SCR_CPOL | QSPI_SCR_CPHA;
970 scr = atmel_qspi_read(aq, QSPI_SCR);
971 if ((scr & mask) == new_value)
974 scr = (scr & ~mask) | new_value;
975 atmel_qspi_write(scr, aq, QSPI_SCR);
976 if (aq->caps->has_gclk)
977 return atmel_qspi_update_config(aq);
982 static int atmel_qspi_enable_clk(struct udevice *dev)
984 struct atmel_qspi *aq = dev_get_priv(dev);
985 struct clk pclk, qspick, gclk;
988 ret = clk_get_by_name(dev, "pclk", &pclk);
990 ret = clk_get_by_index(dev, 0, &pclk);
993 dev_err(dev, "Missing QSPI peripheral clock\n");
997 ret = clk_enable(&pclk);
999 dev_err(dev, "Failed to enable QSPI peripheral clock\n");
1003 if (aq->caps->has_qspick) {
1004 /* Get the QSPI system clock */
1005 ret = clk_get_by_name(dev, "qspick", &qspick);
1007 dev_err(dev, "Missing QSPI peripheral clock\n");
1011 ret = clk_enable(&qspick);
1013 dev_err(dev, "Failed to enable QSPI system clock\n");
1015 } else if (aq->caps->has_gclk) {
1016 ret = clk_get_by_name(dev, "gclk", &gclk);
1018 dev_err(dev, "Missing QSPI generic clock\n");
1022 ret = clk_enable(&gclk);
1024 dev_err(dev, "Failed to enable QSPI system clock\n");
1028 aq->bus_clk_rate = clk_get_rate(&pclk);
1029 if (!aq->bus_clk_rate)
1038 static int atmel_qspi_init(struct atmel_qspi *aq)
1042 if (aq->caps->has_gclk) {
1043 ret = atmel_qspi_reg_sync(aq);
1046 atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
1050 /* Reset the QSPI controller */
1051 atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
1053 /* Set the QSPI controller by default in Serial Memory Mode */
1054 atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
1055 aq->mr = QSPI_MR_SMM;
1057 /* Enable the QSPI controller */
1058 atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
1063 static const struct atmel_qspi_priv_ops atmel_qspi_priv_ops = {
1064 .set_cfg = atmel_qspi_set_cfg,
1065 .transfer = atmel_qspi_transfer,
1068 static const struct atmel_qspi_priv_ops atmel_qspi_sama7g5_priv_ops = {
1069 .set_cfg = atmel_qspi_sama7g5_set_cfg,
1070 .transfer = atmel_qspi_sama7g5_transfer,
1073 static int atmel_qspi_probe(struct udevice *dev)
1075 struct atmel_qspi *aq = dev_get_priv(dev);
1076 struct resource res;
1079 aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
1081 dev_err(dev, "Could not retrieve QSPI caps\n");
1085 if (aq->caps->has_gclk)
1086 aq->ops = &atmel_qspi_sama7g5_priv_ops;
1088 aq->ops = &atmel_qspi_priv_ops;
1090 /* Map the registers */
1091 ret = dev_read_resource_byname(dev, "qspi_base", &res);
1093 dev_err(dev, "missing registers\n");
1097 aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
1098 if (IS_ERR(aq->regs))
1099 return PTR_ERR(aq->regs);
1101 /* Map the AHB memory */
1102 ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
1104 dev_err(dev, "missing AHB memory\n");
1108 aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
1109 if (IS_ERR(aq->mem))
1110 return PTR_ERR(aq->mem);
1112 aq->mmap_size = resource_size(&res);
1114 ret = atmel_qspi_enable_clk(dev);
1119 return atmel_qspi_init(aq);
1122 static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
1123 .supports_op = atmel_qspi_supports_op,
1124 .exec_op = atmel_qspi_exec_op,
1127 static const struct dm_spi_ops atmel_qspi_ops = {
1128 .set_speed = atmel_qspi_set_speed,
1129 .set_mode = atmel_qspi_set_mode,
1130 .mem_ops = &atmel_qspi_mem_ops,
1133 static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
1135 static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
1140 static const struct atmel_qspi_caps atmel_sama7g5_ospi_caps = {
1145 static const struct atmel_qspi_caps atmel_sama7g5_qspi_caps = {
1149 static const struct udevice_id atmel_qspi_ids[] = {
1151 .compatible = "atmel,sama5d2-qspi",
1152 .data = (ulong)&atmel_sama5d2_qspi_caps,
1155 .compatible = "microchip,sam9x60-qspi",
1156 .data = (ulong)&atmel_sam9x60_qspi_caps,
1159 .compatible = "microchip,sama7g5-ospi",
1160 .data = (ulong)&atmel_sama7g5_ospi_caps,
1163 .compatible = "microchip,sama7g5-qspi",
1164 .data = (ulong)&atmel_sama7g5_qspi_caps,
1169 U_BOOT_DRIVER(atmel_qspi) = {
1170 .name = "atmel_qspi",
1172 .of_match = atmel_qspi_ids,
1173 .ops = &atmel_qspi_ops,
1174 .priv_auto = sizeof(struct atmel_qspi),
1175 .probe = atmel_qspi_probe,