1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Atmel QSPI Controller
5 * Copyright (C) 2015 Atmel Corporation
6 * Copyright (C) 2018 Cryptera A/S
8 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
9 * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
19 #include <dm/device_compat.h>
20 #include <linux/err.h>
22 #include <linux/iopoll.h>
23 #include <linux/ioport.h>
28 /* QSPI register offsets */
29 #define QSPI_CR 0x0000 /* Control Register */
30 #define QSPI_MR 0x0004 /* Mode Register */
31 #define QSPI_RD 0x0008 /* Receive Data Register */
32 #define QSPI_TD 0x000c /* Transmit Data Register */
33 #define QSPI_SR 0x0010 /* Status Register */
34 #define QSPI_IER 0x0014 /* Interrupt Enable Register */
35 #define QSPI_IDR 0x0018 /* Interrupt Disable Register */
36 #define QSPI_IMR 0x001c /* Interrupt Mask Register */
37 #define QSPI_SCR 0x0020 /* Serial Clock Register */
39 #define QSPI_IAR 0x0030 /* Instruction Address Register */
40 #define QSPI_ICR 0x0034 /* Instruction Code Register */
41 #define QSPI_WICR 0x0034 /* Write Instruction Code Register */
42 #define QSPI_IFR 0x0038 /* Instruction Frame Register */
43 #define QSPI_RICR 0x003C /* Read Instruction Code Register */
45 #define QSPI_SMR 0x0040 /* Scrambling Mode Register */
46 #define QSPI_SKR 0x0044 /* Scrambling Key Register */
48 #define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
49 #define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
51 #define QSPI_VERSION 0x00FC /* Version Register */
53 /* Bitfields in QSPI_CR (Control Register) */
54 #define QSPI_CR_QSPIEN BIT(0)
55 #define QSPI_CR_QSPIDIS BIT(1)
56 #define QSPI_CR_SWRST BIT(7)
57 #define QSPI_CR_LASTXFER BIT(24)
59 /* Bitfields in QSPI_MR (Mode Register) */
60 #define QSPI_MR_SMM BIT(0)
61 #define QSPI_MR_LLB BIT(1)
62 #define QSPI_MR_WDRBT BIT(2)
63 #define QSPI_MR_SMRM BIT(3)
64 #define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
65 #define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
66 #define QSPI_MR_CSMODE_LASTXFER (1 << 4)
67 #define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
68 #define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
69 #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
70 #define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
71 #define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
72 #define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
73 #define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
75 /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
76 #define QSPI_SR_RDRF BIT(0)
77 #define QSPI_SR_TDRE BIT(1)
78 #define QSPI_SR_TXEMPTY BIT(2)
79 #define QSPI_SR_OVRES BIT(3)
80 #define QSPI_SR_CSR BIT(8)
81 #define QSPI_SR_CSS BIT(9)
82 #define QSPI_SR_INSTRE BIT(10)
83 #define QSPI_SR_QSPIENS BIT(24)
85 #define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
87 /* Bitfields in QSPI_SCR (Serial Clock Register) */
88 #define QSPI_SCR_CPOL BIT(0)
89 #define QSPI_SCR_CPHA BIT(1)
90 #define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
91 #define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
92 #define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
93 #define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
95 /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
96 #define QSPI_ICR_INST_MASK GENMASK(7, 0)
97 #define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
98 #define QSPI_ICR_OPT_MASK GENMASK(23, 16)
99 #define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
101 /* Bitfields in QSPI_IFR (Instruction Frame Register) */
102 #define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
103 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
104 #define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
105 #define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
106 #define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
107 #define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
108 #define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
109 #define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
110 #define QSPI_IFR_INSTEN BIT(4)
111 #define QSPI_IFR_ADDREN BIT(5)
112 #define QSPI_IFR_OPTEN BIT(6)
113 #define QSPI_IFR_DATAEN BIT(7)
114 #define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
115 #define QSPI_IFR_OPTL_1BIT (0 << 8)
116 #define QSPI_IFR_OPTL_2BIT (1 << 8)
117 #define QSPI_IFR_OPTL_4BIT (2 << 8)
118 #define QSPI_IFR_OPTL_8BIT (3 << 8)
119 #define QSPI_IFR_ADDRL BIT(10)
120 #define QSPI_IFR_TFRTYP_MEM BIT(12)
121 #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
122 #define QSPI_IFR_CRM BIT(14)
123 #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
124 #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
125 #define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
127 /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
128 #define QSPI_SMR_SCREN BIT(0)
129 #define QSPI_SMR_RVDIS BIT(1)
131 /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
132 #define QSPI_WPMR_WPEN BIT(0)
133 #define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
134 #define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
136 /* Bitfields in QSPI_WPSR (Write Protection Status Register) */
137 #define QSPI_WPSR_WPVS BIT(0)
138 #define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
139 #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
141 struct atmel_qspi_caps {
149 const struct atmel_qspi_caps *caps;
154 struct atmel_qspi_mode {
161 static const struct atmel_qspi_mode atmel_qspi_modes[] = {
162 { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
163 { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
164 { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
165 { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
166 { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
167 { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
168 { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
171 static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
172 const struct atmel_qspi_mode *mode)
174 if (op->cmd.buswidth != mode->cmd_buswidth)
177 if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
180 if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
186 static int atmel_qspi_find_mode(const struct spi_mem_op *op)
190 for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
191 if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
197 static bool atmel_qspi_supports_op(struct spi_slave *slave,
198 const struct spi_mem_op *op)
200 if (atmel_qspi_find_mode(op) < 0)
203 /* special case not supported by hardware */
204 if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
205 op->dummy.nbytes == 0)
211 static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
212 const struct spi_mem_op *op, u32 *offset)
215 u32 dummy_cycles = 0;
219 icr = QSPI_ICR_INST(op->cmd.opcode);
220 ifr = QSPI_IFR_INSTEN;
222 mode = atmel_qspi_find_mode(op);
225 ifr |= atmel_qspi_modes[mode].config;
227 if (op->dummy.buswidth && op->dummy.nbytes)
228 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
231 * The controller allows 24 and 32-bit addressing while NAND-flash
232 * requires 16-bit long. Handling 8-bit long addresses is done using
233 * the option field. For the 16-bit addresses, the workaround depends
234 * of the number of requested dummy bits. If there are 8 or more dummy
235 * cycles, the address is shifted and sent with the first dummy byte.
236 * Otherwise opcode is disabled and the first byte of the address
237 * contains the command opcode (works only if the opcode and address
238 * use the same buswidth). The limitation is when the 16-bit address is
239 * used without enough dummy cycles and the opcode is using a different
240 * buswidth than the address.
242 if (op->addr.buswidth) {
243 switch (op->addr.nbytes) {
247 ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
248 icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
251 if (dummy_cycles < 8 / op->addr.buswidth) {
252 ifr &= ~QSPI_IFR_INSTEN;
253 ifr |= QSPI_IFR_ADDREN;
254 iar = (op->cmd.opcode << 16) |
255 (op->addr.val & 0xffff);
257 ifr |= QSPI_IFR_ADDREN;
258 iar = (op->addr.val << 8) & 0xffffff;
259 dummy_cycles -= 8 / op->addr.buswidth;
263 ifr |= QSPI_IFR_ADDREN;
264 iar = op->addr.val & 0xffffff;
267 ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
268 iar = op->addr.val & 0x7ffffff;
275 /* offset of the data access in the QSPI memory space */
278 /* Set number of dummy cycles */
280 ifr |= QSPI_IFR_NBDUM(dummy_cycles);
282 /* Set data enable */
284 ifr |= QSPI_IFR_DATAEN;
287 * If the QSPI controller is set in regular SPI mode, set it in
288 * Serial Memory Mode (SMM).
290 if (aq->mr != QSPI_MR_SMM) {
291 writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
292 aq->mr = QSPI_MR_SMM;
295 /* Clear pending interrupts */
296 (void)readl(aq->regs + QSPI_SR);
298 if (aq->caps->has_ricr) {
299 if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
300 ifr |= QSPI_IFR_APBTFRTYP_READ;
302 /* Set QSPI Instruction Frame registers */
303 writel(iar, aq->regs + QSPI_IAR);
304 if (op->data.dir == SPI_MEM_DATA_IN)
305 writel(icr, aq->regs + QSPI_RICR);
307 writel(icr, aq->regs + QSPI_WICR);
308 writel(ifr, aq->regs + QSPI_IFR);
310 if (op->data.dir == SPI_MEM_DATA_OUT)
311 ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
313 /* Set QSPI Instruction Frame registers */
314 writel(iar, aq->regs + QSPI_IAR);
315 writel(icr, aq->regs + QSPI_ICR);
316 writel(ifr, aq->regs + QSPI_IFR);
322 static int atmel_qspi_exec_op(struct spi_slave *slave,
323 const struct spi_mem_op *op)
325 struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
329 err = atmel_qspi_set_cfg(aq, op, &offset);
333 /* Skip to the final steps if there is no data */
334 if (op->data.nbytes) {
335 /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
336 (void)readl(aq->regs + QSPI_IFR);
338 /* Send/Receive data */
339 if (op->data.dir == SPI_MEM_DATA_IN)
340 memcpy_fromio(op->data.buf.in, aq->mem + offset,
343 memcpy_toio(aq->mem + offset, op->data.buf.out,
346 /* Release the chip-select */
347 writel(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
350 /* Poll INSTruction End and Chip Select Rise flags. */
351 imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
352 return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
356 static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
358 struct atmel_qspi *aq = dev_get_priv(bus);
359 u32 scr, scbr, mask, new_value;
361 /* Compute the QSPI baudrate */
362 scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
366 new_value = QSPI_SCR_SCBR(scbr);
367 mask = QSPI_SCR_SCBR_MASK;
369 scr = readl(aq->regs + QSPI_SCR);
370 if ((scr & mask) == new_value)
373 scr = (scr & ~mask) | new_value;
374 writel(scr, aq->regs + QSPI_SCR);
379 static int atmel_qspi_set_mode(struct udevice *bus, uint mode)
381 struct atmel_qspi *aq = dev_get_priv(bus);
382 u32 scr, mask, new_value = 0;
385 new_value = QSPI_SCR_CPOL;
387 new_value = QSPI_SCR_CPHA;
389 mask = QSPI_SCR_CPOL | QSPI_SCR_CPHA;
391 scr = readl(aq->regs + QSPI_SCR);
392 if ((scr & mask) == new_value)
395 scr = (scr & ~mask) | new_value;
396 writel(scr, aq->regs + QSPI_SCR);
401 static int atmel_qspi_enable_clk(struct udevice *dev)
403 struct atmel_qspi *aq = dev_get_priv(dev);
404 struct clk pclk, qspick;
407 ret = clk_get_by_name(dev, "pclk", &pclk);
409 ret = clk_get_by_index(dev, 0, &pclk);
412 dev_err(dev, "Missing QSPI peripheral clock\n");
416 ret = clk_enable(&pclk);
418 dev_err(dev, "Failed to enable QSPI peripheral clock\n");
422 if (aq->caps->has_qspick) {
423 /* Get the QSPI system clock */
424 ret = clk_get_by_name(dev, "qspick", &qspick);
426 dev_err(dev, "Missing QSPI peripheral clock\n");
430 ret = clk_enable(&qspick);
432 dev_err(dev, "Failed to enable QSPI system clock\n");
436 aq->bus_clk_rate = clk_get_rate(&pclk);
437 if (!aq->bus_clk_rate)
446 static void atmel_qspi_init(struct atmel_qspi *aq)
448 /* Reset the QSPI controller */
449 writel(QSPI_CR_SWRST, aq->regs + QSPI_CR);
451 /* Set the QSPI controller by default in Serial Memory Mode */
452 writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
453 aq->mr = QSPI_MR_SMM;
455 /* Enable the QSPI controller */
456 writel(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
459 static int atmel_qspi_probe(struct udevice *dev)
461 struct atmel_qspi *aq = dev_get_priv(dev);
465 aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
467 dev_err(dev, "Could not retrieve QSPI caps\n");
471 /* Map the registers */
472 ret = dev_read_resource_byname(dev, "qspi_base", &res);
474 dev_err(dev, "missing registers\n");
478 aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
479 if (IS_ERR(aq->regs))
480 return PTR_ERR(aq->regs);
482 /* Map the AHB memory */
483 ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
485 dev_err(dev, "missing AHB memory\n");
489 aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
491 return PTR_ERR(aq->mem);
493 ret = atmel_qspi_enable_clk(dev);
502 static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
503 .supports_op = atmel_qspi_supports_op,
504 .exec_op = atmel_qspi_exec_op,
507 static const struct dm_spi_ops atmel_qspi_ops = {
508 .set_speed = atmel_qspi_set_speed,
509 .set_mode = atmel_qspi_set_mode,
510 .mem_ops = &atmel_qspi_mem_ops,
513 static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
515 static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
520 static const struct udevice_id atmel_qspi_ids[] = {
522 .compatible = "atmel,sama5d2-qspi",
523 .data = (ulong)&atmel_sama5d2_qspi_caps,
526 .compatible = "microchip,sam9x60-qspi",
527 .data = (ulong)&atmel_sam9x60_qspi_caps,
532 U_BOOT_DRIVER(atmel_qspi) = {
533 .name = "atmel_qspi",
535 .of_match = atmel_qspi_ids,
536 .ops = &atmel_qspi_ops,
537 .priv_auto_alloc_size = sizeof(struct atmel_qspi),
538 .probe = atmel_qspi_probe,