1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Atmel QSPI Controller
5 * Copyright (C) 2015 Atmel Corporation
6 * Copyright (C) 2018 Cryptera A/S
8 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
9 * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
11 * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/interrupt.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
22 #include <linux/of_platform.h>
23 #include <linux/platform_device.h>
24 #include <linux/spi/spi-mem.h>
26 /* QSPI register offsets */
27 #define QSPI_CR 0x0000 /* Control Register */
28 #define QSPI_MR 0x0004 /* Mode Register */
29 #define QSPI_RD 0x0008 /* Receive Data Register */
30 #define QSPI_TD 0x000c /* Transmit Data Register */
31 #define QSPI_SR 0x0010 /* Status Register */
32 #define QSPI_IER 0x0014 /* Interrupt Enable Register */
33 #define QSPI_IDR 0x0018 /* Interrupt Disable Register */
34 #define QSPI_IMR 0x001c /* Interrupt Mask Register */
35 #define QSPI_SCR 0x0020 /* Serial Clock Register */
37 #define QSPI_IAR 0x0030 /* Instruction Address Register */
38 #define QSPI_ICR 0x0034 /* Instruction Code Register */
39 #define QSPI_WICR 0x0034 /* Write Instruction Code Register */
40 #define QSPI_IFR 0x0038 /* Instruction Frame Register */
41 #define QSPI_RICR 0x003C /* Read Instruction Code Register */
43 #define QSPI_SMR 0x0040 /* Scrambling Mode Register */
44 #define QSPI_SKR 0x0044 /* Scrambling Key Register */
46 #define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
47 #define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
49 #define QSPI_VERSION 0x00FC /* Version Register */
52 /* Bitfields in QSPI_CR (Control Register) */
53 #define QSPI_CR_QSPIEN BIT(0)
54 #define QSPI_CR_QSPIDIS BIT(1)
55 #define QSPI_CR_SWRST BIT(7)
56 #define QSPI_CR_LASTXFER BIT(24)
58 /* Bitfields in QSPI_MR (Mode Register) */
59 #define QSPI_MR_SMM BIT(0)
60 #define QSPI_MR_LLB BIT(1)
61 #define QSPI_MR_WDRBT BIT(2)
62 #define QSPI_MR_SMRM BIT(3)
63 #define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
64 #define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
65 #define QSPI_MR_CSMODE_LASTXFER (1 << 4)
66 #define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
67 #define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
68 #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
69 #define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
70 #define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
71 #define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
72 #define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
74 /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
75 #define QSPI_SR_RDRF BIT(0)
76 #define QSPI_SR_TDRE BIT(1)
77 #define QSPI_SR_TXEMPTY BIT(2)
78 #define QSPI_SR_OVRES BIT(3)
79 #define QSPI_SR_CSR BIT(8)
80 #define QSPI_SR_CSS BIT(9)
81 #define QSPI_SR_INSTRE BIT(10)
82 #define QSPI_SR_QSPIENS BIT(24)
84 #define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
86 /* Bitfields in QSPI_SCR (Serial Clock Register) */
87 #define QSPI_SCR_CPOL BIT(0)
88 #define QSPI_SCR_CPHA BIT(1)
89 #define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
90 #define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
91 #define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
92 #define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
94 /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
95 #define QSPI_ICR_INST_MASK GENMASK(7, 0)
96 #define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
97 #define QSPI_ICR_OPT_MASK GENMASK(23, 16)
98 #define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
100 /* Bitfields in QSPI_IFR (Instruction Frame Register) */
101 #define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
102 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
103 #define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
104 #define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
105 #define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
106 #define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
107 #define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
108 #define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
109 #define QSPI_IFR_INSTEN BIT(4)
110 #define QSPI_IFR_ADDREN BIT(5)
111 #define QSPI_IFR_OPTEN BIT(6)
112 #define QSPI_IFR_DATAEN BIT(7)
113 #define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
114 #define QSPI_IFR_OPTL_1BIT (0 << 8)
115 #define QSPI_IFR_OPTL_2BIT (1 << 8)
116 #define QSPI_IFR_OPTL_4BIT (2 << 8)
117 #define QSPI_IFR_OPTL_8BIT (3 << 8)
118 #define QSPI_IFR_ADDRL BIT(10)
119 #define QSPI_IFR_TFRTYP_MEM BIT(12)
120 #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
121 #define QSPI_IFR_CRM BIT(14)
122 #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
123 #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
124 #define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
126 /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
127 #define QSPI_SMR_SCREN BIT(0)
128 #define QSPI_SMR_RVDIS BIT(1)
130 /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
131 #define QSPI_WPMR_WPEN BIT(0)
132 #define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
133 #define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
135 /* Bitfields in QSPI_WPSR (Write Protection Status Register) */
136 #define QSPI_WPSR_WPVS BIT(0)
137 #define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
138 #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
140 struct atmel_qspi_caps {
150 struct platform_device *pdev;
151 const struct atmel_qspi_caps *caps;
155 struct completion cmd_completion;
158 struct atmel_qspi_mode {
165 static const struct atmel_qspi_mode atmel_qspi_modes[] = {
166 { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
167 { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
168 { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
169 { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
170 { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
171 { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
172 { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
175 static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
176 const struct atmel_qspi_mode *mode)
178 if (op->cmd.buswidth != mode->cmd_buswidth)
181 if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
184 if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
190 static int atmel_qspi_find_mode(const struct spi_mem_op *op)
194 for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
195 if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
201 static bool atmel_qspi_supports_op(struct spi_mem *mem,
202 const struct spi_mem_op *op)
204 if (atmel_qspi_find_mode(op) < 0)
207 /* special case not supported by hardware */
208 if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
209 op->dummy.nbytes == 0)
215 static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
216 const struct spi_mem_op *op, u32 *offset)
219 u32 dummy_cycles = 0;
223 icr = QSPI_ICR_INST(op->cmd.opcode);
224 ifr = QSPI_IFR_INSTEN;
226 mode = atmel_qspi_find_mode(op);
229 ifr |= atmel_qspi_modes[mode].config;
231 if (op->dummy.buswidth && op->dummy.nbytes)
232 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
235 * The controller allows 24 and 32-bit addressing while NAND-flash
236 * requires 16-bit long. Handling 8-bit long addresses is done using
237 * the option field. For the 16-bit addresses, the workaround depends
238 * of the number of requested dummy bits. If there are 8 or more dummy
239 * cycles, the address is shifted and sent with the first dummy byte.
240 * Otherwise opcode is disabled and the first byte of the address
241 * contains the command opcode (works only if the opcode and address
242 * use the same buswidth). The limitation is when the 16-bit address is
243 * used without enough dummy cycles and the opcode is using a different
244 * buswidth than the address.
246 if (op->addr.buswidth) {
247 switch (op->addr.nbytes) {
251 ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
252 icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
255 if (dummy_cycles < 8 / op->addr.buswidth) {
256 ifr &= ~QSPI_IFR_INSTEN;
257 ifr |= QSPI_IFR_ADDREN;
258 iar = (op->cmd.opcode << 16) |
259 (op->addr.val & 0xffff);
261 ifr |= QSPI_IFR_ADDREN;
262 iar = (op->addr.val << 8) & 0xffffff;
263 dummy_cycles -= 8 / op->addr.buswidth;
267 ifr |= QSPI_IFR_ADDREN;
268 iar = op->addr.val & 0xffffff;
271 ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
272 iar = op->addr.val & 0x7ffffff;
279 /* offset of the data access in the QSPI memory space */
282 /* Set number of dummy cycles */
284 ifr |= QSPI_IFR_NBDUM(dummy_cycles);
286 /* Set data enable */
288 ifr |= QSPI_IFR_DATAEN;
291 * If the QSPI controller is set in regular SPI mode, set it in
292 * Serial Memory Mode (SMM).
294 if (aq->mr != QSPI_MR_SMM) {
295 writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
296 aq->mr = QSPI_MR_SMM;
299 /* Clear pending interrupts */
300 (void)readl_relaxed(aq->regs + QSPI_SR);
302 if (aq->caps->has_ricr) {
303 if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
304 ifr |= QSPI_IFR_APBTFRTYP_READ;
306 /* Set QSPI Instruction Frame registers */
307 writel_relaxed(iar, aq->regs + QSPI_IAR);
308 if (op->data.dir == SPI_MEM_DATA_IN)
309 writel_relaxed(icr, aq->regs + QSPI_RICR);
311 writel_relaxed(icr, aq->regs + QSPI_WICR);
312 writel_relaxed(ifr, aq->regs + QSPI_IFR);
314 if (op->data.dir == SPI_MEM_DATA_OUT)
315 ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
317 /* Set QSPI Instruction Frame registers */
318 writel_relaxed(iar, aq->regs + QSPI_IAR);
319 writel_relaxed(icr, aq->regs + QSPI_ICR);
320 writel_relaxed(ifr, aq->regs + QSPI_IFR);
326 static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
328 struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master);
332 err = atmel_qspi_set_cfg(aq, op, &offset);
336 /* Skip to the final steps if there is no data */
337 if (op->data.nbytes) {
338 /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
339 (void)readl_relaxed(aq->regs + QSPI_IFR);
341 /* Send/Receive data */
342 if (op->data.dir == SPI_MEM_DATA_IN)
343 _memcpy_fromio(op->data.buf.in, aq->mem + offset,
346 _memcpy_toio(aq->mem + offset, op->data.buf.out,
349 /* Release the chip-select */
350 writel_relaxed(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
353 /* Poll INSTRuction End status */
354 sr = readl_relaxed(aq->regs + QSPI_SR);
355 if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
358 /* Wait for INSTRuction End interrupt */
359 reinit_completion(&aq->cmd_completion);
360 aq->pending = sr & QSPI_SR_CMD_COMPLETED;
361 writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IER);
362 if (!wait_for_completion_timeout(&aq->cmd_completion,
363 msecs_to_jiffies(1000)))
365 writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IDR);
370 static const char *atmel_qspi_get_name(struct spi_mem *spimem)
372 return dev_name(spimem->spi->dev.parent);
375 static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
376 .supports_op = atmel_qspi_supports_op,
377 .exec_op = atmel_qspi_exec_op,
378 .get_name = atmel_qspi_get_name
381 static int atmel_qspi_setup(struct spi_device *spi)
383 struct spi_controller *ctrl = spi->master;
384 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
385 unsigned long src_rate;
391 if (!spi->max_speed_hz)
394 src_rate = clk_get_rate(aq->pclk);
398 /* Compute the QSPI baudrate */
399 scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz);
403 aq->scr = QSPI_SCR_SCBR(scbr);
404 writel_relaxed(aq->scr, aq->regs + QSPI_SCR);
409 static void atmel_qspi_init(struct atmel_qspi *aq)
411 /* Reset the QSPI controller */
412 writel_relaxed(QSPI_CR_SWRST, aq->regs + QSPI_CR);
414 /* Set the QSPI controller by default in Serial Memory Mode */
415 writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
416 aq->mr = QSPI_MR_SMM;
418 /* Enable the QSPI controller */
419 writel_relaxed(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
422 static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
424 struct atmel_qspi *aq = dev_id;
425 u32 status, mask, pending;
427 status = readl_relaxed(aq->regs + QSPI_SR);
428 mask = readl_relaxed(aq->regs + QSPI_IMR);
429 pending = status & mask;
434 aq->pending |= pending;
435 if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
436 complete(&aq->cmd_completion);
441 static int atmel_qspi_probe(struct platform_device *pdev)
443 struct spi_controller *ctrl;
444 struct atmel_qspi *aq;
445 struct resource *res;
448 ctrl = spi_alloc_master(&pdev->dev, sizeof(*aq));
452 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
453 ctrl->setup = atmel_qspi_setup;
455 ctrl->mem_ops = &atmel_qspi_mem_ops;
456 ctrl->num_chipselect = 1;
457 ctrl->dev.of_node = pdev->dev.of_node;
458 platform_set_drvdata(pdev, ctrl);
460 aq = spi_controller_get_devdata(ctrl);
462 init_completion(&aq->cmd_completion);
465 /* Map the registers */
466 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
467 aq->regs = devm_ioremap_resource(&pdev->dev, res);
468 if (IS_ERR(aq->regs)) {
469 dev_err(&pdev->dev, "missing registers\n");
470 err = PTR_ERR(aq->regs);
474 /* Map the AHB memory */
475 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
476 aq->mem = devm_ioremap_resource(&pdev->dev, res);
477 if (IS_ERR(aq->mem)) {
478 dev_err(&pdev->dev, "missing AHB memory\n");
479 err = PTR_ERR(aq->mem);
483 /* Get the peripheral clock */
484 aq->pclk = devm_clk_get(&pdev->dev, "pclk");
485 if (IS_ERR(aq->pclk))
486 aq->pclk = devm_clk_get(&pdev->dev, NULL);
488 if (IS_ERR(aq->pclk)) {
489 dev_err(&pdev->dev, "missing peripheral clock\n");
490 err = PTR_ERR(aq->pclk);
494 /* Enable the peripheral clock */
495 err = clk_prepare_enable(aq->pclk);
497 dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
501 aq->caps = of_device_get_match_data(&pdev->dev);
503 dev_err(&pdev->dev, "Could not retrieve QSPI caps\n");
508 if (aq->caps->has_qspick) {
509 /* Get the QSPI system clock */
510 aq->qspick = devm_clk_get(&pdev->dev, "qspick");
511 if (IS_ERR(aq->qspick)) {
512 dev_err(&pdev->dev, "missing system clock\n");
513 err = PTR_ERR(aq->qspick);
517 /* Enable the QSPI system clock */
518 err = clk_prepare_enable(aq->qspick);
521 "failed to enable the QSPI system clock\n");
526 /* Request the IRQ */
527 irq = platform_get_irq(pdev, 0);
529 dev_err(&pdev->dev, "missing IRQ\n");
533 err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
534 0, dev_name(&pdev->dev), aq);
540 err = spi_register_controller(ctrl);
547 clk_disable_unprepare(aq->qspick);
549 clk_disable_unprepare(aq->pclk);
551 spi_controller_put(ctrl);
556 static int atmel_qspi_remove(struct platform_device *pdev)
558 struct spi_controller *ctrl = platform_get_drvdata(pdev);
559 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
561 spi_unregister_controller(ctrl);
562 writel_relaxed(QSPI_CR_QSPIDIS, aq->regs + QSPI_CR);
563 clk_disable_unprepare(aq->qspick);
564 clk_disable_unprepare(aq->pclk);
568 static int __maybe_unused atmel_qspi_suspend(struct device *dev)
570 struct spi_controller *ctrl = dev_get_drvdata(dev);
571 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
573 clk_disable_unprepare(aq->qspick);
574 clk_disable_unprepare(aq->pclk);
579 static int __maybe_unused atmel_qspi_resume(struct device *dev)
581 struct spi_controller *ctrl = dev_get_drvdata(dev);
582 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
584 clk_prepare_enable(aq->pclk);
585 clk_prepare_enable(aq->qspick);
589 writel_relaxed(aq->scr, aq->regs + QSPI_SCR);
594 static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend,
597 static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
599 static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
604 static const struct of_device_id atmel_qspi_dt_ids[] = {
606 .compatible = "atmel,sama5d2-qspi",
607 .data = &atmel_sama5d2_qspi_caps,
610 .compatible = "microchip,sam9x60-qspi",
611 .data = &atmel_sam9x60_qspi_caps,
616 MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);
618 static struct platform_driver atmel_qspi_driver = {
620 .name = "atmel_qspi",
621 .of_match_table = atmel_qspi_dt_ids,
622 .pm = &atmel_qspi_pm_ops,
624 .probe = atmel_qspi_probe,
625 .remove = atmel_qspi_remove,
627 module_platform_driver(atmel_qspi_driver);
629 MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
630 MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com");
631 MODULE_DESCRIPTION("Atmel QSPI Controller driver");
632 MODULE_LICENSE("GPL v2");