1 // SPDX-License-Identifier: GPL-2.0+
3 * Andestech ATCSPI200 SPI controller driver.
5 * Copyright 2017 Andes Technology, Inc.
6 * Author: Rick Chen (rick@andestech.com)
17 DECLARE_GLOBAL_DATA_PTR;
19 #define MAX_TRANSFER_LEN 512
21 #define SPI_TIMEOUT 0x100000
24 #define SPI0_BASE 0xf0b00000
25 #define SPI1_BASE 0xf0f00000
26 #define NSPI_MAX_CS_NUM 1
28 struct atcspi200_spi_regs {
31 u32 format; /* 0x10 */
32 #define DATA_LENGTH(x) ((x-1)<<8)
36 #define TRAMODE_OFFSET 24
37 #define TRAMODE_MASK (0x0F<<TRAMODE_OFFSET)
38 #define TRAMODE_WR_SYNC (0<<TRAMODE_OFFSET)
39 #define TRAMODE_WO (1<<TRAMODE_OFFSET)
40 #define TRAMODE_RO (2<<TRAMODE_OFFSET)
41 #define TRAMODE_WR (3<<TRAMODE_OFFSET)
42 #define TRAMODE_RW (4<<TRAMODE_OFFSET)
43 #define TRAMODE_WDR (5<<TRAMODE_OFFSET)
44 #define TRAMODE_RDW (6<<TRAMODE_OFFSET)
45 #define TRAMODE_NONE (7<<TRAMODE_OFFSET)
46 #define TRAMODE_DW (8<<TRAMODE_OFFSET)
47 #define TRAMODE_DR (9<<TRAMODE_OFFSET)
48 #define WCNT_OFFSET 12
49 #define WCNT_MASK (0x1FF<<WCNT_OFFSET)
51 #define RCNT_MASK (0x1FF<<RCNT_OFFSET)
56 #define TXFTH_OFFSET 16
57 #define RXFTH_OFFSET 8
58 #define TXDMAEN (1<<4)
59 #define RXDMAEN (1<<3)
65 #define TXEPTY (1<<22)
66 #define TXFVE_MASK (0x1F<<16)
68 #define RXFVE_OFFSET (8)
69 #define RXFVE_MASK (0x1F<<RXFVE_OFFSET)
73 u32 timing; /* 0x40 */
74 #define SCLK_DIV_MASK 0xFF
77 struct nds_spi_slave {
78 volatile struct atcspi200_spi_regs *regs;
91 unsigned int max_transfer_length;
94 static int __atcspi200_spi_set_speed(struct nds_spi_slave *ns)
98 tm = ns->regs->timing;
101 if(ns->freq >= ns->clock)
104 for (div = 0; div < 0xff; div++) {
105 if (ns->freq >= ns->clock / (2 * (div + 1)))
111 ns->regs->timing = tm;
117 static int __atcspi200_spi_claim_bus(struct nds_spi_slave *ns)
119 unsigned int format=0;
120 ns->regs->ctrl |= (TXFRST|RXFRST|SPIRST);
121 while((ns->regs->ctrl &(TXFRST|RXFRST|SPIRST))&&(ns->to--))
126 format = ns->mode|DATA_LENGTH(8);
127 ns->regs->format = format;
128 __atcspi200_spi_set_speed(ns);
133 static int __atcspi200_spi_release_bus(struct nds_spi_slave *ns)
139 static int __atcspi200_spi_start(struct nds_spi_slave *ns)
142 int tc = ns->regs->tctrl;
144 tc &= ~(WCNT_MASK|RCNT_MASK|TRAMODE_MASK);
145 if ((ns->din)&&(ns->cmd_len))
154 tc |= (ns->cmd_len+olen-1) << WCNT_OFFSET;
157 tc |= (ns->tran_len-1) << RCNT_OFFSET;
159 ns->regs->tctrl = tc;
162 for (i=0;i<ns->cmd_len;i++)
163 ns->regs->data = ns->cmd_buf[i];
168 static int __atcspi200_spi_stop(struct nds_spi_slave *ns)
170 ns->regs->timing = ns->mtiming;
171 while ((ns->regs->status & SPIBSY)&&(ns->to--))
178 static void __nspi_espi_tx(struct nds_spi_slave *ns, const void *dout)
180 ns->regs->data = *(u8 *)dout;
183 static int __nspi_espi_rx(struct nds_spi_slave *ns, void *din, unsigned int bytes)
185 *(u8 *)din = ns->regs->data;
190 static int __atcspi200_spi_xfer(struct nds_spi_slave *ns,
191 unsigned int bitlen, const void *data_out, void *data_in,
194 unsigned int event, rx_bytes;
195 const void *dout = NULL;
197 int num_blks, num_chunks, max_tran_len, tran_len;
199 u8 *cmd_buf = ns->cmd_buf;
200 size_t cmd_len = ns->cmd_len;
201 unsigned long data_len = bitlen / 8;
205 max_tran_len = ns->max_transfer_length;
208 cmd_len = ns->cmd_len = data_len;
209 memcpy(cmd_buf, data_out, cmd_len);
217 ns->data_len = data_len;
218 ns->din = (u8 *)data_in;
219 ns->dout = (u8 *)data_out;
222 case SPI_XFER_BEGIN | SPI_XFER_END:
226 cmd_len = ns->cmd_len = data_len;
227 memcpy(cmd_buf, data_out, cmd_len);
230 __atcspi200_spi_start(ns);
234 debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) data_len %lu\n",
235 *(uint *)data_out, data_out, *(uint *)data_in,
237 num_chunks = DIV_ROUND_UP(data_len, max_tran_len);
240 while (num_chunks--) {
241 tran_len = min((size_t)data_len, (size_t)max_tran_len);
242 ns->tran_len = tran_len;
243 num_blks = DIV_ROUND_UP(tran_len , CHUNK_SIZE);
244 num_bytes = (tran_len) % CHUNK_SIZE;
246 num_bytes = CHUNK_SIZE;
247 __atcspi200_spi_start(ns);
250 event = in_le32(&ns->regs->status);
251 if ((event & TXEPTY) && (data_out)) {
252 __nspi_espi_tx(ns, dout);
253 num_blks -= CHUNK_SIZE;
257 if ((event & RXFVE_MASK) && (data_in)) {
258 rf_cnt = ((event & RXFVE_MASK)>> RXFVE_OFFSET);
259 if (rf_cnt >= CHUNK_SIZE)
260 rx_bytes = CHUNK_SIZE;
261 else if (num_blks == 1 && rf_cnt == num_bytes)
262 rx_bytes = num_bytes;
266 if (__nspi_espi_rx(ns, din, rx_bytes) == rx_bytes) {
267 num_blks -= CHUNK_SIZE;
268 din = (unsigned char *)din + rx_bytes;
273 data_len -= tran_len;
276 ns->cmd_buf[1] += ((tran_len>>16)&0xff);
277 ns->cmd_buf[2] += ((tran_len>>8)&0xff);
278 ns->cmd_buf[3] += ((tran_len)&0xff);
279 ns->data_len = data_len;
281 ret = __atcspi200_spi_stop(ns);
283 ret = __atcspi200_spi_stop(ns);
288 static int atcspi200_spi_set_speed(struct udevice *bus, uint max_hz)
290 struct nds_spi_slave *ns = dev_get_priv(bus);
292 debug("%s speed %u\n", __func__, max_hz);
295 __atcspi200_spi_set_speed(ns);
300 static int atcspi200_spi_set_mode(struct udevice *bus, uint mode)
302 struct nds_spi_slave *ns = dev_get_priv(bus);
304 debug("%s mode %u\n", __func__, mode);
310 static int atcspi200_spi_claim_bus(struct udevice *dev)
312 struct dm_spi_slave_platdata *slave_plat =
313 dev_get_parent_plat(dev);
314 struct udevice *bus = dev->parent;
315 struct nds_spi_slave *ns = dev_get_priv(bus);
317 if (slave_plat->cs >= ns->num_cs) {
318 printf("Invalid SPI chipselect\n");
322 return __atcspi200_spi_claim_bus(ns);
325 static int atcspi200_spi_release_bus(struct udevice *dev)
327 struct nds_spi_slave *ns = dev_get_priv(dev->parent);
329 return __atcspi200_spi_release_bus(ns);
332 static int atcspi200_spi_xfer(struct udevice *dev, unsigned int bitlen,
333 const void *dout, void *din,
336 struct udevice *bus = dev->parent;
337 struct nds_spi_slave *ns = dev_get_priv(bus);
339 return __atcspi200_spi_xfer(ns, bitlen, dout, din, flags);
342 static int atcspi200_spi_get_clk(struct udevice *bus)
344 struct nds_spi_slave *ns = dev_get_priv(bus);
349 ret = clk_get_by_index(bus, 0, &clk);
353 clk_rate = clk_get_rate(&clk);
357 ns->clock = clk_rate;
363 static int atcspi200_spi_probe(struct udevice *bus)
365 struct nds_spi_slave *ns = dev_get_priv(bus);
367 ns->to = SPI_TIMEOUT;
368 ns->max_transfer_length = MAX_TRANSFER_LEN;
369 ns->mtiming = ns->regs->timing;
370 atcspi200_spi_get_clk(bus);
375 static int atcspi200_ofdata_to_platadata(struct udevice *bus)
377 struct nds_spi_slave *ns = dev_get_priv(bus);
378 const void *blob = gd->fdt_blob;
379 int node = dev_of_offset(bus);
381 ns->regs = map_physmem(dev_read_addr(bus),
382 sizeof(struct atcspi200_spi_regs),
385 printf("%s: could not map device address\n", __func__);
388 ns->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
393 static const struct dm_spi_ops atcspi200_spi_ops = {
394 .claim_bus = atcspi200_spi_claim_bus,
395 .release_bus = atcspi200_spi_release_bus,
396 .xfer = atcspi200_spi_xfer,
397 .set_speed = atcspi200_spi_set_speed,
398 .set_mode = atcspi200_spi_set_mode,
401 static const struct udevice_id atcspi200_spi_ids[] = {
402 { .compatible = "andestech,atcspi200" },
406 U_BOOT_DRIVER(atcspi200_spi) = {
407 .name = "atcspi200_spi",
409 .of_match = atcspi200_spi_ids,
410 .ops = &atcspi200_spi_ops,
411 .ofdata_to_platdata = atcspi200_ofdata_to_platadata,
412 .priv_auto = sizeof(struct nds_spi_slave),
413 .probe = atcspi200_spi_probe,