1 // SPDX-License-Identifier: GPL-2.0+
3 * Andestech ATCSPI200 SPI controller driver.
5 * Copyright 2017 Andes Technology, Inc.
6 * Author: Rick Chen (rick@andestech.com)
14 #include <asm/global_data.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 #define MAX_TRANSFER_LEN 512
22 #define SPI_TIMEOUT 0x100000
25 #define SPI0_BASE 0xf0b00000
26 #define SPI1_BASE 0xf0f00000
27 #define NSPI_MAX_CS_NUM 1
29 struct atcspi200_spi_regs {
32 u32 format; /* 0x10 */
33 #define DATA_LENGTH(x) ((x-1)<<8)
37 #define TRAMODE_OFFSET 24
38 #define TRAMODE_MASK (0x0F<<TRAMODE_OFFSET)
39 #define TRAMODE_WR_SYNC (0<<TRAMODE_OFFSET)
40 #define TRAMODE_WO (1<<TRAMODE_OFFSET)
41 #define TRAMODE_RO (2<<TRAMODE_OFFSET)
42 #define TRAMODE_WR (3<<TRAMODE_OFFSET)
43 #define TRAMODE_RW (4<<TRAMODE_OFFSET)
44 #define TRAMODE_WDR (5<<TRAMODE_OFFSET)
45 #define TRAMODE_RDW (6<<TRAMODE_OFFSET)
46 #define TRAMODE_NONE (7<<TRAMODE_OFFSET)
47 #define TRAMODE_DW (8<<TRAMODE_OFFSET)
48 #define TRAMODE_DR (9<<TRAMODE_OFFSET)
49 #define WCNT_OFFSET 12
50 #define WCNT_MASK (0x1FF<<WCNT_OFFSET)
52 #define RCNT_MASK (0x1FF<<RCNT_OFFSET)
57 #define TXFTH_OFFSET 16
58 #define RXFTH_OFFSET 8
59 #define TXDMAEN (1<<4)
60 #define RXDMAEN (1<<3)
66 #define TXEPTY (1<<22)
67 #define TXFVE_MASK (0x1F<<16)
69 #define RXFVE_OFFSET (8)
70 #define RXFVE_MASK (0x1F<<RXFVE_OFFSET)
74 u32 timing; /* 0x40 */
75 #define SCLK_DIV_MASK 0xFF
78 struct nds_spi_slave {
79 volatile struct atcspi200_spi_regs *regs;
92 unsigned int max_transfer_length;
95 static int __atcspi200_spi_set_speed(struct nds_spi_slave *ns)
99 tm = ns->regs->timing;
100 tm &= ~SCLK_DIV_MASK;
102 if(ns->freq >= ns->clock)
105 for (div = 0; div < 0xff; div++) {
106 if (ns->freq >= ns->clock / (2 * (div + 1)))
112 ns->regs->timing = tm;
118 static int __atcspi200_spi_claim_bus(struct nds_spi_slave *ns)
120 unsigned int format=0;
121 ns->regs->ctrl |= (TXFRST|RXFRST|SPIRST);
122 while((ns->regs->ctrl &(TXFRST|RXFRST|SPIRST))&&(ns->to--))
127 format = ns->mode|DATA_LENGTH(8);
128 ns->regs->format = format;
129 __atcspi200_spi_set_speed(ns);
134 static int __atcspi200_spi_release_bus(struct nds_spi_slave *ns)
140 static int __atcspi200_spi_start(struct nds_spi_slave *ns)
143 int tc = ns->regs->tctrl;
145 tc &= ~(WCNT_MASK|RCNT_MASK|TRAMODE_MASK);
146 if ((ns->din)&&(ns->cmd_len))
155 tc |= (ns->cmd_len+olen-1) << WCNT_OFFSET;
158 tc |= (ns->tran_len-1) << RCNT_OFFSET;
160 ns->regs->tctrl = tc;
163 for (i=0;i<ns->cmd_len;i++)
164 ns->regs->data = ns->cmd_buf[i];
169 static int __atcspi200_spi_stop(struct nds_spi_slave *ns)
171 ns->regs->timing = ns->mtiming;
172 while ((ns->regs->status & SPIBSY)&&(ns->to--))
179 static void __nspi_espi_tx(struct nds_spi_slave *ns, const void *dout)
181 ns->regs->data = *(u8 *)dout;
184 static int __nspi_espi_rx(struct nds_spi_slave *ns, void *din, unsigned int bytes)
186 *(u8 *)din = ns->regs->data;
191 static int __atcspi200_spi_xfer(struct nds_spi_slave *ns,
192 unsigned int bitlen, const void *data_out, void *data_in,
195 unsigned int event, rx_bytes;
196 const void *dout = NULL;
198 int num_blks, num_chunks, max_tran_len, tran_len;
200 u8 *cmd_buf = ns->cmd_buf;
201 size_t cmd_len = ns->cmd_len;
202 unsigned long data_len = bitlen / 8;
204 int ret = 0, timeout = 0;
206 max_tran_len = ns->max_transfer_length;
209 cmd_len = ns->cmd_len = data_len;
210 memcpy(cmd_buf, data_out, cmd_len);
218 ns->data_len = data_len;
219 ns->din = (u8 *)data_in;
220 ns->dout = (u8 *)data_out;
223 case SPI_XFER_BEGIN | SPI_XFER_END:
227 cmd_len = ns->cmd_len = data_len;
228 memcpy(cmd_buf, data_out, cmd_len);
231 __atcspi200_spi_start(ns);
235 debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) data_len %lu\n",
236 *(uint *)data_out, data_out, *(uint *)data_in,
238 num_chunks = DIV_ROUND_UP(data_len, max_tran_len);
241 while (num_chunks--) {
242 tran_len = min((size_t)data_len, (size_t)max_tran_len);
243 ns->tran_len = tran_len;
244 num_blks = DIV_ROUND_UP(tran_len , CHUNK_SIZE);
245 num_bytes = (tran_len) % CHUNK_SIZE;
246 timeout = SPI_TIMEOUT;
248 num_bytes = CHUNK_SIZE;
249 __atcspi200_spi_start(ns);
251 while (num_blks && (timeout--)) {
252 event = in_le32(&ns->regs->status);
253 if ((event & TXEPTY) && (data_out)) {
254 __nspi_espi_tx(ns, dout);
255 num_blks -= CHUNK_SIZE;
259 if ((event & RXFVE_MASK) && (data_in)) {
260 rf_cnt = ((event & RXFVE_MASK)>> RXFVE_OFFSET);
261 if (rf_cnt >= CHUNK_SIZE)
262 rx_bytes = CHUNK_SIZE;
263 else if (num_blks == 1 && rf_cnt == num_bytes)
264 rx_bytes = num_bytes;
268 if (__nspi_espi_rx(ns, din, rx_bytes) == rx_bytes) {
269 num_blks -= CHUNK_SIZE;
270 din = (unsigned char *)din + rx_bytes;
275 debug("spi_xfer: %s() timeout\n", __func__);
280 data_len -= tran_len;
283 ns->cmd_buf[1] += ((tran_len>>16)&0xff);
284 ns->cmd_buf[2] += ((tran_len>>8)&0xff);
285 ns->cmd_buf[3] += ((tran_len)&0xff);
286 ns->data_len = data_len;
288 ret = __atcspi200_spi_stop(ns);
290 ret = __atcspi200_spi_stop(ns);
295 static int atcspi200_spi_set_speed(struct udevice *bus, uint max_hz)
297 struct nds_spi_slave *ns = dev_get_priv(bus);
299 debug("%s speed %u\n", __func__, max_hz);
302 __atcspi200_spi_set_speed(ns);
307 static int atcspi200_spi_set_mode(struct udevice *bus, uint mode)
309 struct nds_spi_slave *ns = dev_get_priv(bus);
311 debug("%s mode %u\n", __func__, mode);
317 static int atcspi200_spi_claim_bus(struct udevice *dev)
319 struct dm_spi_slave_plat *slave_plat =
320 dev_get_parent_plat(dev);
321 struct udevice *bus = dev->parent;
322 struct nds_spi_slave *ns = dev_get_priv(bus);
324 if (slave_plat->cs >= ns->num_cs) {
325 printf("Invalid SPI chipselect\n");
329 return __atcspi200_spi_claim_bus(ns);
332 static int atcspi200_spi_release_bus(struct udevice *dev)
334 struct nds_spi_slave *ns = dev_get_priv(dev->parent);
336 return __atcspi200_spi_release_bus(ns);
339 static int atcspi200_spi_xfer(struct udevice *dev, unsigned int bitlen,
340 const void *dout, void *din,
343 struct udevice *bus = dev->parent;
344 struct nds_spi_slave *ns = dev_get_priv(bus);
346 return __atcspi200_spi_xfer(ns, bitlen, dout, din, flags);
349 static int atcspi200_spi_get_clk(struct udevice *bus)
351 struct nds_spi_slave *ns = dev_get_priv(bus);
356 ret = clk_get_by_index(bus, 0, &clk);
360 clk_rate = clk_get_rate(&clk);
364 ns->clock = clk_rate;
370 static int atcspi200_spi_probe(struct udevice *bus)
372 struct nds_spi_slave *ns = dev_get_priv(bus);
374 ns->to = SPI_TIMEOUT;
375 ns->max_transfer_length = MAX_TRANSFER_LEN;
376 ns->mtiming = ns->regs->timing;
377 atcspi200_spi_get_clk(bus);
382 static int atcspi200_ofdata_to_platadata(struct udevice *bus)
384 struct nds_spi_slave *ns = dev_get_priv(bus);
385 const void *blob = gd->fdt_blob;
386 int node = dev_of_offset(bus);
388 ns->regs = map_physmem(dev_read_addr(bus),
389 sizeof(struct atcspi200_spi_regs),
392 printf("%s: could not map device address\n", __func__);
395 ns->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
400 static const struct dm_spi_ops atcspi200_spi_ops = {
401 .claim_bus = atcspi200_spi_claim_bus,
402 .release_bus = atcspi200_spi_release_bus,
403 .xfer = atcspi200_spi_xfer,
404 .set_speed = atcspi200_spi_set_speed,
405 .set_mode = atcspi200_spi_set_mode,
408 static const struct udevice_id atcspi200_spi_ids[] = {
409 { .compatible = "andestech,atcspi200" },
413 U_BOOT_DRIVER(atcspi200_spi) = {
414 .name = "atcspi200_spi",
416 .of_match = atcspi200_spi_ids,
417 .ops = &atcspi200_spi_ops,
418 .of_to_plat = atcspi200_ofdata_to_platadata,
419 .priv_auto = sizeof(struct nds_spi_slave),
420 .probe = atcspi200_spi_probe,