2 * drivers/spi/amba-pl022.c
4 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
6 * Copyright (C) 2008-2009 ST-Ericsson AB
7 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
11 * Initial version inspired by:
12 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
13 * Initial adoption to PL022 by:
14 * Sachin Verma <sachin.verma@st.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/device.h>
30 #include <linux/ioport.h>
31 #include <linux/errno.h>
32 #include <linux/interrupt.h>
33 #include <linux/spi/spi.h>
34 #include <linux/workqueue.h>
35 #include <linux/delay.h>
36 #include <linux/clk.h>
37 #include <linux/err.h>
38 #include <linux/amba/bus.h>
39 #include <linux/amba/pl022.h>
41 #include <linux/slab.h>
42 #include <linux/dmaengine.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/scatterlist.h>
47 * This macro is used to define some register default values.
48 * reg is masked with mask, the OR:ed with an (again masked)
49 * val shifted sb steps to the left.
51 #define SSP_WRITE_BITS(reg, val, mask, sb) \
52 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
55 * This macro is also used to define some default values.
56 * It will just shift val by sb steps to the left and mask
57 * the result with mask.
59 #define GEN_MASK_BITS(val, mask, sb) \
60 (((val)<<(sb)) & (mask))
63 #define DO_NOT_DRIVE_TX 1
65 #define DO_NOT_QUEUE_DMA 0
72 * Macros to access SSP Registers with their offsets
74 #define SSP_CR0(r) (r + 0x000)
75 #define SSP_CR1(r) (r + 0x004)
76 #define SSP_DR(r) (r + 0x008)
77 #define SSP_SR(r) (r + 0x00C)
78 #define SSP_CPSR(r) (r + 0x010)
79 #define SSP_IMSC(r) (r + 0x014)
80 #define SSP_RIS(r) (r + 0x018)
81 #define SSP_MIS(r) (r + 0x01C)
82 #define SSP_ICR(r) (r + 0x020)
83 #define SSP_DMACR(r) (r + 0x024)
84 #define SSP_ITCR(r) (r + 0x080)
85 #define SSP_ITIP(r) (r + 0x084)
86 #define SSP_ITOP(r) (r + 0x088)
87 #define SSP_TDR(r) (r + 0x08C)
89 #define SSP_PID0(r) (r + 0xFE0)
90 #define SSP_PID1(r) (r + 0xFE4)
91 #define SSP_PID2(r) (r + 0xFE8)
92 #define SSP_PID3(r) (r + 0xFEC)
94 #define SSP_CID0(r) (r + 0xFF0)
95 #define SSP_CID1(r) (r + 0xFF4)
96 #define SSP_CID2(r) (r + 0xFF8)
97 #define SSP_CID3(r) (r + 0xFFC)
100 * SSP Control Register 0 - SSP_CR0
102 #define SSP_CR0_MASK_DSS (0x0FUL << 0)
103 #define SSP_CR0_MASK_FRF (0x3UL << 4)
104 #define SSP_CR0_MASK_SPO (0x1UL << 6)
105 #define SSP_CR0_MASK_SPH (0x1UL << 7)
106 #define SSP_CR0_MASK_SCR (0xFFUL << 8)
109 * The ST version of this block moves som bits
110 * in SSP_CR0 and extends it to 32 bits
112 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
113 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
114 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
115 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
119 * SSP Control Register 0 - SSP_CR1
121 #define SSP_CR1_MASK_LBM (0x1UL << 0)
122 #define SSP_CR1_MASK_SSE (0x1UL << 1)
123 #define SSP_CR1_MASK_MS (0x1UL << 2)
124 #define SSP_CR1_MASK_SOD (0x1UL << 3)
127 * The ST version of this block adds some bits
130 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
131 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
132 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
133 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
134 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
135 /* This one is only in the PL023 variant */
136 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
139 * SSP Status Register - SSP_SR
141 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
142 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
143 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
144 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
145 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
148 * SSP Clock Prescale Register - SSP_CPSR
150 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
153 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
155 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
156 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
157 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
158 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
161 * SSP Raw Interrupt Status Register - SSP_RIS
163 /* Receive Overrun Raw Interrupt status */
164 #define SSP_RIS_MASK_RORRIS (0x1UL << 0)
165 /* Receive Timeout Raw Interrupt status */
166 #define SSP_RIS_MASK_RTRIS (0x1UL << 1)
167 /* Receive FIFO Raw Interrupt status */
168 #define SSP_RIS_MASK_RXRIS (0x1UL << 2)
169 /* Transmit FIFO Raw Interrupt status */
170 #define SSP_RIS_MASK_TXRIS (0x1UL << 3)
173 * SSP Masked Interrupt Status Register - SSP_MIS
175 /* Receive Overrun Masked Interrupt status */
176 #define SSP_MIS_MASK_RORMIS (0x1UL << 0)
177 /* Receive Timeout Masked Interrupt status */
178 #define SSP_MIS_MASK_RTMIS (0x1UL << 1)
179 /* Receive FIFO Masked Interrupt status */
180 #define SSP_MIS_MASK_RXMIS (0x1UL << 2)
181 /* Transmit FIFO Masked Interrupt status */
182 #define SSP_MIS_MASK_TXMIS (0x1UL << 3)
185 * SSP Interrupt Clear Register - SSP_ICR
187 /* Receive Overrun Raw Clear Interrupt bit */
188 #define SSP_ICR_MASK_RORIC (0x1UL << 0)
189 /* Receive Timeout Clear Interrupt bit */
190 #define SSP_ICR_MASK_RTIC (0x1UL << 1)
193 * SSP DMA Control Register - SSP_DMACR
195 /* Receive DMA Enable bit */
196 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
197 /* Transmit DMA Enable bit */
198 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
201 * SSP Integration Test control Register - SSP_ITCR
203 #define SSP_ITCR_MASK_ITEN (0x1UL << 0)
204 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
207 * SSP Integration Test Input Register - SSP_ITIP
209 #define ITIP_MASK_SSPRXD (0x1UL << 0)
210 #define ITIP_MASK_SSPFSSIN (0x1UL << 1)
211 #define ITIP_MASK_SSPCLKIN (0x1UL << 2)
212 #define ITIP_MASK_RXDMAC (0x1UL << 3)
213 #define ITIP_MASK_TXDMAC (0x1UL << 4)
214 #define ITIP_MASK_SSPTXDIN (0x1UL << 5)
217 * SSP Integration Test output Register - SSP_ITOP
219 #define ITOP_MASK_SSPTXD (0x1UL << 0)
220 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
221 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
222 #define ITOP_MASK_SSPOEn (0x1UL << 3)
223 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
224 #define ITOP_MASK_RORINTR (0x1UL << 5)
225 #define ITOP_MASK_RTINTR (0x1UL << 6)
226 #define ITOP_MASK_RXINTR (0x1UL << 7)
227 #define ITOP_MASK_TXINTR (0x1UL << 8)
228 #define ITOP_MASK_INTR (0x1UL << 9)
229 #define ITOP_MASK_RXDMABREQ (0x1UL << 10)
230 #define ITOP_MASK_RXDMASREQ (0x1UL << 11)
231 #define ITOP_MASK_TXDMABREQ (0x1UL << 12)
232 #define ITOP_MASK_TXDMASREQ (0x1UL << 13)
235 * SSP Test Data Register - SSP_TDR
237 #define TDR_MASK_TESTDATA (0xFFFFFFFF)
241 * we use the spi_message.state (void *) pointer to
242 * hold a single state value, that's why all this
243 * (void *) casting is done here.
245 #define STATE_START ((void *) 0)
246 #define STATE_RUNNING ((void *) 1)
247 #define STATE_DONE ((void *) 2)
248 #define STATE_ERROR ((void *) -1)
251 * SSP State - Whether Enabled or Disabled
253 #define SSP_DISABLED (0)
254 #define SSP_ENABLED (1)
257 * SSP DMA State - Whether DMA Enabled or Disabled
259 #define SSP_DMA_DISABLED (0)
260 #define SSP_DMA_ENABLED (1)
265 #define SSP_DEFAULT_CLKRATE 0x2
266 #define SSP_DEFAULT_PRESCALE 0x40
269 * SSP Clock Parameter ranges
271 #define CPSDVR_MIN 0x02
272 #define CPSDVR_MAX 0xFE
277 * SSP Interrupt related Macros
279 #define DEFAULT_SSP_REG_IMSC 0x0UL
280 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
281 #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
283 #define CLEAR_ALL_INTERRUPTS 0x3
285 #define SPI_POLLING_TIMEOUT 1000
289 * The type of reading going on on this chip
299 * The type of writing going on on this chip
309 * struct vendor_data - vendor-specific config parameters
310 * for PL022 derivates
311 * @fifodepth: depth of FIFOs (both)
312 * @max_bpw: maximum number of bits per word
313 * @unidir: supports unidirection transfers
314 * @extended_cr: 32 bit wide control register 0 with extra
315 * features and extra features in CR1 as found in the ST variants
316 * @pl023: supports a subset of the ST extensions called "PL023"
328 * struct pl022 - This is the private SSP driver data structure
329 * @adev: AMBA device model hookup
330 * @vendor: vendor data for the IP block
331 * @phybase: the physical memory where the SSP device resides
332 * @virtbase: the virtual memory where the SSP is mapped
333 * @clk: outgoing clock "SPICLK" for the SPI bus
334 * @master: SPI framework hookup
335 * @master_info: controller-specific data from machine setup
336 * @workqueue: a workqueue on which any spi_message request is queued
337 * @pump_messages: work struct for scheduling work to the workqueue
338 * @queue_lock: spinlock to syncronise access to message queue
339 * @queue: message queue
340 * @busy: workqueue is busy
341 * @running: workqueue is running
342 * @pump_transfers: Tasklet used in Interrupt Transfer mode
343 * @cur_msg: Pointer to current spi_message being processed
344 * @cur_transfer: Pointer to current spi_transfer
345 * @cur_chip: pointer to current clients chip(assigned from controller_state)
346 * @tx: current position in TX buffer to be read
347 * @tx_end: end position in TX buffer to be read
348 * @rx: current position in RX buffer to be written
349 * @rx_end: end position in RX buffer to be written
350 * @read: the type of read currently going on
351 * @write: the type of write currently going on
352 * @exp_fifo_level: expected FIFO level
353 * @dma_rx_channel: optional channel for RX DMA
354 * @dma_tx_channel: optional channel for TX DMA
355 * @sgt_rx: scattertable for the RX transfer
356 * @sgt_tx: scattertable for the TX transfer
357 * @dummypage: a dummy page used for driving data on the bus with DMA
360 struct amba_device *adev;
361 struct vendor_data *vendor;
362 resource_size_t phybase;
363 void __iomem *virtbase;
365 struct spi_master *master;
366 struct pl022_ssp_controller *master_info;
367 /* Driver message queue */
368 struct workqueue_struct *workqueue;
369 struct work_struct pump_messages;
370 spinlock_t queue_lock;
371 struct list_head queue;
374 /* Message transfer pump */
375 struct tasklet_struct pump_transfers;
376 struct spi_message *cur_msg;
377 struct spi_transfer *cur_transfer;
378 struct chip_data *cur_chip;
383 enum ssp_reading read;
384 enum ssp_writing write;
387 #ifdef CONFIG_DMA_ENGINE
388 struct dma_chan *dma_rx_channel;
389 struct dma_chan *dma_tx_channel;
390 struct sg_table sgt_rx;
391 struct sg_table sgt_tx;
397 * struct chip_data - To maintain runtime state of SSP for each client chip
398 * @cr0: Value of control register CR0 of SSP - on later ST variants this
399 * register is 32 bits wide rather than just 16
400 * @cr1: Value of control register CR1 of SSP
401 * @dmacr: Value of DMA control Register of SSP
402 * @cpsr: Value of Clock prescale register
403 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
404 * @enable_dma: Whether to enable DMA or not
405 * @read: function ptr to be used to read when doing xfer for this chip
406 * @write: function ptr to be used to write when doing xfer for this chip
407 * @cs_control: chip select callback provided by chip
408 * @xfer_type: polling/interrupt/DMA
410 * Runtime state of the SSP controller, maintained per chip,
411 * This would be set according to the current message that would be served
420 enum ssp_reading read;
421 enum ssp_writing write;
422 void (*cs_control) (u32 command);
427 * null_cs_control - Dummy chip select function
428 * @command: select/delect the chip
430 * If no chip select function is provided by client this is used as dummy
433 static void null_cs_control(u32 command)
435 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
439 * giveback - current spi_message is over, schedule next message and call
440 * callback of this message. Assumes that caller already
441 * set message->status; dma and pio irqs are blocked
442 * @pl022: SSP driver private data structure
444 static void giveback(struct pl022 *pl022)
446 struct spi_transfer *last_transfer;
448 struct spi_message *msg;
449 void (*curr_cs_control) (u32 command);
452 * This local reference to the chip select function
453 * is needed because we set curr_chip to NULL
454 * as a step toward termininating the message.
456 curr_cs_control = pl022->cur_chip->cs_control;
457 spin_lock_irqsave(&pl022->queue_lock, flags);
458 msg = pl022->cur_msg;
459 pl022->cur_msg = NULL;
460 pl022->cur_transfer = NULL;
461 pl022->cur_chip = NULL;
462 queue_work(pl022->workqueue, &pl022->pump_messages);
463 spin_unlock_irqrestore(&pl022->queue_lock, flags);
465 last_transfer = list_entry(msg->transfers.prev,
469 /* Delay if requested before any change in chip select */
470 if (last_transfer->delay_usecs)
472 * FIXME: This runs in interrupt context.
473 * Is this really smart?
475 udelay(last_transfer->delay_usecs);
478 * Drop chip select UNLESS cs_change is true or we are returning
479 * a message with an error, or next message is for another chip
481 if (!last_transfer->cs_change)
482 curr_cs_control(SSP_CHIP_DESELECT);
484 struct spi_message *next_msg;
486 /* Holding of cs was hinted, but we need to make sure
487 * the next message is for the same chip. Don't waste
488 * time with the following tests unless this was hinted.
490 * We cannot postpone this until pump_messages, because
491 * after calling msg->complete (below) the driver that
492 * sent the current message could be unloaded, which
493 * could invalidate the cs_control() callback...
496 /* get a pointer to the next message, if any */
497 spin_lock_irqsave(&pl022->queue_lock, flags);
498 if (list_empty(&pl022->queue))
501 next_msg = list_entry(pl022->queue.next,
502 struct spi_message, queue);
503 spin_unlock_irqrestore(&pl022->queue_lock, flags);
505 /* see if the next and current messages point
508 if (next_msg && next_msg->spi != msg->spi)
510 if (!next_msg || msg->state == STATE_ERROR)
511 curr_cs_control(SSP_CHIP_DESELECT);
515 msg->complete(msg->context);
516 /* This message is completed, so let's turn off the clocks & power */
517 clk_disable(pl022->clk);
518 amba_pclk_disable(pl022->adev);
519 amba_vcore_disable(pl022->adev);
523 * flush - flush the FIFO to reach a clean state
524 * @pl022: SSP driver private data structure
526 static int flush(struct pl022 *pl022)
528 unsigned long limit = loops_per_jiffy << 1;
530 dev_dbg(&pl022->adev->dev, "flush\n");
532 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
533 readw(SSP_DR(pl022->virtbase));
534 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
536 pl022->exp_fifo_level = 0;
542 * restore_state - Load configuration of current chip
543 * @pl022: SSP driver private data structure
545 static void restore_state(struct pl022 *pl022)
547 struct chip_data *chip = pl022->cur_chip;
549 if (pl022->vendor->extended_cr)
550 writel(chip->cr0, SSP_CR0(pl022->virtbase));
552 writew(chip->cr0, SSP_CR0(pl022->virtbase));
553 writew(chip->cr1, SSP_CR1(pl022->virtbase));
554 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
555 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
556 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
557 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
561 * Default SSP Register Values
563 #define DEFAULT_SSP_REG_CR0 ( \
564 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
565 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
566 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
567 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
568 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
571 /* ST versions have slightly different bit layout */
572 #define DEFAULT_SSP_REG_CR0_ST ( \
573 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
574 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
575 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
576 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
577 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
578 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
579 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
582 /* The PL023 version is slightly different again */
583 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
584 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
585 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
586 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
587 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
590 #define DEFAULT_SSP_REG_CR1 ( \
591 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
592 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
593 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
594 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
597 /* ST versions extend this register to use all 16 bits */
598 #define DEFAULT_SSP_REG_CR1_ST ( \
599 DEFAULT_SSP_REG_CR1 | \
600 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
601 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
602 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
603 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
604 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
608 * The PL023 variant has further differences: no loopback mode, no microwire
609 * support, and a new clock feedback delay setting.
611 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
612 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
613 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
614 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
615 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
616 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
617 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
618 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
619 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
622 #define DEFAULT_SSP_REG_CPSR ( \
623 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
626 #define DEFAULT_SSP_REG_DMACR (\
627 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
628 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
632 * load_ssp_default_config - Load default configuration for SSP
633 * @pl022: SSP driver private data structure
635 static void load_ssp_default_config(struct pl022 *pl022)
637 if (pl022->vendor->pl023) {
638 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
639 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
640 } else if (pl022->vendor->extended_cr) {
641 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
642 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
644 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
645 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
647 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
648 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
649 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
650 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
654 * This will write to TX and read from RX according to the parameters
657 static void readwriter(struct pl022 *pl022)
661 * The FIFO depth is different between primecell variants.
662 * I believe filling in too much in the FIFO might cause
663 * errons in 8bit wide transfers on ARM variants (just 8 words
664 * FIFO, means only 8x8 = 64 bits in FIFO) at least.
666 * To prevent this issue, the TX FIFO is only filled to the
667 * unused RX FIFO fill length, regardless of what the TX
668 * FIFO status flag indicates.
670 dev_dbg(&pl022->adev->dev,
671 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
672 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
674 /* Read as much as you can */
675 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
676 && (pl022->rx < pl022->rx_end)) {
677 switch (pl022->read) {
679 readw(SSP_DR(pl022->virtbase));
682 *(u8 *) (pl022->rx) =
683 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
686 *(u16 *) (pl022->rx) =
687 (u16) readw(SSP_DR(pl022->virtbase));
690 *(u32 *) (pl022->rx) =
691 readl(SSP_DR(pl022->virtbase));
694 pl022->rx += (pl022->cur_chip->n_bytes);
695 pl022->exp_fifo_level--;
698 * Write as much as possible up to the RX FIFO size
700 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
701 && (pl022->tx < pl022->tx_end)) {
702 switch (pl022->write) {
704 writew(0x0, SSP_DR(pl022->virtbase));
707 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
710 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
713 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
716 pl022->tx += (pl022->cur_chip->n_bytes);
717 pl022->exp_fifo_level++;
719 * This inner reader takes care of things appearing in the RX
720 * FIFO as we're transmitting. This will happen a lot since the
721 * clock starts running when you put things into the TX FIFO,
722 * and then things are continuously clocked into the RX FIFO.
724 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
725 && (pl022->rx < pl022->rx_end)) {
726 switch (pl022->read) {
728 readw(SSP_DR(pl022->virtbase));
731 *(u8 *) (pl022->rx) =
732 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
735 *(u16 *) (pl022->rx) =
736 (u16) readw(SSP_DR(pl022->virtbase));
739 *(u32 *) (pl022->rx) =
740 readl(SSP_DR(pl022->virtbase));
743 pl022->rx += (pl022->cur_chip->n_bytes);
744 pl022->exp_fifo_level--;
748 * When we exit here the TX FIFO should be full and the RX FIFO
755 * next_transfer - Move to the Next transfer in the current spi message
756 * @pl022: SSP driver private data structure
758 * This function moves though the linked list of spi transfers in the
759 * current spi message and returns with the state of current spi
760 * message i.e whether its last transfer is done(STATE_DONE) or
761 * Next transfer is ready(STATE_RUNNING)
763 static void *next_transfer(struct pl022 *pl022)
765 struct spi_message *msg = pl022->cur_msg;
766 struct spi_transfer *trans = pl022->cur_transfer;
768 /* Move to next transfer */
769 if (trans->transfer_list.next != &msg->transfers) {
770 pl022->cur_transfer =
771 list_entry(trans->transfer_list.next,
772 struct spi_transfer, transfer_list);
773 return STATE_RUNNING;
779 * This DMA functionality is only compiled in if we have
780 * access to the generic DMA devices/DMA engine.
782 #ifdef CONFIG_DMA_ENGINE
783 static void unmap_free_dma_scatter(struct pl022 *pl022)
785 /* Unmap and free the SG tables */
786 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
787 pl022->sgt_tx.nents, DMA_TO_DEVICE);
788 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
789 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
790 sg_free_table(&pl022->sgt_rx);
791 sg_free_table(&pl022->sgt_tx);
794 static void dma_callback(void *data)
796 struct pl022 *pl022 = data;
797 struct spi_message *msg = pl022->cur_msg;
799 BUG_ON(!pl022->sgt_rx.sgl);
803 * Optionally dump out buffers to inspect contents, this is
804 * good if you want to convince yourself that the loopback
805 * read/write contents are the same, when adopting to a new
809 struct scatterlist *sg;
812 dma_sync_sg_for_cpu(&pl022->adev->dev,
817 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
818 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
819 print_hex_dump(KERN_ERR, "SPI RX: ",
827 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
828 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
829 print_hex_dump(KERN_ERR, "SPI TX: ",
840 unmap_free_dma_scatter(pl022);
842 /* Update total bytes transferred */
843 msg->actual_length += pl022->cur_transfer->len;
844 if (pl022->cur_transfer->cs_change)
846 cs_control(SSP_CHIP_DESELECT);
848 /* Move to next transfer */
849 msg->state = next_transfer(pl022);
850 tasklet_schedule(&pl022->pump_transfers);
853 static void setup_dma_scatter(struct pl022 *pl022,
856 struct sg_table *sgtab)
858 struct scatterlist *sg;
859 int bytesleft = length;
865 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
867 * If there are less bytes left than what fits
868 * in the current page (plus page alignment offset)
869 * we just feed in this, else we stuff in as much
872 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
873 mapbytes = bytesleft;
875 mapbytes = PAGE_SIZE - offset_in_page(bufp);
876 sg_set_page(sg, virt_to_page(bufp),
877 mapbytes, offset_in_page(bufp));
879 bytesleft -= mapbytes;
880 dev_dbg(&pl022->adev->dev,
881 "set RX/TX target page @ %p, %d bytes, %d left\n",
882 bufp, mapbytes, bytesleft);
885 /* Map the dummy buffer on every page */
886 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
887 if (bytesleft < PAGE_SIZE)
888 mapbytes = bytesleft;
890 mapbytes = PAGE_SIZE;
891 sg_set_page(sg, virt_to_page(pl022->dummypage),
893 bytesleft -= mapbytes;
894 dev_dbg(&pl022->adev->dev,
895 "set RX/TX to dummy page %d bytes, %d left\n",
896 mapbytes, bytesleft);
904 * configure_dma - configures the channels for the next transfer
905 * @pl022: SSP driver's private data structure
907 static int configure_dma(struct pl022 *pl022)
909 struct dma_slave_config rx_conf = {
910 .src_addr = SSP_DR(pl022->phybase),
911 .direction = DMA_FROM_DEVICE,
912 .src_maxburst = pl022->vendor->fifodepth >> 1,
914 struct dma_slave_config tx_conf = {
915 .dst_addr = SSP_DR(pl022->phybase),
916 .direction = DMA_TO_DEVICE,
917 .dst_maxburst = pl022->vendor->fifodepth >> 1,
921 int rx_sglen, tx_sglen;
922 struct dma_chan *rxchan = pl022->dma_rx_channel;
923 struct dma_chan *txchan = pl022->dma_tx_channel;
924 struct dma_async_tx_descriptor *rxdesc;
925 struct dma_async_tx_descriptor *txdesc;
927 /* Check that the channels are available */
928 if (!rxchan || !txchan)
931 switch (pl022->read) {
933 /* Use the same as for writing */
934 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
937 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
940 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
943 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
947 switch (pl022->write) {
949 /* Use the same as for reading */
950 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
953 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
956 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
959 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
963 /* SPI pecularity: we need to read and write the same width */
964 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
965 rx_conf.src_addr_width = tx_conf.dst_addr_width;
966 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
967 tx_conf.dst_addr_width = rx_conf.src_addr_width;
968 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
970 dmaengine_slave_config(rxchan, &rx_conf);
971 dmaengine_slave_config(txchan, &tx_conf);
973 /* Create sglists for the transfers */
974 pages = (pl022->cur_transfer->len >> PAGE_SHIFT) + 1;
975 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
977 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_KERNEL);
979 goto err_alloc_rx_sg;
981 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_KERNEL);
983 goto err_alloc_tx_sg;
985 /* Fill in the scatterlists for the RX+TX buffers */
986 setup_dma_scatter(pl022, pl022->rx,
987 pl022->cur_transfer->len, &pl022->sgt_rx);
988 setup_dma_scatter(pl022, pl022->tx,
989 pl022->cur_transfer->len, &pl022->sgt_tx);
991 /* Map DMA buffers */
992 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
993 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
997 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
998 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1002 /* Send both scatterlists */
1003 rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
1007 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1011 txdesc = txchan->device->device_prep_slave_sg(txchan,
1015 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1019 /* Put the callback on the RX transfer only, that should finish last */
1020 rxdesc->callback = dma_callback;
1021 rxdesc->callback_param = pl022;
1023 /* Submit and fire RX and TX with TX last so we're ready to read! */
1024 dmaengine_submit(rxdesc);
1025 dmaengine_submit(txdesc);
1026 dma_async_issue_pending(rxchan);
1027 dma_async_issue_pending(txchan);
1032 dmaengine_terminate_all(txchan);
1034 dmaengine_terminate_all(rxchan);
1035 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1036 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1038 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1039 pl022->sgt_tx.nents, DMA_FROM_DEVICE);
1041 sg_free_table(&pl022->sgt_tx);
1043 sg_free_table(&pl022->sgt_rx);
1048 static int __init pl022_dma_probe(struct pl022 *pl022)
1050 dma_cap_mask_t mask;
1052 /* Try to acquire a generic DMA engine slave channel */
1054 dma_cap_set(DMA_SLAVE, mask);
1056 * We need both RX and TX channels to do DMA, else do none
1059 pl022->dma_rx_channel = dma_request_channel(mask,
1060 pl022->master_info->dma_filter,
1061 pl022->master_info->dma_rx_param);
1062 if (!pl022->dma_rx_channel) {
1063 dev_err(&pl022->adev->dev, "no RX DMA channel!\n");
1067 pl022->dma_tx_channel = dma_request_channel(mask,
1068 pl022->master_info->dma_filter,
1069 pl022->master_info->dma_tx_param);
1070 if (!pl022->dma_tx_channel) {
1071 dev_err(&pl022->adev->dev, "no TX DMA channel!\n");
1075 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1076 if (!pl022->dummypage) {
1077 dev_err(&pl022->adev->dev, "no DMA dummypage!\n");
1078 goto err_no_dummypage;
1081 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1082 dma_chan_name(pl022->dma_rx_channel),
1083 dma_chan_name(pl022->dma_tx_channel));
1088 dma_release_channel(pl022->dma_tx_channel);
1090 dma_release_channel(pl022->dma_rx_channel);
1091 pl022->dma_rx_channel = NULL;
1096 static void terminate_dma(struct pl022 *pl022)
1098 struct dma_chan *rxchan = pl022->dma_rx_channel;
1099 struct dma_chan *txchan = pl022->dma_tx_channel;
1101 dmaengine_terminate_all(rxchan);
1102 dmaengine_terminate_all(txchan);
1103 unmap_free_dma_scatter(pl022);
1106 static void pl022_dma_remove(struct pl022 *pl022)
1109 terminate_dma(pl022);
1110 if (pl022->dma_tx_channel)
1111 dma_release_channel(pl022->dma_tx_channel);
1112 if (pl022->dma_rx_channel)
1113 dma_release_channel(pl022->dma_rx_channel);
1114 kfree(pl022->dummypage);
1118 static inline int configure_dma(struct pl022 *pl022)
1123 static inline int pl022_dma_probe(struct pl022 *pl022)
1128 static inline void pl022_dma_remove(struct pl022 *pl022)
1134 * pl022_interrupt_handler - Interrupt handler for SSP controller
1136 * This function handles interrupts generated for an interrupt based transfer.
1137 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
1138 * current message's state as STATE_ERROR and schedule the tasklet
1139 * pump_transfers which will do the postprocessing of the current message by
1140 * calling giveback(). Otherwise it reads data from RX FIFO till there is no
1141 * more data, and writes data in TX FIFO till it is not full. If we complete
1142 * the transfer we move to the next transfer and schedule the tasklet.
1144 static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1146 struct pl022 *pl022 = dev_id;
1147 struct spi_message *msg = pl022->cur_msg;
1151 if (unlikely(!msg)) {
1152 dev_err(&pl022->adev->dev,
1153 "bad message state in interrupt handler");
1158 /* Read the Interrupt Status Register */
1159 irq_status = readw(SSP_MIS(pl022->virtbase));
1161 if (unlikely(!irq_status))
1165 * This handles the FIFO interrupts, the timeout
1166 * interrupts are flatly ignored, they cannot be
1169 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
1171 * Overrun interrupt - bail out since our Data has been
1174 dev_err(&pl022->adev->dev, "FIFO overrun\n");
1175 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1176 dev_err(&pl022->adev->dev,
1177 "RXFIFO is full\n");
1178 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
1179 dev_err(&pl022->adev->dev,
1180 "TXFIFO is full\n");
1183 * Disable and clear interrupts, disable SSP,
1184 * mark message with bad status so it can be
1187 writew(DISABLE_ALL_INTERRUPTS,
1188 SSP_IMSC(pl022->virtbase));
1189 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1190 writew((readw(SSP_CR1(pl022->virtbase)) &
1191 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1192 msg->state = STATE_ERROR;
1194 /* Schedule message queue handler */
1195 tasklet_schedule(&pl022->pump_transfers);
1201 if ((pl022->tx == pl022->tx_end) && (flag == 0)) {
1203 /* Disable Transmit interrupt */
1204 writew(readw(SSP_IMSC(pl022->virtbase)) &
1205 (~SSP_IMSC_MASK_TXIM),
1206 SSP_IMSC(pl022->virtbase));
1210 * Since all transactions must write as much as shall be read,
1211 * we can conclude the entire transaction once RX is complete.
1212 * At this point, all TX will always be finished.
1214 if (pl022->rx >= pl022->rx_end) {
1215 writew(DISABLE_ALL_INTERRUPTS,
1216 SSP_IMSC(pl022->virtbase));
1217 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1218 if (unlikely(pl022->rx > pl022->rx_end)) {
1219 dev_warn(&pl022->adev->dev, "read %u surplus "
1220 "bytes (did you request an odd "
1221 "number of bytes on a 16bit bus?)\n",
1222 (u32) (pl022->rx - pl022->rx_end));
1224 /* Update total bytes transferred */
1225 msg->actual_length += pl022->cur_transfer->len;
1226 if (pl022->cur_transfer->cs_change)
1228 cs_control(SSP_CHIP_DESELECT);
1229 /* Move to next transfer */
1230 msg->state = next_transfer(pl022);
1231 tasklet_schedule(&pl022->pump_transfers);
1239 * This sets up the pointers to memory for the next message to
1240 * send out on the SPI bus.
1242 static int set_up_next_transfer(struct pl022 *pl022,
1243 struct spi_transfer *transfer)
1247 /* Sanity check the message for this bus width */
1248 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1249 if (unlikely(residue != 0)) {
1250 dev_err(&pl022->adev->dev,
1251 "message of %u bytes to transmit but the current "
1252 "chip bus has a data width of %u bytes!\n",
1253 pl022->cur_transfer->len,
1254 pl022->cur_chip->n_bytes);
1255 dev_err(&pl022->adev->dev, "skipping this message\n");
1258 pl022->tx = (void *)transfer->tx_buf;
1259 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1260 pl022->rx = (void *)transfer->rx_buf;
1261 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1263 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1264 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1269 * pump_transfers - Tasklet function which schedules next transfer
1270 * when running in interrupt or DMA transfer mode.
1271 * @data: SSP driver private data structure
1274 static void pump_transfers(unsigned long data)
1276 struct pl022 *pl022 = (struct pl022 *) data;
1277 struct spi_message *message = NULL;
1278 struct spi_transfer *transfer = NULL;
1279 struct spi_transfer *previous = NULL;
1281 /* Get current state information */
1282 message = pl022->cur_msg;
1283 transfer = pl022->cur_transfer;
1285 /* Handle for abort */
1286 if (message->state == STATE_ERROR) {
1287 message->status = -EIO;
1292 /* Handle end of message */
1293 if (message->state == STATE_DONE) {
1294 message->status = 0;
1299 /* Delay if requested at end of transfer before CS change */
1300 if (message->state == STATE_RUNNING) {
1301 previous = list_entry(transfer->transfer_list.prev,
1302 struct spi_transfer,
1304 if (previous->delay_usecs)
1306 * FIXME: This runs in interrupt context.
1307 * Is this really smart?
1309 udelay(previous->delay_usecs);
1311 /* Drop chip select only if cs_change is requested */
1312 if (previous->cs_change)
1313 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1316 message->state = STATE_RUNNING;
1319 if (set_up_next_transfer(pl022, transfer)) {
1320 message->state = STATE_ERROR;
1321 message->status = -EIO;
1325 /* Flush the FIFOs and let's go! */
1328 if (pl022->cur_chip->enable_dma) {
1329 if (configure_dma(pl022)) {
1330 dev_dbg(&pl022->adev->dev,
1331 "configuration of DMA failed, fall back to interrupt mode\n");
1332 goto err_config_dma;
1338 writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
1341 static void do_interrupt_dma_transfer(struct pl022 *pl022)
1343 u32 irqflags = ENABLE_ALL_INTERRUPTS;
1345 /* Enable target chip */
1346 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1347 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1349 pl022->cur_msg->state = STATE_ERROR;
1350 pl022->cur_msg->status = -EIO;
1354 /* If we're using DMA, set up DMA here */
1355 if (pl022->cur_chip->enable_dma) {
1356 /* Configure DMA transfer */
1357 if (configure_dma(pl022)) {
1358 dev_dbg(&pl022->adev->dev,
1359 "configuration of DMA failed, fall back to interrupt mode\n");
1360 goto err_config_dma;
1362 /* Disable interrupts in DMA mode, IRQ from DMA controller */
1363 irqflags = DISABLE_ALL_INTERRUPTS;
1366 /* Enable SSP, turn on interrupts */
1367 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1368 SSP_CR1(pl022->virtbase));
1369 writew(irqflags, SSP_IMSC(pl022->virtbase));
1372 static void do_polling_transfer(struct pl022 *pl022)
1374 struct spi_message *message = NULL;
1375 struct spi_transfer *transfer = NULL;
1376 struct spi_transfer *previous = NULL;
1377 struct chip_data *chip;
1378 unsigned long time, timeout;
1380 chip = pl022->cur_chip;
1381 message = pl022->cur_msg;
1383 while (message->state != STATE_DONE) {
1384 /* Handle for abort */
1385 if (message->state == STATE_ERROR)
1387 transfer = pl022->cur_transfer;
1389 /* Delay if requested at end of transfer */
1390 if (message->state == STATE_RUNNING) {
1392 list_entry(transfer->transfer_list.prev,
1393 struct spi_transfer, transfer_list);
1394 if (previous->delay_usecs)
1395 udelay(previous->delay_usecs);
1396 if (previous->cs_change)
1397 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1400 message->state = STATE_RUNNING;
1401 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1404 /* Configuration Changing Per Transfer */
1405 if (set_up_next_transfer(pl022, transfer)) {
1407 message->state = STATE_ERROR;
1410 /* Flush FIFOs and enable SSP */
1412 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1413 SSP_CR1(pl022->virtbase));
1415 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
1417 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
1418 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
1421 if (time_after(time, timeout)) {
1422 dev_warn(&pl022->adev->dev,
1423 "%s: timeout!\n", __func__);
1424 message->state = STATE_ERROR;
1429 /* Update total byte transferred */
1430 message->actual_length += pl022->cur_transfer->len;
1431 if (pl022->cur_transfer->cs_change)
1432 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT);
1433 /* Move to next transfer */
1434 message->state = next_transfer(pl022);
1437 /* Handle end of message */
1438 if (message->state == STATE_DONE)
1439 message->status = 0;
1441 message->status = -EIO;
1448 * pump_messages - Workqueue function which processes spi message queue
1449 * @data: pointer to private data of SSP driver
1451 * This function checks if there is any spi message in the queue that
1452 * needs processing and delegate control to appropriate function
1453 * do_polling_transfer()/do_interrupt_dma_transfer()
1454 * based on the kind of the transfer
1457 static void pump_messages(struct work_struct *work)
1459 struct pl022 *pl022 =
1460 container_of(work, struct pl022, pump_messages);
1461 unsigned long flags;
1463 /* Lock queue and check for queue work */
1464 spin_lock_irqsave(&pl022->queue_lock, flags);
1465 if (list_empty(&pl022->queue) || !pl022->running) {
1466 pl022->busy = false;
1467 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1470 /* Make sure we are not already running a message */
1471 if (pl022->cur_msg) {
1472 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1475 /* Extract head of queue */
1477 list_entry(pl022->queue.next, struct spi_message, queue);
1479 list_del_init(&pl022->cur_msg->queue);
1481 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1483 /* Initial message state */
1484 pl022->cur_msg->state = STATE_START;
1485 pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next,
1486 struct spi_transfer,
1489 /* Setup the SPI using the per chip configuration */
1490 pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi);
1492 * We enable the core voltage and clocks here, then the clocks
1493 * and core will be disabled when giveback() is called in each method
1494 * (poll/interrupt/DMA)
1496 amba_vcore_enable(pl022->adev);
1497 amba_pclk_enable(pl022->adev);
1498 clk_enable(pl022->clk);
1499 restore_state(pl022);
1502 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1503 do_polling_transfer(pl022);
1505 do_interrupt_dma_transfer(pl022);
1509 static int __init init_queue(struct pl022 *pl022)
1511 INIT_LIST_HEAD(&pl022->queue);
1512 spin_lock_init(&pl022->queue_lock);
1514 pl022->running = false;
1515 pl022->busy = false;
1517 tasklet_init(&pl022->pump_transfers,
1518 pump_transfers, (unsigned long)pl022);
1520 INIT_WORK(&pl022->pump_messages, pump_messages);
1521 pl022->workqueue = create_singlethread_workqueue(
1522 dev_name(pl022->master->dev.parent));
1523 if (pl022->workqueue == NULL)
1530 static int start_queue(struct pl022 *pl022)
1532 unsigned long flags;
1534 spin_lock_irqsave(&pl022->queue_lock, flags);
1536 if (pl022->running || pl022->busy) {
1537 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1541 pl022->running = true;
1542 pl022->cur_msg = NULL;
1543 pl022->cur_transfer = NULL;
1544 pl022->cur_chip = NULL;
1545 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1547 queue_work(pl022->workqueue, &pl022->pump_messages);
1553 static int stop_queue(struct pl022 *pl022)
1555 unsigned long flags;
1556 unsigned limit = 500;
1559 spin_lock_irqsave(&pl022->queue_lock, flags);
1561 /* This is a bit lame, but is optimized for the common execution path.
1562 * A wait_queue on the pl022->busy could be used, but then the common
1563 * execution path (pump_messages) would be required to call wake_up or
1564 * friends on every SPI message. Do this instead */
1565 while ((!list_empty(&pl022->queue) || pl022->busy) && limit--) {
1566 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1568 spin_lock_irqsave(&pl022->queue_lock, flags);
1571 if (!list_empty(&pl022->queue) || pl022->busy)
1574 pl022->running = false;
1576 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1581 static int destroy_queue(struct pl022 *pl022)
1585 status = stop_queue(pl022);
1586 /* we are unloading the module or failing to load (only two calls
1587 * to this routine), and neither call can handle a return value.
1588 * However, destroy_workqueue calls flush_workqueue, and that will
1589 * block until all work is done. If the reason that stop_queue
1590 * timed out is that the work will never finish, then it does no
1591 * good to call destroy_workqueue, so return anyway. */
1595 destroy_workqueue(pl022->workqueue);
1600 static int verify_controller_parameters(struct pl022 *pl022,
1601 struct pl022_config_chip const *chip_info)
1603 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1604 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
1605 dev_err(&pl022->adev->dev,
1606 "interface is configured incorrectly\n");
1609 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1610 (!pl022->vendor->unidir)) {
1611 dev_err(&pl022->adev->dev,
1612 "unidirectional mode not supported in this "
1613 "hardware version\n");
1616 if ((chip_info->hierarchy != SSP_MASTER)
1617 && (chip_info->hierarchy != SSP_SLAVE)) {
1618 dev_err(&pl022->adev->dev,
1619 "hierarchy is configured incorrectly\n");
1622 if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1623 && (chip_info->com_mode != DMA_TRANSFER)
1624 && (chip_info->com_mode != POLLING_TRANSFER)) {
1625 dev_err(&pl022->adev->dev,
1626 "Communication mode is configured incorrectly\n");
1629 if ((chip_info->rx_lev_trig < SSP_RX_1_OR_MORE_ELEM)
1630 || (chip_info->rx_lev_trig > SSP_RX_32_OR_MORE_ELEM)) {
1631 dev_err(&pl022->adev->dev,
1632 "RX FIFO Trigger Level is configured incorrectly\n");
1635 if ((chip_info->tx_lev_trig < SSP_TX_1_OR_MORE_EMPTY_LOC)
1636 || (chip_info->tx_lev_trig > SSP_TX_32_OR_MORE_EMPTY_LOC)) {
1637 dev_err(&pl022->adev->dev,
1638 "TX FIFO Trigger Level is configured incorrectly\n");
1641 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1642 if ((chip_info->ctrl_len < SSP_BITS_4)
1643 || (chip_info->ctrl_len > SSP_BITS_32)) {
1644 dev_err(&pl022->adev->dev,
1645 "CTRL LEN is configured incorrectly\n");
1648 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1649 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
1650 dev_err(&pl022->adev->dev,
1651 "Wait State is configured incorrectly\n");
1654 /* Half duplex is only available in the ST Micro version */
1655 if (pl022->vendor->extended_cr) {
1656 if ((chip_info->duplex !=
1657 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1658 && (chip_info->duplex !=
1659 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
1660 dev_err(&pl022->adev->dev,
1661 "Microwire duplex mode is configured incorrectly\n");
1665 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1666 dev_err(&pl022->adev->dev,
1667 "Microwire half duplex mode requested,"
1668 " but this is only available in the"
1669 " ST version of PL022\n");
1677 * pl022_transfer - transfer function registered to SPI master framework
1678 * @spi: spi device which is requesting transfer
1679 * @msg: spi message which is to handled is queued to driver queue
1681 * This function is registered to the SPI framework for this SPI master
1682 * controller. It will queue the spi_message in the queue of driver if
1683 * the queue is not stopped and return.
1685 static int pl022_transfer(struct spi_device *spi, struct spi_message *msg)
1687 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1688 unsigned long flags;
1690 spin_lock_irqsave(&pl022->queue_lock, flags);
1692 if (!pl022->running) {
1693 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1696 msg->actual_length = 0;
1697 msg->status = -EINPROGRESS;
1698 msg->state = STATE_START;
1700 list_add_tail(&msg->queue, &pl022->queue);
1701 if (pl022->running && !pl022->busy)
1702 queue_work(pl022->workqueue, &pl022->pump_messages);
1704 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1708 static int calculate_effective_freq(struct pl022 *pl022,
1710 struct ssp_clock_params *clk_freq)
1712 /* Lets calculate the frequency parameters */
1715 bool freq_found = false;
1720 rate = clk_get_rate(pl022->clk);
1721 /* cpsdvscr = 2 & scr 0 */
1722 max_tclk = (rate / (CPSDVR_MIN * (1 + SCR_MIN)));
1723 /* cpsdvsr = 254 & scr = 255 */
1724 min_tclk = (rate / (CPSDVR_MAX * (1 + SCR_MAX)));
1726 if ((freq <= max_tclk) && (freq >= min_tclk)) {
1727 while (cpsdvsr <= CPSDVR_MAX && !freq_found) {
1728 while (scr <= SCR_MAX && !freq_found) {
1730 (cpsdvsr * (1 + scr))) > freq)
1734 * This bool is made true when
1735 * effective frequency >=
1736 * target frequency is found
1740 (cpsdvsr * (1 + scr))) != freq) {
1741 if (scr == SCR_MIN) {
1755 dev_dbg(&pl022->adev->dev,
1756 "SSP Effective Frequency is %u\n",
1757 (rate / (cpsdvsr * (1 + scr))));
1758 clk_freq->cpsdvsr = (u8) (cpsdvsr & 0xFF);
1759 clk_freq->scr = (u8) (scr & 0xFF);
1760 dev_dbg(&pl022->adev->dev,
1761 "SSP cpsdvsr = %d, scr = %d\n",
1762 clk_freq->cpsdvsr, clk_freq->scr);
1765 dev_err(&pl022->adev->dev,
1766 "controller data is incorrect: out of range frequency");
1774 * A piece of default chip info unless the platform
1777 static const struct pl022_config_chip pl022_default_chip_info = {
1778 .com_mode = POLLING_TRANSFER,
1779 .iface = SSP_INTERFACE_MOTOROLA_SPI,
1780 .hierarchy = SSP_SLAVE,
1781 .slave_tx_disable = DO_NOT_DRIVE_TX,
1782 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
1783 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
1784 .ctrl_len = SSP_BITS_8,
1785 .wait_state = SSP_MWIRE_WAIT_ZERO,
1786 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
1787 .cs_control = null_cs_control,
1792 * pl022_setup - setup function registered to SPI master framework
1793 * @spi: spi device which is requesting setup
1795 * This function is registered to the SPI framework for this SPI master
1796 * controller. If it is the first time when setup is called by this device,
1797 * this function will initialize the runtime state for this chip and save
1798 * the same in the device structure. Else it will update the runtime info
1799 * with the updated chip info. Nothing is really being written to the
1800 * controller hardware here, that is not done until the actual transfer
1803 static int pl022_setup(struct spi_device *spi)
1805 struct pl022_config_chip const *chip_info;
1806 struct chip_data *chip;
1807 struct ssp_clock_params clk_freq = {0, };
1809 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1810 unsigned int bits = spi->bits_per_word;
1813 if (!spi->max_speed_hz)
1816 /* Get controller_state if one is supplied */
1817 chip = spi_get_ctldata(spi);
1820 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1823 "cannot allocate controller state\n");
1827 "allocated memory for controller's runtime state\n");
1830 /* Get controller data if one is supplied */
1831 chip_info = spi->controller_data;
1833 if (chip_info == NULL) {
1834 chip_info = &pl022_default_chip_info;
1835 /* spi_board_info.controller_data not is supplied */
1837 "using default controller_data settings\n");
1840 "using user supplied controller_data settings\n");
1843 * We can override with custom divisors, else we use the board
1846 if ((0 == chip_info->clk_freq.cpsdvsr)
1847 && (0 == chip_info->clk_freq.scr)) {
1848 status = calculate_effective_freq(pl022,
1852 goto err_config_params;
1854 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
1855 if ((clk_freq.cpsdvsr % 2) != 0)
1857 clk_freq.cpsdvsr - 1;
1859 if ((clk_freq.cpsdvsr < CPSDVR_MIN)
1860 || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
1862 "cpsdvsr is configured incorrectly\n");
1863 goto err_config_params;
1867 status = verify_controller_parameters(pl022, chip_info);
1869 dev_err(&spi->dev, "controller data is incorrect");
1870 goto err_config_params;
1873 /* Now set controller state based on controller data */
1874 chip->xfer_type = chip_info->com_mode;
1875 if (!chip_info->cs_control) {
1876 chip->cs_control = null_cs_control;
1878 "chip select function is NULL for this chip\n");
1880 chip->cs_control = chip_info->cs_control;
1883 /* PL022 doesn't support less than 4-bits */
1885 goto err_config_params;
1886 } else if (bits <= 8) {
1887 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
1889 chip->read = READING_U8;
1890 chip->write = WRITING_U8;
1891 } else if (bits <= 16) {
1892 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1894 chip->read = READING_U16;
1895 chip->write = WRITING_U16;
1897 if (pl022->vendor->max_bpw >= 32) {
1898 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1900 chip->read = READING_U32;
1901 chip->write = WRITING_U32;
1904 "illegal data size for this controller!\n");
1906 "a standard pl022 can only handle "
1907 "1 <= n <= 16 bit words\n");
1909 goto err_config_params;
1913 /* Now Initialize all register settings required for this chip */
1918 if ((chip_info->com_mode == DMA_TRANSFER)
1919 && ((pl022->master_info)->enable_dma)) {
1920 chip->enable_dma = true;
1921 dev_dbg(&spi->dev, "DMA mode set in controller state\n");
1922 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1923 SSP_DMACR_MASK_RXDMAE, 0);
1924 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1925 SSP_DMACR_MASK_TXDMAE, 1);
1927 chip->enable_dma = false;
1928 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
1929 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1930 SSP_DMACR_MASK_RXDMAE, 0);
1931 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1932 SSP_DMACR_MASK_TXDMAE, 1);
1935 chip->cpsr = clk_freq.cpsdvsr;
1937 /* Special setup for the ST micro extended control registers */
1938 if (pl022->vendor->extended_cr) {
1941 if (pl022->vendor->pl023) {
1942 /* These bits are only in the PL023 */
1943 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
1944 SSP_CR1_MASK_FBCLKDEL_ST, 13);
1946 /* These bits are in the PL022 but not PL023 */
1947 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
1948 SSP_CR0_MASK_HALFDUP_ST, 5);
1949 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
1950 SSP_CR0_MASK_CSS_ST, 16);
1951 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1952 SSP_CR0_MASK_FRF_ST, 21);
1953 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
1954 SSP_CR1_MASK_MWAIT_ST, 6);
1956 SSP_WRITE_BITS(chip->cr0, bits - 1,
1957 SSP_CR0_MASK_DSS_ST, 0);
1959 if (spi->mode & SPI_LSB_FIRST) {
1966 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
1967 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
1968 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
1969 SSP_CR1_MASK_RXIFLSEL_ST, 7);
1970 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
1971 SSP_CR1_MASK_TXIFLSEL_ST, 10);
1973 SSP_WRITE_BITS(chip->cr0, bits - 1,
1974 SSP_CR0_MASK_DSS, 0);
1975 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1976 SSP_CR0_MASK_FRF, 4);
1979 /* Stuff that is common for all versions */
1980 if (spi->mode & SPI_CPOL)
1981 tmp = SSP_CLK_POL_IDLE_HIGH;
1983 tmp = SSP_CLK_POL_IDLE_LOW;
1984 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
1986 if (spi->mode & SPI_CPHA)
1987 tmp = SSP_CLK_SECOND_EDGE;
1989 tmp = SSP_CLK_FIRST_EDGE;
1990 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
1992 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
1993 /* Loopback is available on all versions except PL023 */
1994 if (pl022->vendor->loopback) {
1995 if (spi->mode & SPI_LOOP)
1996 tmp = LOOPBACK_ENABLED;
1998 tmp = LOOPBACK_DISABLED;
1999 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
2001 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
2002 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
2003 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 3);
2005 /* Save controller_state */
2006 spi_set_ctldata(spi, chip);
2009 spi_set_ctldata(spi, NULL);
2015 * pl022_cleanup - cleanup function registered to SPI master framework
2016 * @spi: spi device which is requesting cleanup
2018 * This function is registered to the SPI framework for this SPI master
2019 * controller. It will free the runtime state of chip.
2021 static void pl022_cleanup(struct spi_device *spi)
2023 struct chip_data *chip = spi_get_ctldata(spi);
2025 spi_set_ctldata(spi, NULL);
2030 static int __devinit
2031 pl022_probe(struct amba_device *adev, const struct amba_id *id)
2033 struct device *dev = &adev->dev;
2034 struct pl022_ssp_controller *platform_info = adev->dev.platform_data;
2035 struct spi_master *master;
2036 struct pl022 *pl022 = NULL; /*Data for this driver */
2039 dev_info(&adev->dev,
2040 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
2041 if (platform_info == NULL) {
2042 dev_err(&adev->dev, "probe - no platform data supplied\n");
2047 /* Allocate master with space for data */
2048 master = spi_alloc_master(dev, sizeof(struct pl022));
2049 if (master == NULL) {
2050 dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
2055 pl022 = spi_master_get_devdata(master);
2056 pl022->master = master;
2057 pl022->master_info = platform_info;
2059 pl022->vendor = id->data;
2062 * Bus Number Which has been Assigned to this SSP controller
2065 master->bus_num = platform_info->bus_id;
2066 master->num_chipselect = platform_info->num_chipselect;
2067 master->cleanup = pl022_cleanup;
2068 master->setup = pl022_setup;
2069 master->transfer = pl022_transfer;
2072 * Supports mode 0-3, loopback, and active low CS. Transfers are
2073 * always MS bit first on the original pl022.
2075 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
2076 if (pl022->vendor->extended_cr)
2077 master->mode_bits |= SPI_LSB_FIRST;
2079 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
2081 status = amba_request_regions(adev, NULL);
2083 goto err_no_ioregion;
2085 pl022->phybase = adev->res.start;
2086 pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
2087 if (pl022->virtbase == NULL) {
2089 goto err_no_ioremap;
2091 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n",
2092 adev->res.start, pl022->virtbase);
2094 pl022->clk = clk_get(&adev->dev, NULL);
2095 if (IS_ERR(pl022->clk)) {
2096 status = PTR_ERR(pl022->clk);
2097 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
2102 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2103 SSP_CR1(pl022->virtbase));
2104 load_ssp_default_config(pl022);
2106 status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022",
2109 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
2113 /* Get DMA channels */
2114 if (platform_info->enable_dma) {
2115 status = pl022_dma_probe(pl022);
2120 /* Initialize and start queue */
2121 status = init_queue(pl022);
2123 dev_err(&adev->dev, "probe - problem initializing queue\n");
2124 goto err_init_queue;
2126 status = start_queue(pl022);
2128 dev_err(&adev->dev, "probe - problem starting queue\n");
2129 goto err_start_queue;
2131 /* Register with the SPI framework */
2132 amba_set_drvdata(adev, pl022);
2133 status = spi_register_master(master);
2136 "probe - problem registering spi master\n");
2137 goto err_spi_register;
2139 dev_dbg(dev, "probe succeeded\n");
2141 * Disable the silicon block pclk and any voltage domain and just
2142 * power it up and clock it when it's needed
2144 amba_pclk_disable(adev);
2145 amba_vcore_disable(adev);
2151 destroy_queue(pl022);
2152 pl022_dma_remove(pl022);
2154 free_irq(adev->irq[0], pl022);
2156 clk_put(pl022->clk);
2158 iounmap(pl022->virtbase);
2160 amba_release_regions(adev);
2162 spi_master_put(master);
2168 static int __devexit
2169 pl022_remove(struct amba_device *adev)
2171 struct pl022 *pl022 = amba_get_drvdata(adev);
2176 /* Remove the queue */
2177 status = destroy_queue(pl022);
2180 "queue remove failed (%d)\n", status);
2183 load_ssp_default_config(pl022);
2184 pl022_dma_remove(pl022);
2185 free_irq(adev->irq[0], pl022);
2186 clk_disable(pl022->clk);
2187 clk_put(pl022->clk);
2188 iounmap(pl022->virtbase);
2189 amba_release_regions(adev);
2190 tasklet_disable(&pl022->pump_transfers);
2191 spi_unregister_master(pl022->master);
2192 spi_master_put(pl022->master);
2193 amba_set_drvdata(adev, NULL);
2194 dev_dbg(&adev->dev, "remove succeeded\n");
2199 static int pl022_suspend(struct amba_device *adev, pm_message_t state)
2201 struct pl022 *pl022 = amba_get_drvdata(adev);
2204 status = stop_queue(pl022);
2206 dev_warn(&adev->dev, "suspend cannot stop queue\n");
2210 amba_vcore_enable(adev);
2211 amba_pclk_enable(adev);
2212 load_ssp_default_config(pl022);
2213 amba_pclk_disable(adev);
2214 amba_vcore_disable(adev);
2215 dev_dbg(&adev->dev, "suspended\n");
2219 static int pl022_resume(struct amba_device *adev)
2221 struct pl022 *pl022 = amba_get_drvdata(adev);
2224 /* Start the queue running */
2225 status = start_queue(pl022);
2227 dev_err(&adev->dev, "problem starting queue (%d)\n", status);
2229 dev_dbg(&adev->dev, "resumed\n");
2234 #define pl022_suspend NULL
2235 #define pl022_resume NULL
2236 #endif /* CONFIG_PM */
2238 static struct vendor_data vendor_arm = {
2242 .extended_cr = false,
2248 static struct vendor_data vendor_st = {
2252 .extended_cr = true,
2257 static struct vendor_data vendor_st_pl023 = {
2261 .extended_cr = true,
2266 static struct vendor_data vendor_db5500_pl023 = {
2270 .extended_cr = true,
2275 static struct amba_id pl022_ids[] = {
2278 * ARM PL022 variant, this has a 16bit wide
2279 * and 8 locations deep TX/RX FIFO
2283 .data = &vendor_arm,
2287 * ST Micro derivative, this has 32bit wide
2288 * and 32 locations deep TX/RX FIFO
2296 * ST-Ericsson derivative "PL023" (this is not
2297 * an official ARM number), this is a PL022 SSP block
2298 * stripped to SPI mode only, it has 32bit wide
2299 * and 32 locations deep TX/RX FIFO but no extended
2304 .data = &vendor_st_pl023,
2309 .data = &vendor_db5500_pl023,
2314 static struct amba_driver pl022_driver = {
2316 .name = "ssp-pl022",
2318 .id_table = pl022_ids,
2319 .probe = pl022_probe,
2320 .remove = __devexit_p(pl022_remove),
2321 .suspend = pl022_suspend,
2322 .resume = pl022_resume,
2326 static int __init pl022_init(void)
2328 return amba_driver_register(&pl022_driver);
2331 subsys_initcall(pl022_init);
2333 static void __exit pl022_exit(void)
2335 amba_driver_unregister(&pl022_driver);
2338 module_exit(pl022_exit);
2340 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2341 MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2342 MODULE_LICENSE("GPL");