4 bool "Enable Driver Model for SPI drivers"
7 Enable driver model for SPI. The SPI slave interface
8 (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
9 the SPI uclass. Drivers provide methods to access the SPI
10 buses that they control. The uclass interface is defined in
11 include/spi.h. The existing spi_slave structure is attached
12 as 'parent data' to every slave on each bus. Slaves
13 typically use driver-private data instead of extending the
19 bool "Altera SPI driver"
21 Enable the Altera SPI driver. This driver can be used to
22 access the SPI NOR flash on platforms embedding this Altera
23 IP core. Please find details on the "Embedded Peripherals IP
24 User Guide" of Altera.
27 bool "Atheros SPI driver"
30 Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used
31 to access SPI NOR flash and other SPI peripherals. This driver
32 uses driver model and requires a device tree binding to operate.
33 please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
36 bool "Cadence QSPI driver"
38 Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
39 used to access the SPI NOR flash on platforms embedding this
43 bool "Designware SPI driver"
45 Enable the Designware SPI driver. This driver can be used to
46 access the SPI NOR flash on platforms embedding this Designware
50 bool "Samsung Exynos SPI driver"
52 Enable the Samsung Exynos SPI driver. This driver can be used to
53 access the SPI NOR flash on platforms embedding this Samsung
57 bool "Freescale DSPI driver"
59 Enable the Freescale DSPI driver. This driver can be used to
60 access the SPI NOR flash and SPI Data flash on platforms embedding
61 this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
65 bool "Freescale QSPI driver"
67 Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
68 used to access the SPI NOR flash on platforms embedding this
72 bool "Intel ICH SPI driver"
74 Enable the Intel ICH SPI driver. This driver can be used to
75 access the SPI NOR flash on platforms embedding this Intel
79 bool "Microchip PIC32 SPI driver"
82 Enable the Microchip PIC32 SPI driver. This driver can be used
83 to access the SPI NOR flash, MMC-over-SPI on platforms based on
84 Microchip PIC32 family devices.
87 bool "Rockchip SPI driver"
89 Enable the Rockchip SPI driver, used to access SPI NOR flash and
90 other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs.
91 This uses driver model and requires a device tree binding to
95 bool "Sandbox SPI driver"
96 depends on SANDBOX && DM
98 Enable SPI support for sandbox. This is an emulation of a real SPI
99 bus. Devices can be attached to the bus using the device tree
100 which specifies the driver to use. As an example, see this device
101 tree fragment from sandbox.dts. It shows that the SPI bus has a
102 single flash device on chip select 0 which is emulated by the driver
103 for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c.
106 #address-cells = <1>;
109 compatible = "sandbox,spi";
110 cs-gpios = <0>, <&gpio_a 0>;
113 compatible = "spansion,m25p16", "sandbox,spi-flash";
114 spi-max-frequency = <40000000>;
115 sandbox,filename = "spi.bin";
120 bool "nVidia Tegra114 SPI driver"
122 Enable the nVidia Tegra114 SPI driver. This driver can be used to
123 access the SPI NOR flash on platforms embedding this nVidia Tegra114
126 This controller is different than the older SoCs SPI controller and
127 also register interface get changed with this controller.
129 config TEGRA20_SFLASH
130 bool "nVidia Tegra20 Serial Flash controller driver"
132 Enable the nVidia Tegra20 Serial Flash controller driver. This driver
133 can be used to access the SPI NOR flash on platforms embedding this
134 nVidia Tegra20 IP core.
137 bool "nVidia Tegra20/Tegra30 SLINK driver"
139 Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can
140 be used to access the SPI NOR flash on platforms embedding this
141 nVidia Tegra20/Tegra30 IP cores.
144 bool "nVidia Tegra210 QSPI driver"
146 Enable the Tegra Quad-SPI (QSPI) driver for T210. This driver
147 be used to access SPI chips on platforms embedding this
148 NVIDIA Tegra210 IP core.
151 bool "Xilinx SPI driver"
153 Enable the Xilinx SPI driver from the Xilinx EDK. This SPI
154 controller support 8 bit SPI transfers only, with or w/o FIFO.
155 For more info on Xilinx SPI Register Definitions and Overview
156 see driver file - drivers/spi/xilinx_spi.c
159 bool "Zynq SPI driver"
160 depends on ARCH_ZYNQ || ARCH_ZYNQMP
162 Enable the Zynq SPI driver. This driver can be used to
163 access the SPI NOR flash on platforms embedding this Zynq
167 bool "Zynq QSPI driver"
170 Enable the Zynq Quad-SPI (QSPI) driver. This driver can be
171 used to access the SPI NOR flash on platforms embedding this
172 Zynq QSPI IP core. This IP is used to connect the flash in
173 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
176 bool "McSPI driver for OMAP"
178 SPI master controller for OMAP24XX and later Multichannel SPI
179 (McSPI). This driver be used to access SPI chips on platforms
180 embedding this OMAP3 McSPI IP core.
185 bool "Freescale eSPI driver"
187 Enable the Freescale eSPI driver. This driver can be used to
188 access the SPI interface and SPI NOR flash on platforms embedding
189 this Freescale eSPI IP core.
192 bool "TI QSPI driver"
194 Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
195 This driver support spi flash single, quad and memory reads.
197 endmenu # menu "SPI Support"