drivers/soundwire/qcom.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2019, Linaro Limited
   3
   4 #include <linux/clk.h>
   5 #include <linux/completion.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/io.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_irq.h>
  12 #include <linux/of_device.h>
  13 #include <linux/regmap.h>
  14 #include <linux/slab.h>
  15 #include <linux/slimbus.h>
  16 #include <linux/soundwire/sdw.h>
  17 #include <linux/soundwire/sdw_registers.h>
  18 #include <sound/pcm_params.h>
  19 #include <sound/soc.h>
  20 #include "bus.h"
  21
  22 #define SWRM_COMP_HW_VERSION                                    0x00
  23 #define SWRM_COMP_CFG_ADDR                                      0x04
  24 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK                    BIT(1)
  25 #define SWRM_COMP_CFG_ENABLE_MSK                                BIT(0)
  26 #define SWRM_COMP_PARAMS                                        0x100
  27 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH                          GENMASK(14, 10)
  28 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH                          GENMASK(19, 15)
  29 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK                        GENMASK(4, 0)
  30 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK                         GENMASK(9, 5)
  31 #define SWRM_INTERRUPT_STATUS                                   0x200
  32 #define SWRM_INTERRUPT_STATUS_RMSK                              GENMASK(16, 0)
  33 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ                    BIT(0)
  34 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED                BIT(1)
  35 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS          BIT(2)
  36 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET                  BIT(3)
  37 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  BIT(4)
  38 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 BIT(5)
  39 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW              BIT(6)
  40 #define SWRM_INTERRUPT_STATUS_CMD_ERROR                         BIT(7)
  41 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION               BIT(8)
  42 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH         BIT(9)
  43 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           BIT(10)
  44 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2             BIT(13)
  45 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2              BIT(14)
  46 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP               BIT(16)
  47 #define SWRM_INTERRUPT_MAX                                      17
  48 #define SWRM_INTERRUPT_MASK_ADDR                                0x204
  49 #define SWRM_INTERRUPT_CLEAR                                    0x208
  50 #define SWRM_INTERRUPT_CPU_EN                                   0x210
  51 #define SWRM_CMD_FIFO_WR_CMD                                    0x300
  52 #define SWRM_CMD_FIFO_RD_CMD                                    0x304
  53 #define SWRM_CMD_FIFO_CMD                                       0x308
  54 #define SWRM_CMD_FIFO_FLUSH                                     0x1
  55 #define SWRM_CMD_FIFO_STATUS                                    0x30C
  56 #define SWRM_RD_CMD_FIFO_CNT_MASK                               GENMASK(20, 16)
  57 #define SWRM_WR_CMD_FIFO_CNT_MASK                               GENMASK(12, 8)
  58 #define SWRM_CMD_FIFO_CFG_ADDR                                  0x314
  59 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE                        BIT(31)
  60 #define SWRM_RD_WR_CMD_RETRIES                                  0x7
  61 #define SWRM_CMD_FIFO_RD_FIFO_ADDR                              0x318
  62 #define SWRM_RD_FIFO_CMD_ID_MASK                                GENMASK(11, 8)
  63 #define SWRM_ENUMERATOR_CFG_ADDR                                0x500
  64 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m)               (0x530 + 0x8 * (m))
  65 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m)               (0x534 + 0x8 * (m))
  66 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m)                (0x101C + 0x40 * (m))
  67 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK                  GENMASK(2, 0)
  68 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK                  GENMASK(7, 3)
  69 #define SWRM_MCP_BUS_CTRL                                       0x1044
  70 #define SWRM_MCP_BUS_CLK_START                                  BIT(1)
  71 #define SWRM_MCP_CFG_ADDR                                       0x1048
  72 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK               GENMASK(21, 17)
  73 #define SWRM_DEF_CMD_NO_PINGS                                   0x1f
  74 #define SWRM_MCP_STATUS                                         0x104C
  75 #define SWRM_MCP_STATUS_BANK_NUM_MASK                           BIT(0)
  76 #define SWRM_MCP_SLV_STATUS                                     0x1090
  77 #define SWRM_MCP_SLV_STATUS_MASK                                GENMASK(1, 0)
  78 #define SWRM_MCP_SLV_STATUS_SZ                                  2
  79 #define SWRM_DP_PORT_CTRL_BANK(n, m)    (0x1124 + 0x100 * (n - 1) + 0x40 * m)
  80 #define SWRM_DP_PORT_CTRL_2_BANK(n, m)  (0x1128 + 0x100 * (n - 1) + 0x40 * m)
  81 #define SWRM_DP_BLOCK_CTRL_1(n)         (0x112C + 0x100 * (n - 1))
  82 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m)  (0x1130 + 0x100 * (n - 1) + 0x40 * m)
  83 #define SWRM_DP_PORT_HCTRL_BANK(n, m)   (0x1134 + 0x100 * (n - 1) + 0x40 * m)
  84 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m)  (0x1138 + 0x100 * (n - 1) + 0x40 * m)
  85 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n)   (0x1054 + 0x100 * (n - 1))
  86
  87 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT                          0x18
  88 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT                          0x10
  89 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT                          0x08
  90 #define SWRM_AHB_BRIDGE_WR_DATA_0                               0xc85
  91 #define SWRM_AHB_BRIDGE_WR_ADDR_0                               0xc89
  92 #define SWRM_AHB_BRIDGE_RD_ADDR_0                               0xc8d
  93 #define SWRM_AHB_BRIDGE_RD_DATA_0                               0xc91
  94
  95 #define SWRM_REG_VAL_PACK(data, dev, id, reg)   \
  96                         ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
  97
  98 #define SWRM_SPECIAL_CMD_ID     0xF
  99 #define MAX_FREQ_NUM            1
 100 #define TIMEOUT_MS              100
 101 #define QCOM_SWRM_MAX_RD_LEN    0x1
 102 #define QCOM_SDW_MAX_PORTS      14
 103 #define DEFAULT_CLK_FREQ        9600000
 104 #define SWRM_MAX_DAIS           0xF
 105 #define SWR_INVALID_PARAM 0xFF
 106 #define SWR_HSTOP_MAX_VAL 0xF
 107 #define SWR_HSTART_MIN_VAL 0x0
 108 #define SWR_BROADCAST_CMD_ID    0x0F
 109 #define SWR_MAX_CMD_ID  14
 110 #define MAX_FIFO_RD_RETRY 3
 111 #define SWR_OVERFLOW_RETRY_COUNT 30
 112
 113 struct qcom_swrm_port_config {
 114         u8 si;
 115         u8 off1;
 116         u8 off2;
 117         u8 bp_mode;
 118         u8 hstart;
 119         u8 hstop;
 120         u8 word_length;
 121         u8 blk_group_count;
 122         u8 lane_control;
 123 };
 124
 125 struct qcom_swrm_ctrl {
 126         struct sdw_bus bus;
 127         struct device *dev;
 128         struct regmap *regmap;
 129         void __iomem *mmio;
 130         struct completion broadcast;
 131         struct completion enumeration;
 132         struct work_struct slave_work;
 133         /* Port alloc/free lock */
 134         struct mutex port_lock;
 135         struct clk *hclk;
 136         u8 wr_cmd_id;
 137         u8 rd_cmd_id;
 138         int irq;
 139         unsigned int version;
 140         int num_din_ports;
 141         int num_dout_ports;
 142         int cols_index;
 143         int rows_index;
 144         unsigned long dout_port_mask;
 145         unsigned long din_port_mask;
 146         u32 intr_mask;
 147         u8 rcmd_id;
 148         u8 wcmd_id;
 149         struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS];
 150         struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
 151         enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
 152         int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
 153         int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
 154         u32 slave_status;
 155         u32 wr_fifo_depth;
 156         u32 rd_fifo_depth;
 157 };
 158
 159 struct qcom_swrm_data {
 160         u32 default_cols;
 161         u32 default_rows;
 162 };
 163
 164 static struct qcom_swrm_data swrm_v1_3_data = {
 165         .default_rows = 48,
 166         .default_cols = 16,
 167 };
 168
 169 static struct qcom_swrm_data swrm_v1_5_data = {
 170         .default_rows = 50,
 171         .default_cols = 16,
 172 };
 173
 174 #define to_qcom_sdw(b)  container_of(b, struct qcom_swrm_ctrl, bus)
 175
 176 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 177                                   u32 *val)
 178 {
 179         struct regmap *wcd_regmap = ctrl->regmap;
 180         int ret;
 181
 182         /* pg register + offset */
 183         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
 184                           (u8 *)&reg, 4);
 185         if (ret < 0)
 186                 return SDW_CMD_FAIL;
 187
 188         ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
 189                                val, 4);
 190         if (ret < 0)
 191                 return SDW_CMD_FAIL;
 192
 193         return SDW_CMD_OK;
 194 }
 195
 196 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
 197                                    int reg, int val)
 198 {
 199         struct regmap *wcd_regmap = ctrl->regmap;
 200         int ret;
 201         /* pg register + offset */
 202         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
 203                           (u8 *)&val, 4);
 204         if (ret)
 205                 return SDW_CMD_FAIL;
 206
 207         /* write address register */
 208         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
 209                           (u8 *)&reg, 4);
 210         if (ret)
 211                 return SDW_CMD_FAIL;
 212
 213         return SDW_CMD_OK;
 214 }
 215
 216 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 217                                   u32 *val)
 218 {
 219         *val = readl(ctrl->mmio + reg);
 220         return SDW_CMD_OK;
 221 }
 222
 223 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
 224                                    int val)
 225 {
 226         writel(val, ctrl->mmio + reg);
 227         return SDW_CMD_OK;
 228 }
 229
 230 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
 231                                    u8 dev_addr, u16 reg_addr)
 232 {
 233         u32 val;
 234         u8 id = *cmd_id;
 235
 236         if (id != SWR_BROADCAST_CMD_ID) {
 237                 if (id < SWR_MAX_CMD_ID)
 238                         id += 1;
 239                 else
 240                         id = 0;
 241                 *cmd_id = id;
 242         }
 243         val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
 244
 245         return val;
 246 }
 247
 248 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm)
 249 {
 250         u32 fifo_outstanding_data, value;
 251         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 252
 253         do {
 254                 /* Check for fifo underflow during read */
 255                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 256                 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
 257
 258                 /* Check if read data is available in read fifo */
 259                 if (fifo_outstanding_data > 0)
 260                         return 0;
 261
 262                 usleep_range(500, 510);
 263         } while (fifo_retry_count--);
 264
 265         if (fifo_outstanding_data == 0) {
 266                 dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__);
 267                 return -EIO;
 268         }
 269
 270         return 0;
 271 }
 272
 273 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm)
 274 {
 275         u32 fifo_outstanding_cmds, value;
 276         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 277
 278         do {
 279                 /* Check for fifo overflow during write */
 280                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 281                 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
 282
 283                 /* Check for space in write fifo before writing */
 284                 if (fifo_outstanding_cmds < swrm->wr_fifo_depth)
 285                         return 0;
 286
 287                 usleep_range(500, 510);
 288         } while (fifo_retry_count--);
 289
 290         if (fifo_outstanding_cmds == swrm->wr_fifo_depth) {
 291                 dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__);
 292                 return -EIO;
 293         }
 294
 295         return 0;
 296 }
 297
 298 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data,
 299                                      u8 dev_addr, u16 reg_addr)
 300 {
 301
 302         u32 val;
 303         int ret = 0;
 304         u8 cmd_id = 0x0;
 305
 306         if (dev_addr == SDW_BROADCAST_DEV_NUM) {
 307                 cmd_id = SWR_BROADCAST_CMD_ID;
 308                 val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
 309                                               dev_addr, reg_addr);
 310         } else {
 311                 val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
 312                                               dev_addr, reg_addr);
 313         }
 314
 315         if (swrm_wait_for_wr_fifo_avail(swrm))
 316                 return SDW_CMD_FAIL_OTHER;
 317
 318         if (cmd_id == SWR_BROADCAST_CMD_ID)
 319                 reinit_completion(&swrm->broadcast);
 320
 321         /* Its assumed that write is okay as we do not get any status back */
 322         swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
 323
 324         /* version 1.3 or less */
 325         if (swrm->version <= 0x01030000)
 326                 usleep_range(150, 155);
 327
 328         if (cmd_id == SWR_BROADCAST_CMD_ID) {
 329                 /*
 330                  * sleep for 10ms for MSM soundwire variant to allow broadcast
 331                  * command to complete.
 332                  */
 333                 ret = wait_for_completion_timeout(&swrm->broadcast,
 334                                                   msecs_to_jiffies(TIMEOUT_MS));
 335                 if (!ret)
 336                         ret = SDW_CMD_IGNORED;
 337                 else
 338                         ret = SDW_CMD_OK;
 339
 340         } else {
 341                 ret = SDW_CMD_OK;
 342         }
 343         return ret;
 344 }
 345
 346 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm,
 347                                      u8 dev_addr, u16 reg_addr,
 348                                      u32 len, u8 *rval)
 349 {
 350         u32 cmd_data, cmd_id, val, retry_attempt = 0;
 351
 352         val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
 353
 354         /*
 355          * Check for outstanding cmd wrt. write fifo depth to avoid
 356          * overflow as read will also increase write fifo cnt.
 357          */
 358         swrm_wait_for_wr_fifo_avail(swrm);
 359
 360         /* wait for FIFO RD to complete to avoid overflow */
 361         usleep_range(100, 105);
 362         swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
 363         /* wait for FIFO RD CMD complete to avoid overflow */
 364         usleep_range(250, 255);
 365
 366         if (swrm_wait_for_rd_fifo_avail(swrm))
 367                 return SDW_CMD_FAIL_OTHER;
 368
 369         do {
 370                 swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
 371                 rval[0] = cmd_data & 0xFF;
 372                 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
 373
 374                 if (cmd_id != swrm->rcmd_id) {
 375                         if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
 376                                 /* wait 500 us before retry on fifo read failure */
 377                                 usleep_range(500, 505);
 378                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD,
 379                                                 SWRM_CMD_FIFO_FLUSH);
 380                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
 381                         }
 382                         retry_attempt++;
 383                 } else {
 384                         return SDW_CMD_OK;
 385                 }
 386
 387         } while (retry_attempt < MAX_FIFO_RD_RETRY);
 388
 389         dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
 390                 dev_num: 0x%x, cmd_data: 0x%x\n",
 391                 reg_addr, swrm->rcmd_id, dev_addr, cmd_data);
 392
 393         return SDW_CMD_IGNORED;
 394 }
 395
 396 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
 397 {
 398         u32 val, status;
 399         int dev_num;
 400
 401         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 402
 403         for (dev_num = 0; dev_num <= SDW_MAX_DEVICES; dev_num++) {
 404                 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
 405
 406                 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
 407                         ctrl->status[dev_num] = status;
 408                         return dev_num;
 409                 }
 410         }
 411
 412         return -EINVAL;
 413 }
 414
 415 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
 416 {
 417         u32 val;
 418         int i;
 419
 420         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 421         ctrl->slave_status = val;
 422
 423         for (i = 0; i <= SDW_MAX_DEVICES; i++) {
 424                 u32 s;
 425
 426                 s = (val >> (i * 2));
 427                 s &= SWRM_MCP_SLV_STATUS_MASK;
 428                 ctrl->status[i] = s;
 429         }
 430 }
 431
 432 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
 433                                         struct sdw_slave *slave, int devnum)
 434 {
 435         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 436         u32 status;
 437
 438         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
 439         status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
 440         status &= SWRM_MCP_SLV_STATUS_MASK;
 441
 442         if (status == SDW_SLAVE_ATTACHED) {
 443                 if (slave)
 444                         slave->dev_num = devnum;
 445                 mutex_lock(&bus->bus_lock);
 446                 set_bit(devnum, bus->assigned);
 447                 mutex_unlock(&bus->bus_lock);
 448         }
 449 }
 450
 451 static int qcom_swrm_enumerate(struct sdw_bus *bus)
 452 {
 453         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 454         struct sdw_slave *slave, *_s;
 455         struct sdw_slave_id id;
 456         u32 val1, val2;
 457         bool found;
 458         u64 addr;
 459         int i;
 460         char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
 461
 462         for (i = 1; i <= SDW_MAX_DEVICES; i++) {
 463                 /* do not continue if the status is Not Present  */
 464                 if (!ctrl->status[i])
 465                         continue;
 466
 467                 /*SCP_Devid5 - Devid 4*/
 468                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
 469
 470                 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
 471                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
 472
 473                 if (!val1 && !val2)
 474                         break;
 475
 476                 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
 477                         ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
 478                         ((u64)buf1[0] << 40);
 479
 480                 sdw_extract_slave_id(bus, addr, &id);
 481                 found = false;
 482                 /* Now compare with entries */
 483                 list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
 484                         if (sdw_compare_devid(slave, id) == 0) {
 485                                 qcom_swrm_set_slave_dev_num(bus, slave, i);
 486                                 found = true;
 487                                 break;
 488                         }
 489                 }
 490
 491                 if (!found) {
 492                         qcom_swrm_set_slave_dev_num(bus, NULL, i);
 493                         sdw_slave_add(bus, &id, NULL);
 494                 }
 495         }
 496
 497         complete(&ctrl->enumeration);
 498         return 0;
 499 }
 500
 501 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
 502 {
 503         struct qcom_swrm_ctrl *swrm = dev_id;
 504         u32 value, intr_sts, intr_sts_masked, slave_status;
 505         u32 i;
 506         int devnum;
 507         int ret = IRQ_HANDLED;
 508
 509         swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
 510         intr_sts_masked = intr_sts & swrm->intr_mask;
 511
 512         do {
 513                 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
 514                         value = intr_sts_masked & BIT(i);
 515                         if (!value)
 516                                 continue;
 517
 518                         switch (value) {
 519                         case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
 520                                 devnum = qcom_swrm_get_alert_slave_dev_num(swrm);
 521                                 if (devnum < 0) {
 522                                         dev_err_ratelimited(swrm->dev,
 523                                             "no slave alert found.spurious interrupt\n");
 524                                 } else {
 525                                         sdw_handle_slave_status(&swrm->bus, swrm->status);
 526                                 }
 527
 528                                 break;
 529                         case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
 530                         case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
 531                                 dev_err_ratelimited(swrm->dev, "%s: SWR new slave attached\n",
 532                                         __func__);
 533                                 swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status);
 534                                 if (swrm->slave_status == slave_status) {
 535                                         dev_err(swrm->dev, "Slave status not changed %x\n",
 536                                                 slave_status);
 537                                 } else {
 538                                         qcom_swrm_get_device_status(swrm);
 539                                         qcom_swrm_enumerate(&swrm->bus);
 540                                         sdw_handle_slave_status(&swrm->bus, swrm->status);
 541                                 }
 542                                 break;
 543                         case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
 544                                 dev_err_ratelimited(swrm->dev,
 545                                                 "%s: SWR bus clsh detected\n",
 546                                                 __func__);
 547                                 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
 548                                 swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 549                                 break;
 550                         case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
 551                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 552                                 dev_err_ratelimited(swrm->dev,
 553                                         "%s: SWR read FIFO overflow fifo status 0x%x\n",
 554                                         __func__, value);
 555                                 break;
 556                         case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
 557                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 558                                 dev_err_ratelimited(swrm->dev,
 559                                         "%s: SWR read FIFO underflow fifo status 0x%x\n",
 560                                         __func__, value);
 561                                 break;
 562                         case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
 563                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 564                                 dev_err(swrm->dev,
 565                                         "%s: SWR write FIFO overflow fifo status %x\n",
 566                                         __func__, value);
 567                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
 568                                 break;
 569                         case SWRM_INTERRUPT_STATUS_CMD_ERROR:
 570                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 571                                 dev_err_ratelimited(swrm->dev,
 572                                         "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
 573                                         __func__, value);
 574                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
 575                                 break;
 576                         case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
 577                                 dev_err_ratelimited(swrm->dev,
 578                                                 "%s: SWR Port collision detected\n",
 579                                                 __func__);
 580                                 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
 581                                 swrm->reg_write(swrm,
 582                                         SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 583                                 break;
 584                         case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
 585                                 dev_err_ratelimited(swrm->dev,
 586                                         "%s: SWR read enable valid mismatch\n",
 587                                         __func__);
 588                                 swrm->intr_mask &=
 589                                         ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
 590                                 swrm->reg_write(swrm,
 591                                         SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 592                                 break;
 593                         case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
 594                                 complete(&swrm->broadcast);
 595                                 break;
 596                         case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
 597                                 break;
 598                         case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
 599                                 break;
 600                         case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
 601                                 break;
 602                         default:
 603                                 dev_err_ratelimited(swrm->dev,
 604                                                 "%s: SWR unknown interrupt value: %d\n",
 605                                                 __func__, value);
 606                                 ret = IRQ_NONE;
 607                                 break;
 608                         }
 609                 }
 610                 swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts);
 611                 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
 612                 intr_sts_masked = intr_sts & swrm->intr_mask;
 613         } while (intr_sts_masked);
 614
 615         return ret;
 616 }
 617
 618 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
 619 {
 620         u32 val;
 621
 622         /* Clear Rows and Cols */
 623         val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
 624         val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
 625
 626         ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
 627
 628         /* Enable Auto enumeration */
 629         ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
 630
 631         ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
 632         /* Mask soundwire interrupts */
 633         ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
 634                         SWRM_INTERRUPT_STATUS_RMSK);
 635
 636         /* Configure No pings */
 637         ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
 638         u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
 639         ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
 640
 641         ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
 642         /* Configure number of retries of a read/write cmd */
 643         if (ctrl->version > 0x01050001) {
 644                 /* Only for versions >= 1.5.1 */
 645                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 646                                 SWRM_RD_WR_CMD_RETRIES |
 647                                 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
 648         } else {
 649                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 650                                 SWRM_RD_WR_CMD_RETRIES);
 651         }
 652
 653         /* Set IRQ to PULSE */
 654         ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
 655                         SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
 656                         SWRM_COMP_CFG_ENABLE_MSK);
 657
 658         /* enable CPU IRQs */
 659         if (ctrl->mmio) {
 660                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
 661                                 SWRM_INTERRUPT_STATUS_RMSK);
 662         }
 663         ctrl->slave_status = 0;
 664         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
 665         ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
 666         ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
 667
 668         return 0;
 669 }
 670
 671 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
 672                                                     struct sdw_msg *msg)
 673 {
 674         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 675         int ret, i, len;
 676
 677         if (msg->flags == SDW_MSG_FLAG_READ) {
 678                 for (i = 0; i < msg->len;) {
 679                         if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
 680                                 len = msg->len - i;
 681                         else
 682                                 len = QCOM_SWRM_MAX_RD_LEN;
 683
 684                         ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
 685                                                         msg->addr + i, len,
 686                                                        &msg->buf[i]);
 687                         if (ret)
 688                                 return ret;
 689
 690                         i = i + len;
 691                 }
 692         } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
 693                 for (i = 0; i < msg->len; i++) {
 694                         ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
 695                                                         msg->dev_num,
 696                                                        msg->addr + i);
 697                         if (ret)
 698                                 return SDW_CMD_IGNORED;
 699                 }
 700         }
 701
 702         return SDW_CMD_OK;
 703 }
 704
 705 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
 706 {
 707         u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
 708         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 709         u32 val;
 710
 711         ctrl->reg_read(ctrl, reg, &val);
 712
 713         u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
 714         u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
 715
 716         return ctrl->reg_write(ctrl, reg, val);
 717 }
 718
 719 static int qcom_swrm_port_params(struct sdw_bus *bus,
 720                                  struct sdw_port_params *p_params,
 721                                  unsigned int bank)
 722 {
 723         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 724
 725         return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
 726                                p_params->bps - 1);
 727
 728 }
 729
 730 static int qcom_swrm_transport_params(struct sdw_bus *bus,
 731                                       struct sdw_transport_params *params,
 732                                       enum sdw_reg_bank bank)
 733 {
 734         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 735         struct qcom_swrm_port_config *pcfg;
 736         u32 value;
 737         int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
 738         int ret;
 739
 740         pcfg = &ctrl->pconfig[params->port_num];
 741
 742         value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
 743         value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
 744         value |= pcfg->si;
 745
 746         ret = ctrl->reg_write(ctrl, reg, value);
 747         if (ret)
 748                 goto err;
 749
 750         if (pcfg->lane_control != SWR_INVALID_PARAM) {
 751                 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
 752                 value = pcfg->lane_control;
 753                 ret = ctrl->reg_write(ctrl, reg, value);
 754                 if (ret)
 755                         goto err;
 756         }
 757
 758         if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
 759                 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
 760                 value = pcfg->blk_group_count;
 761                 ret = ctrl->reg_write(ctrl, reg, value);
 762                 if (ret)
 763                         goto err;
 764         }
 765
 766         if (pcfg->hstart != SWR_INVALID_PARAM
 767                         && pcfg->hstop != SWR_INVALID_PARAM) {
 768                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
 769                 value = (pcfg->hstop << 4) | pcfg->hstart;
 770                 ret = ctrl->reg_write(ctrl, reg, value);
 771         } else {
 772                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
 773                 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
 774                 ret = ctrl->reg_write(ctrl, reg, value);
 775         }
 776
 777         if (ret)
 778                 goto err;
 779
 780         if (pcfg->bp_mode != SWR_INVALID_PARAM) {
 781                 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
 782                 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
 783         }
 784
 785 err:
 786         return ret;
 787 }
 788
 789 static int qcom_swrm_port_enable(struct sdw_bus *bus,
 790                                  struct sdw_enable_ch *enable_ch,
 791                                  unsigned int bank)
 792 {
 793         u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
 794         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 795         u32 val;
 796
 797         ctrl->reg_read(ctrl, reg, &val);
 798
 799         if (enable_ch->enable)
 800                 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 801         else
 802                 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 803
 804         return ctrl->reg_write(ctrl, reg, val);
 805 }
 806
 807 static const struct sdw_master_port_ops qcom_swrm_port_ops = {
 808         .dpn_set_port_params = qcom_swrm_port_params,
 809         .dpn_set_port_transport_params = qcom_swrm_transport_params,
 810         .dpn_port_enable_ch = qcom_swrm_port_enable,
 811 };
 812
 813 static const struct sdw_master_ops qcom_swrm_ops = {
 814         .xfer_msg = qcom_swrm_xfer_msg,
 815         .pre_bank_switch = qcom_swrm_pre_bank_switch,
 816 };
 817
 818 static int qcom_swrm_compute_params(struct sdw_bus *bus)
 819 {
 820         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 821         struct sdw_master_runtime *m_rt;
 822         struct sdw_slave_runtime *s_rt;
 823         struct sdw_port_runtime *p_rt;
 824         struct qcom_swrm_port_config *pcfg;
 825         struct sdw_slave *slave;
 826         unsigned int m_port;
 827         int i = 1;
 828
 829         list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
 830                 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
 831                         pcfg = &ctrl->pconfig[p_rt->num];
 832                         p_rt->transport_params.port_num = p_rt->num;
 833                         if (pcfg->word_length != SWR_INVALID_PARAM) {
 834                                 sdw_fill_port_params(&p_rt->port_params,
 835                                              p_rt->num,  pcfg->word_length + 1,
 836                                              SDW_PORT_FLOW_MODE_ISOCH,
 837                                              SDW_PORT_DATA_MODE_NORMAL);
 838                         }
 839
 840                 }
 841
 842                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
 843                         slave = s_rt->slave;
 844                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
 845                                 m_port = slave->m_port_map[p_rt->num];
 846                                 /* port config starts at offset 0 so -1 from actual port number */
 847                                 if (m_port)
 848                                         pcfg = &ctrl->pconfig[m_port];
 849                                 else
 850                                         pcfg = &ctrl->pconfig[i];
 851                                 p_rt->transport_params.port_num = p_rt->num;
 852                                 p_rt->transport_params.sample_interval =
 853                                         pcfg->si + 1;
 854                                 p_rt->transport_params.offset1 = pcfg->off1;
 855                                 p_rt->transport_params.offset2 = pcfg->off2;
 856                                 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
 857                                 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
 858
 859                                 p_rt->transport_params.hstart = pcfg->hstart;
 860                                 p_rt->transport_params.hstop = pcfg->hstop;
 861                                 p_rt->transport_params.lane_ctrl = pcfg->lane_control;
 862                                 if (pcfg->word_length != SWR_INVALID_PARAM) {
 863                                         sdw_fill_port_params(&p_rt->port_params,
 864                                                      p_rt->num,
 865                                                      pcfg->word_length + 1,
 866                                                      SDW_PORT_FLOW_MODE_ISOCH,
 867                                                      SDW_PORT_DATA_MODE_NORMAL);
 868                                 }
 869                                 i++;
 870                         }
 871                 }
 872         }
 873
 874         return 0;
 875 }
 876
 877 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
 878         DEFAULT_CLK_FREQ,
 879 };
 880
 881 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
 882                                         struct sdw_stream_runtime *stream)
 883 {
 884         struct sdw_master_runtime *m_rt;
 885         struct sdw_port_runtime *p_rt;
 886         unsigned long *port_mask;
 887
 888         mutex_lock(&ctrl->port_lock);
 889
 890         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
 891                 if (m_rt->direction == SDW_DATA_DIR_RX)
 892                         port_mask = &ctrl->dout_port_mask;
 893                 else
 894                         port_mask = &ctrl->din_port_mask;
 895
 896                 list_for_each_entry(p_rt, &m_rt->port_list, port_node)
 897                         clear_bit(p_rt->num, port_mask);
 898         }
 899
 900         mutex_unlock(&ctrl->port_lock);
 901 }
 902
 903 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
 904                                         struct sdw_stream_runtime *stream,
 905                                        struct snd_pcm_hw_params *params,
 906                                        int direction)
 907 {
 908         struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
 909         struct sdw_stream_config sconfig;
 910         struct sdw_master_runtime *m_rt;
 911         struct sdw_slave_runtime *s_rt;
 912         struct sdw_port_runtime *p_rt;
 913         struct sdw_slave *slave;
 914         unsigned long *port_mask;
 915         int i, maxport, pn, nports = 0, ret = 0;
 916         unsigned int m_port;
 917
 918         mutex_lock(&ctrl->port_lock);
 919         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
 920                 if (m_rt->direction == SDW_DATA_DIR_RX) {
 921                         maxport = ctrl->num_dout_ports;
 922                         port_mask = &ctrl->dout_port_mask;
 923                 } else {
 924                         maxport = ctrl->num_din_ports;
 925                         port_mask = &ctrl->din_port_mask;
 926                 }
 927
 928                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
 929                         slave = s_rt->slave;
 930                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
 931                                 m_port = slave->m_port_map[p_rt->num];
 932                                 /* Port numbers start from 1 - 14*/
 933                                 if (m_port)
 934                                         pn = m_port;
 935                                 else
 936                                         pn = find_first_zero_bit(port_mask, maxport);
 937
 938                                 if (pn > maxport) {
 939                                         dev_err(ctrl->dev, "All ports busy\n");
 940                                         ret = -EBUSY;
 941                                         goto err;
 942                                 }
 943                                 set_bit(pn, port_mask);
 944                                 pconfig[nports].num = pn;
 945                                 pconfig[nports].ch_mask = p_rt->ch_mask;
 946                                 nports++;
 947                         }
 948                 }
 949         }
 950
 951         if (direction == SNDRV_PCM_STREAM_CAPTURE)
 952                 sconfig.direction = SDW_DATA_DIR_TX;
 953         else
 954                 sconfig.direction = SDW_DATA_DIR_RX;
 955
 956         /* hw parameters wil be ignored as we only support PDM */
 957         sconfig.ch_count = 1;
 958         sconfig.frame_rate = params_rate(params);
 959         sconfig.type = stream->type;
 960         sconfig.bps = 1;
 961         sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
 962                               nports, stream);
 963 err:
 964         if (ret) {
 965                 for (i = 0; i < nports; i++)
 966                         clear_bit(pconfig[i].num, port_mask);
 967         }
 968
 969         mutex_unlock(&ctrl->port_lock);
 970
 971         return ret;
 972 }
 973
 974 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
 975                                struct snd_pcm_hw_params *params,
 976                               struct snd_soc_dai *dai)
 977 {
 978         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
 979         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
 980         int ret;
 981
 982         ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
 983                                            substream->stream);
 984         if (ret)
 985                 qcom_swrm_stream_free_ports(ctrl, sruntime);
 986
 987         return ret;
 988 }
 989
 990 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
 991                              struct snd_soc_dai *dai)
 992 {
 993         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
 994         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
 995
 996         qcom_swrm_stream_free_ports(ctrl, sruntime);
 997         sdw_stream_remove_master(&ctrl->bus, sruntime);
 998
 999         return 0;
1000 }
1001
1002 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
1003                                     void *stream, int direction)
1004 {
1005         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1006
1007         ctrl->sruntime[dai->id] = stream;
1008
1009         return 0;
1010 }
1011
1012 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
1013 {
1014         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1015
1016         return ctrl->sruntime[dai->id];
1017 }
1018
1019 static int qcom_swrm_startup(struct snd_pcm_substream *substream,
1020                              struct snd_soc_dai *dai)
1021 {
1022         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1023         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1024         struct sdw_stream_runtime *sruntime;
1025         struct snd_soc_dai *codec_dai;
1026         int ret, i;
1027
1028         sruntime = sdw_alloc_stream(dai->name);
1029         if (!sruntime)
1030                 return -ENOMEM;
1031
1032         ctrl->sruntime[dai->id] = sruntime;
1033
1034         for_each_rtd_codec_dais(rtd, i, codec_dai) {
1035                 ret = snd_soc_dai_set_sdw_stream(codec_dai, sruntime,
1036                                                  substream->stream);
1037                 if (ret < 0 && ret != -ENOTSUPP) {
1038                         dev_err(dai->dev, "Failed to set sdw stream on %s\n",
1039                                 codec_dai->name);
1040                         sdw_release_stream(sruntime);
1041                         return ret;
1042                 }
1043         }
1044
1045         return 0;
1046 }
1047
1048 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
1049                                struct snd_soc_dai *dai)
1050 {
1051         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1052
1053         sdw_release_stream(ctrl->sruntime[dai->id]);
1054         ctrl->sruntime[dai->id] = NULL;
1055 }
1056
1057 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
1058         .hw_params = qcom_swrm_hw_params,
1059         .hw_free = qcom_swrm_hw_free,
1060         .startup = qcom_swrm_startup,
1061         .shutdown = qcom_swrm_shutdown,
1062         .set_sdw_stream = qcom_swrm_set_sdw_stream,
1063         .get_sdw_stream = qcom_swrm_get_sdw_stream,
1064 };
1065
1066 static const struct snd_soc_component_driver qcom_swrm_dai_component = {
1067         .name = "soundwire",
1068 };
1069
1070 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1071 {
1072         int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1073         struct snd_soc_dai_driver *dais;
1074         struct snd_soc_pcm_stream *stream;
1075         struct device *dev = ctrl->dev;
1076         int i;
1077
1078         /* PDM dais are only tested for now */
1079         dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
1080         if (!dais)
1081                 return -ENOMEM;
1082
1083         for (i = 0; i < num_dais; i++) {
1084                 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
1085                 if (!dais[i].name)
1086                         return -ENOMEM;
1087
1088                 if (i < ctrl->num_dout_ports)
1089                         stream = &dais[i].playback;
1090                 else
1091                         stream = &dais[i].capture;
1092
1093                 stream->channels_min = 1;
1094                 stream->channels_max = 1;
1095                 stream->rates = SNDRV_PCM_RATE_48000;
1096                 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
1097
1098                 dais[i].ops = &qcom_swrm_pdm_dai_ops;
1099                 dais[i].id = i;
1100         }
1101
1102         return devm_snd_soc_register_component(ctrl->dev,
1103                                                 &qcom_swrm_dai_component,
1104                                                 dais, num_dais);
1105 }
1106
1107 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1108 {
1109         struct device_node *np = ctrl->dev->of_node;
1110         u8 off1[QCOM_SDW_MAX_PORTS];
1111         u8 off2[QCOM_SDW_MAX_PORTS];
1112         u8 si[QCOM_SDW_MAX_PORTS];
1113         u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
1114         u8 hstart[QCOM_SDW_MAX_PORTS];
1115         u8 hstop[QCOM_SDW_MAX_PORTS];
1116         u8 word_length[QCOM_SDW_MAX_PORTS];
1117         u8 blk_group_count[QCOM_SDW_MAX_PORTS];
1118         u8 lane_control[QCOM_SDW_MAX_PORTS];
1119         int i, ret, nports, val;
1120
1121         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1122
1123         ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1124         ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1125
1126         ret = of_property_read_u32(np, "qcom,din-ports", &val);
1127         if (ret)
1128                 return ret;
1129
1130         if (val > ctrl->num_din_ports)
1131                 return -EINVAL;
1132
1133         ctrl->num_din_ports = val;
1134
1135         ret = of_property_read_u32(np, "qcom,dout-ports", &val);
1136         if (ret)
1137                 return ret;
1138
1139         if (val > ctrl->num_dout_ports)
1140                 return -EINVAL;
1141
1142         ctrl->num_dout_ports = val;
1143
1144         nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1145         /* Valid port numbers are from 1-14, so mask out port 0 explicitly */
1146         set_bit(0, &ctrl->dout_port_mask);
1147         set_bit(0, &ctrl->din_port_mask);
1148
1149         ret = of_property_read_u8_array(np, "qcom,ports-offset1",
1150                                         off1, nports);
1151         if (ret)
1152                 return ret;
1153
1154         ret = of_property_read_u8_array(np, "qcom,ports-offset2",
1155                                         off2, nports);
1156         if (ret)
1157                 return ret;
1158
1159         ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
1160                                         si, nports);
1161         if (ret)
1162                 return ret;
1163
1164         ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
1165                                         bp_mode, nports);
1166         if (ret) {
1167                 u32 version;
1168
1169                 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &version);
1170
1171                 if (version <= 0x01030000)
1172                         memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1173                 else
1174                         return ret;
1175         }
1176
1177         memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1178         of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports);
1179
1180         memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1181         of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports);
1182
1183         memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1184         of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports);
1185
1186         memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1187         of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports);
1188
1189         memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1190         of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports);
1191
1192         for (i = 0; i < nports; i++) {
1193                 /* Valid port number range is from 1-14 */
1194                 ctrl->pconfig[i + 1].si = si[i];
1195                 ctrl->pconfig[i + 1].off1 = off1[i];
1196                 ctrl->pconfig[i + 1].off2 = off2[i];
1197                 ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
1198                 ctrl->pconfig[i + 1].hstart = hstart[i];
1199                 ctrl->pconfig[i + 1].hstop = hstop[i];
1200                 ctrl->pconfig[i + 1].word_length = word_length[i];
1201                 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
1202                 ctrl->pconfig[i + 1].lane_control = lane_control[i];
1203         }
1204
1205         return 0;
1206 }
1207
1208 static int qcom_swrm_probe(struct platform_device *pdev)
1209 {
1210         struct device *dev = &pdev->dev;
1211         struct sdw_master_prop *prop;
1212         struct sdw_bus_params *params;
1213         struct qcom_swrm_ctrl *ctrl;
1214         const struct qcom_swrm_data *data;
1215         int ret;
1216         u32 val;
1217
1218         ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1219         if (!ctrl)
1220                 return -ENOMEM;
1221
1222         data = of_device_get_match_data(dev);
1223         ctrl->rows_index = sdw_find_row_index(data->default_rows);
1224         ctrl->cols_index = sdw_find_col_index(data->default_cols);
1225 #if IS_REACHABLE(CONFIG_SLIMBUS)
1226         if (dev->parent->bus == &slimbus_bus) {
1227 #else
1228         if (false) {
1229 #endif
1230                 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1231                 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1232                 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1233                 if (!ctrl->regmap)
1234                         return -EINVAL;
1235         } else {
1236                 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1237                 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1238                 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1239                 if (IS_ERR(ctrl->mmio))
1240                         return PTR_ERR(ctrl->mmio);
1241         }
1242
1243         ctrl->irq = of_irq_get(dev->of_node, 0);
1244         if (ctrl->irq < 0) {
1245                 ret = ctrl->irq;
1246                 goto err_init;
1247         }
1248
1249         ctrl->hclk = devm_clk_get(dev, "iface");
1250         if (IS_ERR(ctrl->hclk)) {
1251                 ret = PTR_ERR(ctrl->hclk);
1252                 goto err_init;
1253         }
1254
1255         clk_prepare_enable(ctrl->hclk);
1256
1257         ctrl->dev = dev;
1258         dev_set_drvdata(&pdev->dev, ctrl);
1259         mutex_init(&ctrl->port_lock);
1260         init_completion(&ctrl->broadcast);
1261         init_completion(&ctrl->enumeration);
1262
1263         ctrl->bus.ops = &qcom_swrm_ops;
1264         ctrl->bus.port_ops = &qcom_swrm_port_ops;
1265         ctrl->bus.compute_params = &qcom_swrm_compute_params;
1266
1267         ret = qcom_swrm_get_port_config(ctrl);
1268         if (ret)
1269                 goto err_clk;
1270
1271         params = &ctrl->bus.params;
1272         params->max_dr_freq = DEFAULT_CLK_FREQ;
1273         params->curr_dr_freq = DEFAULT_CLK_FREQ;
1274         params->col = data->default_cols;
1275         params->row = data->default_rows;
1276         ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1277         params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1278         params->next_bank = !params->curr_bank;
1279
1280         prop = &ctrl->bus.prop;
1281         prop->max_clk_freq = DEFAULT_CLK_FREQ;
1282         prop->num_clk_gears = 0;
1283         prop->num_clk_freq = MAX_FREQ_NUM;
1284         prop->clk_freq = &qcom_swrm_freq_tbl[0];
1285         prop->default_col = data->default_cols;
1286         prop->default_row = data->default_rows;
1287
1288         ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1289
1290         ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1291                                         qcom_swrm_irq_handler,
1292                                         IRQF_TRIGGER_RISING |
1293                                         IRQF_ONESHOT,
1294                                         "soundwire", ctrl);
1295         if (ret) {
1296                 dev_err(dev, "Failed to request soundwire irq\n");
1297                 goto err_clk;
1298         }
1299
1300         ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1301         if (ret) {
1302                 dev_err(dev, "Failed to register Soundwire controller (%d)\n",
1303                         ret);
1304                 goto err_clk;
1305         }
1306
1307         qcom_swrm_init(ctrl);
1308         wait_for_completion_timeout(&ctrl->enumeration,
1309                                     msecs_to_jiffies(TIMEOUT_MS));
1310         ret = qcom_swrm_register_dais(ctrl);
1311         if (ret)
1312                 goto err_master_add;
1313
1314         dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
1315                  (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1316                  ctrl->version & 0xffff);
1317
1318         return 0;
1319
1320 err_master_add:
1321         sdw_bus_master_delete(&ctrl->bus);
1322 err_clk:
1323         clk_disable_unprepare(ctrl->hclk);
1324 err_init:
1325         return ret;
1326 }
1327
1328 static int qcom_swrm_remove(struct platform_device *pdev)
1329 {
1330         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1331
1332         sdw_bus_master_delete(&ctrl->bus);
1333         clk_disable_unprepare(ctrl->hclk);
1334
1335         return 0;
1336 }
1337
1338 static const struct of_device_id qcom_swrm_of_match[] = {
1339         { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1340         { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1341         {/* sentinel */},
1342 };
1343
1344 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
1345
1346 static struct platform_driver qcom_swrm_driver = {
1347         .probe  = &qcom_swrm_probe,
1348         .remove = &qcom_swrm_remove,
1349         .driver = {
1350                 .name   = "qcom-soundwire",
1351                 .of_match_table = qcom_swrm_of_match,
1352         }
1353 };
1354 module_platform_driver(qcom_swrm_driver);
1355
1356 MODULE_DESCRIPTION("Qualcomm soundwire driver");
1357 MODULE_LICENSE("GPL v2");