drivers/soundwire/qcom.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2019, Linaro Limited
   3
   4 #include <linux/clk.h>
   5 #include <linux/completion.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/io.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/debugfs.h>
  11 #include <linux/of.h>
  12 #include <linux/of_irq.h>
  13 #include <linux/of_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regmap.h>
  16 #include <linux/reset.h>
  17 #include <linux/slab.h>
  18 #include <linux/pm_wakeirq.h>
  19 #include <linux/slimbus.h>
  20 #include <linux/soundwire/sdw.h>
  21 #include <linux/soundwire/sdw_registers.h>
  22 #include <sound/pcm_params.h>
  23 #include <sound/soc.h>
  24 #include "bus.h"
  25
  26 #define SWRM_COMP_SW_RESET                                      0x008
  27 #define SWRM_COMP_STATUS                                        0x014
  28 #define SWRM_FRM_GEN_ENABLED                                    BIT(0)
  29 #define SWRM_COMP_HW_VERSION                                    0x00
  30 #define SWRM_COMP_CFG_ADDR                                      0x04
  31 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK                    BIT(1)
  32 #define SWRM_COMP_CFG_ENABLE_MSK                                BIT(0)
  33 #define SWRM_COMP_PARAMS                                        0x100
  34 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH                          GENMASK(14, 10)
  35 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH                          GENMASK(19, 15)
  36 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK                        GENMASK(4, 0)
  37 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK                         GENMASK(9, 5)
  38 #define SWRM_COMP_MASTER_ID                                     0x104
  39 #define SWRM_INTERRUPT_STATUS                                   0x200
  40 #define SWRM_INTERRUPT_STATUS_RMSK                              GENMASK(16, 0)
  41 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ                    BIT(0)
  42 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED                BIT(1)
  43 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS          BIT(2)
  44 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET                  BIT(3)
  45 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  BIT(4)
  46 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 BIT(5)
  47 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW              BIT(6)
  48 #define SWRM_INTERRUPT_STATUS_CMD_ERROR                         BIT(7)
  49 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION               BIT(8)
  50 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH         BIT(9)
  51 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           BIT(10)
  52 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2             BIT(13)
  53 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2              BIT(14)
  54 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP               BIT(16)
  55 #define SWRM_INTERRUPT_MAX                                      17
  56 #define SWRM_INTERRUPT_MASK_ADDR                                0x204
  57 #define SWRM_INTERRUPT_CLEAR                                    0x208
  58 #define SWRM_INTERRUPT_CPU_EN                                   0x210
  59 #define SWRM_CMD_FIFO_WR_CMD                                    0x300
  60 #define SWRM_CMD_FIFO_RD_CMD                                    0x304
  61 #define SWRM_CMD_FIFO_CMD                                       0x308
  62 #define SWRM_CMD_FIFO_FLUSH                                     0x1
  63 #define SWRM_CMD_FIFO_STATUS                                    0x30C
  64 #define SWRM_RD_CMD_FIFO_CNT_MASK                               GENMASK(20, 16)
  65 #define SWRM_WR_CMD_FIFO_CNT_MASK                               GENMASK(12, 8)
  66 #define SWRM_CMD_FIFO_CFG_ADDR                                  0x314
  67 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE                        BIT(31)
  68 #define SWRM_RD_WR_CMD_RETRIES                                  0x7
  69 #define SWRM_CMD_FIFO_RD_FIFO_ADDR                              0x318
  70 #define SWRM_RD_FIFO_CMD_ID_MASK                                GENMASK(11, 8)
  71 #define SWRM_ENUMERATOR_CFG_ADDR                                0x500
  72 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m)               (0x530 + 0x8 * (m))
  73 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m)               (0x534 + 0x8 * (m))
  74 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m)                (0x101C + 0x40 * (m))
  75 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK                  GENMASK(2, 0)
  76 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK                  GENMASK(7, 3)
  77 #define SWRM_MCP_BUS_CTRL                                       0x1044
  78 #define SWRM_MCP_BUS_CLK_START                                  BIT(1)
  79 #define SWRM_MCP_CFG_ADDR                                       0x1048
  80 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK               GENMASK(21, 17)
  81 #define SWRM_DEF_CMD_NO_PINGS                                   0x1f
  82 #define SWRM_MCP_STATUS                                         0x104C
  83 #define SWRM_MCP_STATUS_BANK_NUM_MASK                           BIT(0)
  84 #define SWRM_MCP_SLV_STATUS                                     0x1090
  85 #define SWRM_MCP_SLV_STATUS_MASK                                GENMASK(1, 0)
  86 #define SWRM_MCP_SLV_STATUS_SZ                                  2
  87 #define SWRM_DP_PORT_CTRL_BANK(n, m)    (0x1124 + 0x100 * (n - 1) + 0x40 * m)
  88 #define SWRM_DP_PORT_CTRL_2_BANK(n, m)  (0x1128 + 0x100 * (n - 1) + 0x40 * m)
  89 #define SWRM_DP_BLOCK_CTRL_1(n)         (0x112C + 0x100 * (n - 1))
  90 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m)  (0x1130 + 0x100 * (n - 1) + 0x40 * m)
  91 #define SWRM_DP_PORT_HCTRL_BANK(n, m)   (0x1134 + 0x100 * (n - 1) + 0x40 * m)
  92 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m)  (0x1138 + 0x100 * (n - 1) + 0x40 * m)
  93 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n)   (0x1054 + 0x100 * (n - 1))
  94 #define SWR_MSTR_MAX_REG_ADDR           (0x1740)
  95
  96 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT                          0x18
  97 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT                          0x10
  98 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT                          0x08
  99 #define SWRM_AHB_BRIDGE_WR_DATA_0                               0xc85
 100 #define SWRM_AHB_BRIDGE_WR_ADDR_0                               0xc89
 101 #define SWRM_AHB_BRIDGE_RD_ADDR_0                               0xc8d
 102 #define SWRM_AHB_BRIDGE_RD_DATA_0                               0xc91
 103
 104 #define SWRM_REG_VAL_PACK(data, dev, id, reg)   \
 105                         ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
 106
 107 #define SWRM_SPECIAL_CMD_ID     0xF
 108 #define MAX_FREQ_NUM            1
 109 #define TIMEOUT_MS              100
 110 #define QCOM_SWRM_MAX_RD_LEN    0x1
 111 #define QCOM_SDW_MAX_PORTS      14
 112 #define DEFAULT_CLK_FREQ        9600000
 113 #define SWRM_MAX_DAIS           0xF
 114 #define SWR_INVALID_PARAM 0xFF
 115 #define SWR_HSTOP_MAX_VAL 0xF
 116 #define SWR_HSTART_MIN_VAL 0x0
 117 #define SWR_BROADCAST_CMD_ID    0x0F
 118 #define SWR_MAX_CMD_ID  14
 119 #define MAX_FIFO_RD_RETRY 3
 120 #define SWR_OVERFLOW_RETRY_COUNT 30
 121 #define SWRM_LINK_STATUS_RETRY_CNT 100
 122
 123 enum {
 124         MASTER_ID_WSA = 1,
 125         MASTER_ID_RX,
 126         MASTER_ID_TX
 127 };
 128
 129 struct qcom_swrm_port_config {
 130         u8 si;
 131         u8 off1;
 132         u8 off2;
 133         u8 bp_mode;
 134         u8 hstart;
 135         u8 hstop;
 136         u8 word_length;
 137         u8 blk_group_count;
 138         u8 lane_control;
 139 };
 140
 141 struct qcom_swrm_ctrl {
 142         struct sdw_bus bus;
 143         struct device *dev;
 144         struct regmap *regmap;
 145         void __iomem *mmio;
 146         struct reset_control *audio_cgcr;
 147 #ifdef CONFIG_DEBUG_FS
 148         struct dentry *debugfs;
 149 #endif
 150         struct completion broadcast;
 151         struct completion enumeration;
 152         struct work_struct slave_work;
 153         /* Port alloc/free lock */
 154         struct mutex port_lock;
 155         struct clk *hclk;
 156         u8 wr_cmd_id;
 157         u8 rd_cmd_id;
 158         int irq;
 159         unsigned int version;
 160         int wake_irq;
 161         int num_din_ports;
 162         int num_dout_ports;
 163         int cols_index;
 164         int rows_index;
 165         unsigned long dout_port_mask;
 166         unsigned long din_port_mask;
 167         u32 intr_mask;
 168         u8 rcmd_id;
 169         u8 wcmd_id;
 170         struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS];
 171         struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
 172         enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
 173         int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
 174         int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
 175         u32 slave_status;
 176         u32 wr_fifo_depth;
 177         u32 rd_fifo_depth;
 178         bool clock_stop_not_supported;
 179 };
 180
 181 struct qcom_swrm_data {
 182         u32 default_cols;
 183         u32 default_rows;
 184         bool sw_clk_gate_required;
 185 };
 186
 187 static const struct qcom_swrm_data swrm_v1_3_data = {
 188         .default_rows = 48,
 189         .default_cols = 16,
 190 };
 191
 192 static const struct qcom_swrm_data swrm_v1_5_data = {
 193         .default_rows = 50,
 194         .default_cols = 16,
 195 };
 196
 197 static const struct qcom_swrm_data swrm_v1_6_data = {
 198         .default_rows = 50,
 199         .default_cols = 16,
 200         .sw_clk_gate_required = true,
 201 };
 202
 203 #define to_qcom_sdw(b)  container_of(b, struct qcom_swrm_ctrl, bus)
 204
 205 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 206                                   u32 *val)
 207 {
 208         struct regmap *wcd_regmap = ctrl->regmap;
 209         int ret;
 210
 211         /* pg register + offset */
 212         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
 213                           (u8 *)&reg, 4);
 214         if (ret < 0)
 215                 return SDW_CMD_FAIL;
 216
 217         ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
 218                                val, 4);
 219         if (ret < 0)
 220                 return SDW_CMD_FAIL;
 221
 222         return SDW_CMD_OK;
 223 }
 224
 225 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
 226                                    int reg, int val)
 227 {
 228         struct regmap *wcd_regmap = ctrl->regmap;
 229         int ret;
 230         /* pg register + offset */
 231         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
 232                           (u8 *)&val, 4);
 233         if (ret)
 234                 return SDW_CMD_FAIL;
 235
 236         /* write address register */
 237         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
 238                           (u8 *)&reg, 4);
 239         if (ret)
 240                 return SDW_CMD_FAIL;
 241
 242         return SDW_CMD_OK;
 243 }
 244
 245 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 246                                   u32 *val)
 247 {
 248         *val = readl(ctrl->mmio + reg);
 249         return SDW_CMD_OK;
 250 }
 251
 252 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
 253                                    int val)
 254 {
 255         writel(val, ctrl->mmio + reg);
 256         return SDW_CMD_OK;
 257 }
 258
 259 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
 260                                    u8 dev_addr, u16 reg_addr)
 261 {
 262         u32 val;
 263         u8 id = *cmd_id;
 264
 265         if (id != SWR_BROADCAST_CMD_ID) {
 266                 if (id < SWR_MAX_CMD_ID)
 267                         id += 1;
 268                 else
 269                         id = 0;
 270                 *cmd_id = id;
 271         }
 272         val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
 273
 274         return val;
 275 }
 276
 277 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm)
 278 {
 279         u32 fifo_outstanding_data, value;
 280         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 281
 282         do {
 283                 /* Check for fifo underflow during read */
 284                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 285                 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
 286
 287                 /* Check if read data is available in read fifo */
 288                 if (fifo_outstanding_data > 0)
 289                         return 0;
 290
 291                 usleep_range(500, 510);
 292         } while (fifo_retry_count--);
 293
 294         if (fifo_outstanding_data == 0) {
 295                 dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__);
 296                 return -EIO;
 297         }
 298
 299         return 0;
 300 }
 301
 302 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm)
 303 {
 304         u32 fifo_outstanding_cmds, value;
 305         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 306
 307         do {
 308                 /* Check for fifo overflow during write */
 309                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 310                 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
 311
 312                 /* Check for space in write fifo before writing */
 313                 if (fifo_outstanding_cmds < swrm->wr_fifo_depth)
 314                         return 0;
 315
 316                 usleep_range(500, 510);
 317         } while (fifo_retry_count--);
 318
 319         if (fifo_outstanding_cmds == swrm->wr_fifo_depth) {
 320                 dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__);
 321                 return -EIO;
 322         }
 323
 324         return 0;
 325 }
 326
 327 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data,
 328                                      u8 dev_addr, u16 reg_addr)
 329 {
 330
 331         u32 val;
 332         int ret = 0;
 333         u8 cmd_id = 0x0;
 334
 335         if (dev_addr == SDW_BROADCAST_DEV_NUM) {
 336                 cmd_id = SWR_BROADCAST_CMD_ID;
 337                 val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
 338                                               dev_addr, reg_addr);
 339         } else {
 340                 val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
 341                                               dev_addr, reg_addr);
 342         }
 343
 344         if (swrm_wait_for_wr_fifo_avail(swrm))
 345                 return SDW_CMD_FAIL_OTHER;
 346
 347         if (cmd_id == SWR_BROADCAST_CMD_ID)
 348                 reinit_completion(&swrm->broadcast);
 349
 350         /* Its assumed that write is okay as we do not get any status back */
 351         swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
 352
 353         /* version 1.3 or less */
 354         if (swrm->version <= 0x01030000)
 355                 usleep_range(150, 155);
 356
 357         if (cmd_id == SWR_BROADCAST_CMD_ID) {
 358                 /*
 359                  * sleep for 10ms for MSM soundwire variant to allow broadcast
 360                  * command to complete.
 361                  */
 362                 ret = wait_for_completion_timeout(&swrm->broadcast,
 363                                                   msecs_to_jiffies(TIMEOUT_MS));
 364                 if (!ret)
 365                         ret = SDW_CMD_IGNORED;
 366                 else
 367                         ret = SDW_CMD_OK;
 368
 369         } else {
 370                 ret = SDW_CMD_OK;
 371         }
 372         return ret;
 373 }
 374
 375 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm,
 376                                      u8 dev_addr, u16 reg_addr,
 377                                      u32 len, u8 *rval)
 378 {
 379         u32 cmd_data, cmd_id, val, retry_attempt = 0;
 380
 381         val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
 382
 383         /*
 384          * Check for outstanding cmd wrt. write fifo depth to avoid
 385          * overflow as read will also increase write fifo cnt.
 386          */
 387         swrm_wait_for_wr_fifo_avail(swrm);
 388
 389         /* wait for FIFO RD to complete to avoid overflow */
 390         usleep_range(100, 105);
 391         swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
 392         /* wait for FIFO RD CMD complete to avoid overflow */
 393         usleep_range(250, 255);
 394
 395         if (swrm_wait_for_rd_fifo_avail(swrm))
 396                 return SDW_CMD_FAIL_OTHER;
 397
 398         do {
 399                 swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
 400                 rval[0] = cmd_data & 0xFF;
 401                 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
 402
 403                 if (cmd_id != swrm->rcmd_id) {
 404                         if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
 405                                 /* wait 500 us before retry on fifo read failure */
 406                                 usleep_range(500, 505);
 407                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD,
 408                                                 SWRM_CMD_FIFO_FLUSH);
 409                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
 410                         }
 411                         retry_attempt++;
 412                 } else {
 413                         return SDW_CMD_OK;
 414                 }
 415
 416         } while (retry_attempt < MAX_FIFO_RD_RETRY);
 417
 418         dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
 419                 dev_num: 0x%x, cmd_data: 0x%x\n",
 420                 reg_addr, swrm->rcmd_id, dev_addr, cmd_data);
 421
 422         return SDW_CMD_IGNORED;
 423 }
 424
 425 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
 426 {
 427         u32 val, status;
 428         int dev_num;
 429
 430         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 431
 432         for (dev_num = 1; dev_num <= SDW_MAX_DEVICES; dev_num++) {
 433                 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
 434
 435                 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
 436                         ctrl->status[dev_num] = status;
 437                         return dev_num;
 438                 }
 439         }
 440
 441         return -EINVAL;
 442 }
 443
 444 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
 445 {
 446         u32 val;
 447         int i;
 448
 449         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 450         ctrl->slave_status = val;
 451
 452         for (i = 1; i <= SDW_MAX_DEVICES; i++) {
 453                 u32 s;
 454
 455                 s = (val >> (i * 2));
 456                 s &= SWRM_MCP_SLV_STATUS_MASK;
 457                 ctrl->status[i] = s;
 458         }
 459 }
 460
 461 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
 462                                         struct sdw_slave *slave, int devnum)
 463 {
 464         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 465         u32 status;
 466
 467         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
 468         status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
 469         status &= SWRM_MCP_SLV_STATUS_MASK;
 470
 471         if (status == SDW_SLAVE_ATTACHED) {
 472                 if (slave)
 473                         slave->dev_num = devnum;
 474                 mutex_lock(&bus->bus_lock);
 475                 set_bit(devnum, bus->assigned);
 476                 mutex_unlock(&bus->bus_lock);
 477         }
 478 }
 479
 480 static int qcom_swrm_enumerate(struct sdw_bus *bus)
 481 {
 482         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 483         struct sdw_slave *slave, *_s;
 484         struct sdw_slave_id id;
 485         u32 val1, val2;
 486         bool found;
 487         u64 addr;
 488         int i;
 489         char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
 490
 491         for (i = 1; i <= SDW_MAX_DEVICES; i++) {
 492                 /* do not continue if the status is Not Present  */
 493                 if (!ctrl->status[i])
 494                         continue;
 495
 496                 /*SCP_Devid5 - Devid 4*/
 497                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
 498
 499                 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
 500                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
 501
 502                 if (!val1 && !val2)
 503                         break;
 504
 505                 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
 506                         ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
 507                         ((u64)buf1[0] << 40);
 508
 509                 sdw_extract_slave_id(bus, addr, &id);
 510                 found = false;
 511                 /* Now compare with entries */
 512                 list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
 513                         if (sdw_compare_devid(slave, id) == 0) {
 514                                 qcom_swrm_set_slave_dev_num(bus, slave, i);
 515                                 found = true;
 516                                 break;
 517                         }
 518                 }
 519
 520                 if (!found) {
 521                         qcom_swrm_set_slave_dev_num(bus, NULL, i);
 522                         sdw_slave_add(bus, &id, NULL);
 523                 }
 524         }
 525
 526         complete(&ctrl->enumeration);
 527         return 0;
 528 }
 529
 530 static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id)
 531 {
 532         struct qcom_swrm_ctrl *swrm = dev_id;
 533         int ret;
 534
 535         ret = pm_runtime_resume_and_get(swrm->dev);
 536         if (ret < 0 && ret != -EACCES) {
 537                 dev_err_ratelimited(swrm->dev,
 538                                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
 539                                     __func__, ret);
 540                 return ret;
 541         }
 542
 543         if (swrm->wake_irq > 0) {
 544                 if (!irqd_irq_disabled(irq_get_irq_data(swrm->wake_irq)))
 545                         disable_irq_nosync(swrm->wake_irq);
 546         }
 547
 548         pm_runtime_mark_last_busy(swrm->dev);
 549         pm_runtime_put_autosuspend(swrm->dev);
 550
 551         return IRQ_HANDLED;
 552 }
 553
 554 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
 555 {
 556         struct qcom_swrm_ctrl *swrm = dev_id;
 557         u32 value, intr_sts, intr_sts_masked, slave_status;
 558         u32 i;
 559         int devnum;
 560         int ret = IRQ_HANDLED;
 561         clk_prepare_enable(swrm->hclk);
 562
 563         swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
 564         intr_sts_masked = intr_sts & swrm->intr_mask;
 565
 566         do {
 567                 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
 568                         value = intr_sts_masked & BIT(i);
 569                         if (!value)
 570                                 continue;
 571
 572                         switch (value) {
 573                         case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
 574                                 devnum = qcom_swrm_get_alert_slave_dev_num(swrm);
 575                                 if (devnum < 0) {
 576                                         dev_err_ratelimited(swrm->dev,
 577                                             "no slave alert found.spurious interrupt\n");
 578                                 } else {
 579                                         sdw_handle_slave_status(&swrm->bus, swrm->status);
 580                                 }
 581
 582                                 break;
 583                         case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
 584                         case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
 585                                 dev_dbg_ratelimited(swrm->dev, "SWR new slave attached\n");
 586                                 swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status);
 587                                 if (swrm->slave_status == slave_status) {
 588                                         dev_dbg(swrm->dev, "Slave status not changed %x\n",
 589                                                 slave_status);
 590                                 } else {
 591                                         qcom_swrm_get_device_status(swrm);
 592                                         qcom_swrm_enumerate(&swrm->bus);
 593                                         sdw_handle_slave_status(&swrm->bus, swrm->status);
 594                                 }
 595                                 break;
 596                         case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
 597                                 dev_err_ratelimited(swrm->dev,
 598                                                 "%s: SWR bus clsh detected\n",
 599                                                 __func__);
 600                                 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
 601                                 swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 602                                 break;
 603                         case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
 604                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 605                                 dev_err_ratelimited(swrm->dev,
 606                                         "%s: SWR read FIFO overflow fifo status 0x%x\n",
 607                                         __func__, value);
 608                                 break;
 609                         case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
 610                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 611                                 dev_err_ratelimited(swrm->dev,
 612                                         "%s: SWR read FIFO underflow fifo status 0x%x\n",
 613                                         __func__, value);
 614                                 break;
 615                         case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
 616                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 617                                 dev_err(swrm->dev,
 618                                         "%s: SWR write FIFO overflow fifo status %x\n",
 619                                         __func__, value);
 620                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
 621                                 break;
 622                         case SWRM_INTERRUPT_STATUS_CMD_ERROR:
 623                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 624                                 dev_err_ratelimited(swrm->dev,
 625                                         "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
 626                                         __func__, value);
 627                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
 628                                 break;
 629                         case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
 630                                 dev_err_ratelimited(swrm->dev,
 631                                                 "%s: SWR Port collision detected\n",
 632                                                 __func__);
 633                                 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
 634                                 swrm->reg_write(swrm,
 635                                         SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 636                                 break;
 637                         case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
 638                                 dev_err_ratelimited(swrm->dev,
 639                                         "%s: SWR read enable valid mismatch\n",
 640                                         __func__);
 641                                 swrm->intr_mask &=
 642                                         ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
 643                                 swrm->reg_write(swrm,
 644                                         SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 645                                 break;
 646                         case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
 647                                 complete(&swrm->broadcast);
 648                                 break;
 649                         case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
 650                                 break;
 651                         case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
 652                                 break;
 653                         case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
 654                                 break;
 655                         default:
 656                                 dev_err_ratelimited(swrm->dev,
 657                                                 "%s: SWR unknown interrupt value: %d\n",
 658                                                 __func__, value);
 659                                 ret = IRQ_NONE;
 660                                 break;
 661                         }
 662                 }
 663                 swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts);
 664                 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
 665                 intr_sts_masked = intr_sts & swrm->intr_mask;
 666         } while (intr_sts_masked);
 667
 668         clk_disable_unprepare(swrm->hclk);
 669         return ret;
 670 }
 671
 672 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
 673 {
 674         u32 val;
 675
 676         /* Clear Rows and Cols */
 677         val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
 678         val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
 679
 680         reset_control_reset(ctrl->audio_cgcr);
 681
 682         ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
 683
 684         /* Enable Auto enumeration */
 685         ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
 686
 687         ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
 688         /* Mask soundwire interrupts */
 689         ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
 690                         SWRM_INTERRUPT_STATUS_RMSK);
 691
 692         /* Configure No pings */
 693         ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
 694         u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
 695         ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
 696
 697         ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
 698         /* Configure number of retries of a read/write cmd */
 699         if (ctrl->version > 0x01050001) {
 700                 /* Only for versions >= 1.5.1 */
 701                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 702                                 SWRM_RD_WR_CMD_RETRIES |
 703                                 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
 704         } else {
 705                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 706                                 SWRM_RD_WR_CMD_RETRIES);
 707         }
 708
 709         /* Set IRQ to PULSE */
 710         ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
 711                         SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
 712                         SWRM_COMP_CFG_ENABLE_MSK);
 713
 714         /* enable CPU IRQs */
 715         if (ctrl->mmio) {
 716                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
 717                                 SWRM_INTERRUPT_STATUS_RMSK);
 718         }
 719         ctrl->slave_status = 0;
 720         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
 721         ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
 722         ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
 723
 724         return 0;
 725 }
 726
 727 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
 728                                                     struct sdw_msg *msg)
 729 {
 730         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 731         int ret, i, len;
 732
 733         if (msg->flags == SDW_MSG_FLAG_READ) {
 734                 for (i = 0; i < msg->len;) {
 735                         if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
 736                                 len = msg->len - i;
 737                         else
 738                                 len = QCOM_SWRM_MAX_RD_LEN;
 739
 740                         ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
 741                                                         msg->addr + i, len,
 742                                                        &msg->buf[i]);
 743                         if (ret)
 744                                 return ret;
 745
 746                         i = i + len;
 747                 }
 748         } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
 749                 for (i = 0; i < msg->len; i++) {
 750                         ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
 751                                                         msg->dev_num,
 752                                                        msg->addr + i);
 753                         if (ret)
 754                                 return SDW_CMD_IGNORED;
 755                 }
 756         }
 757
 758         return SDW_CMD_OK;
 759 }
 760
 761 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
 762 {
 763         u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
 764         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 765         u32 val;
 766
 767         ctrl->reg_read(ctrl, reg, &val);
 768
 769         u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
 770         u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
 771
 772         return ctrl->reg_write(ctrl, reg, val);
 773 }
 774
 775 static int qcom_swrm_port_params(struct sdw_bus *bus,
 776                                  struct sdw_port_params *p_params,
 777                                  unsigned int bank)
 778 {
 779         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 780
 781         return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
 782                                p_params->bps - 1);
 783
 784 }
 785
 786 static int qcom_swrm_transport_params(struct sdw_bus *bus,
 787                                       struct sdw_transport_params *params,
 788                                       enum sdw_reg_bank bank)
 789 {
 790         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 791         struct qcom_swrm_port_config *pcfg;
 792         u32 value;
 793         int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
 794         int ret;
 795
 796         pcfg = &ctrl->pconfig[params->port_num];
 797
 798         value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
 799         value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
 800         value |= pcfg->si;
 801
 802         ret = ctrl->reg_write(ctrl, reg, value);
 803         if (ret)
 804                 goto err;
 805
 806         if (pcfg->lane_control != SWR_INVALID_PARAM) {
 807                 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
 808                 value = pcfg->lane_control;
 809                 ret = ctrl->reg_write(ctrl, reg, value);
 810                 if (ret)
 811                         goto err;
 812         }
 813
 814         if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
 815                 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
 816                 value = pcfg->blk_group_count;
 817                 ret = ctrl->reg_write(ctrl, reg, value);
 818                 if (ret)
 819                         goto err;
 820         }
 821
 822         if (pcfg->hstart != SWR_INVALID_PARAM
 823                         && pcfg->hstop != SWR_INVALID_PARAM) {
 824                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
 825                 value = (pcfg->hstop << 4) | pcfg->hstart;
 826                 ret = ctrl->reg_write(ctrl, reg, value);
 827         } else {
 828                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
 829                 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
 830                 ret = ctrl->reg_write(ctrl, reg, value);
 831         }
 832
 833         if (ret)
 834                 goto err;
 835
 836         if (pcfg->bp_mode != SWR_INVALID_PARAM) {
 837                 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
 838                 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
 839         }
 840
 841 err:
 842         return ret;
 843 }
 844
 845 static int qcom_swrm_port_enable(struct sdw_bus *bus,
 846                                  struct sdw_enable_ch *enable_ch,
 847                                  unsigned int bank)
 848 {
 849         u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
 850         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 851         u32 val;
 852
 853         ctrl->reg_read(ctrl, reg, &val);
 854
 855         if (enable_ch->enable)
 856                 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 857         else
 858                 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 859
 860         return ctrl->reg_write(ctrl, reg, val);
 861 }
 862
 863 static const struct sdw_master_port_ops qcom_swrm_port_ops = {
 864         .dpn_set_port_params = qcom_swrm_port_params,
 865         .dpn_set_port_transport_params = qcom_swrm_transport_params,
 866         .dpn_port_enable_ch = qcom_swrm_port_enable,
 867 };
 868
 869 static const struct sdw_master_ops qcom_swrm_ops = {
 870         .xfer_msg = qcom_swrm_xfer_msg,
 871         .pre_bank_switch = qcom_swrm_pre_bank_switch,
 872 };
 873
 874 static int qcom_swrm_compute_params(struct sdw_bus *bus)
 875 {
 876         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 877         struct sdw_master_runtime *m_rt;
 878         struct sdw_slave_runtime *s_rt;
 879         struct sdw_port_runtime *p_rt;
 880         struct qcom_swrm_port_config *pcfg;
 881         struct sdw_slave *slave;
 882         unsigned int m_port;
 883         int i = 1;
 884
 885         list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
 886                 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
 887                         pcfg = &ctrl->pconfig[p_rt->num];
 888                         p_rt->transport_params.port_num = p_rt->num;
 889                         if (pcfg->word_length != SWR_INVALID_PARAM) {
 890                                 sdw_fill_port_params(&p_rt->port_params,
 891                                              p_rt->num,  pcfg->word_length + 1,
 892                                              SDW_PORT_FLOW_MODE_ISOCH,
 893                                              SDW_PORT_DATA_MODE_NORMAL);
 894                         }
 895
 896                 }
 897
 898                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
 899                         slave = s_rt->slave;
 900                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
 901                                 m_port = slave->m_port_map[p_rt->num];
 902                                 /* port config starts at offset 0 so -1 from actual port number */
 903                                 if (m_port)
 904                                         pcfg = &ctrl->pconfig[m_port];
 905                                 else
 906                                         pcfg = &ctrl->pconfig[i];
 907                                 p_rt->transport_params.port_num = p_rt->num;
 908                                 p_rt->transport_params.sample_interval =
 909                                         pcfg->si + 1;
 910                                 p_rt->transport_params.offset1 = pcfg->off1;
 911                                 p_rt->transport_params.offset2 = pcfg->off2;
 912                                 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
 913                                 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
 914
 915                                 p_rt->transport_params.hstart = pcfg->hstart;
 916                                 p_rt->transport_params.hstop = pcfg->hstop;
 917                                 p_rt->transport_params.lane_ctrl = pcfg->lane_control;
 918                                 if (pcfg->word_length != SWR_INVALID_PARAM) {
 919                                         sdw_fill_port_params(&p_rt->port_params,
 920                                                      p_rt->num,
 921                                                      pcfg->word_length + 1,
 922                                                      SDW_PORT_FLOW_MODE_ISOCH,
 923                                                      SDW_PORT_DATA_MODE_NORMAL);
 924                                 }
 925                                 i++;
 926                         }
 927                 }
 928         }
 929
 930         return 0;
 931 }
 932
 933 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
 934         DEFAULT_CLK_FREQ,
 935 };
 936
 937 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
 938                                         struct sdw_stream_runtime *stream)
 939 {
 940         struct sdw_master_runtime *m_rt;
 941         struct sdw_port_runtime *p_rt;
 942         unsigned long *port_mask;
 943
 944         mutex_lock(&ctrl->port_lock);
 945
 946         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
 947                 if (m_rt->direction == SDW_DATA_DIR_RX)
 948                         port_mask = &ctrl->dout_port_mask;
 949                 else
 950                         port_mask = &ctrl->din_port_mask;
 951
 952                 list_for_each_entry(p_rt, &m_rt->port_list, port_node)
 953                         clear_bit(p_rt->num, port_mask);
 954         }
 955
 956         mutex_unlock(&ctrl->port_lock);
 957 }
 958
 959 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
 960                                         struct sdw_stream_runtime *stream,
 961                                        struct snd_pcm_hw_params *params,
 962                                        int direction)
 963 {
 964         struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
 965         struct sdw_stream_config sconfig;
 966         struct sdw_master_runtime *m_rt;
 967         struct sdw_slave_runtime *s_rt;
 968         struct sdw_port_runtime *p_rt;
 969         struct sdw_slave *slave;
 970         unsigned long *port_mask;
 971         int i, maxport, pn, nports = 0, ret = 0;
 972         unsigned int m_port;
 973
 974         mutex_lock(&ctrl->port_lock);
 975         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
 976                 if (m_rt->direction == SDW_DATA_DIR_RX) {
 977                         maxport = ctrl->num_dout_ports;
 978                         port_mask = &ctrl->dout_port_mask;
 979                 } else {
 980                         maxport = ctrl->num_din_ports;
 981                         port_mask = &ctrl->din_port_mask;
 982                 }
 983
 984                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
 985                         slave = s_rt->slave;
 986                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
 987                                 m_port = slave->m_port_map[p_rt->num];
 988                                 /* Port numbers start from 1 - 14*/
 989                                 if (m_port)
 990                                         pn = m_port;
 991                                 else
 992                                         pn = find_first_zero_bit(port_mask, maxport);
 993
 994                                 if (pn > maxport) {
 995                                         dev_err(ctrl->dev, "All ports busy\n");
 996                                         ret = -EBUSY;
 997                                         goto err;
 998                                 }
 999                                 set_bit(pn, port_mask);
1000                                 pconfig[nports].num = pn;
1001                                 pconfig[nports].ch_mask = p_rt->ch_mask;
1002                                 nports++;
1003                         }
1004                 }
1005         }
1006
1007         if (direction == SNDRV_PCM_STREAM_CAPTURE)
1008                 sconfig.direction = SDW_DATA_DIR_TX;
1009         else
1010                 sconfig.direction = SDW_DATA_DIR_RX;
1011
1012         /* hw parameters wil be ignored as we only support PDM */
1013         sconfig.ch_count = 1;
1014         sconfig.frame_rate = params_rate(params);
1015         sconfig.type = stream->type;
1016         sconfig.bps = 1;
1017         sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
1018                               nports, stream);
1019 err:
1020         if (ret) {
1021                 for (i = 0; i < nports; i++)
1022                         clear_bit(pconfig[i].num, port_mask);
1023         }
1024
1025         mutex_unlock(&ctrl->port_lock);
1026
1027         return ret;
1028 }
1029
1030 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
1031                                struct snd_pcm_hw_params *params,
1032                               struct snd_soc_dai *dai)
1033 {
1034         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1035         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1036         int ret;
1037
1038         ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
1039                                            substream->stream);
1040         if (ret)
1041                 qcom_swrm_stream_free_ports(ctrl, sruntime);
1042
1043         return ret;
1044 }
1045
1046 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
1047                              struct snd_soc_dai *dai)
1048 {
1049         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1050         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1051
1052         qcom_swrm_stream_free_ports(ctrl, sruntime);
1053         sdw_stream_remove_master(&ctrl->bus, sruntime);
1054
1055         return 0;
1056 }
1057
1058 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
1059                                     void *stream, int direction)
1060 {
1061         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1062
1063         ctrl->sruntime[dai->id] = stream;
1064
1065         return 0;
1066 }
1067
1068 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
1069 {
1070         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1071
1072         return ctrl->sruntime[dai->id];
1073 }
1074
1075 static int qcom_swrm_startup(struct snd_pcm_substream *substream,
1076                              struct snd_soc_dai *dai)
1077 {
1078         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1079         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1080         struct sdw_stream_runtime *sruntime;
1081         struct snd_soc_dai *codec_dai;
1082         int ret, i;
1083
1084         ret = pm_runtime_resume_and_get(ctrl->dev);
1085         if (ret < 0 && ret != -EACCES) {
1086                 dev_err_ratelimited(ctrl->dev,
1087                                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
1088                                     __func__, ret);
1089                 return ret;
1090         }
1091
1092         sruntime = sdw_alloc_stream(dai->name);
1093         if (!sruntime)
1094                 return -ENOMEM;
1095
1096         ctrl->sruntime[dai->id] = sruntime;
1097
1098         for_each_rtd_codec_dais(rtd, i, codec_dai) {
1099                 ret = snd_soc_dai_set_stream(codec_dai, sruntime,
1100                                              substream->stream);
1101                 if (ret < 0 && ret != -ENOTSUPP) {
1102                         dev_err(dai->dev, "Failed to set sdw stream on %s\n",
1103                                 codec_dai->name);
1104                         sdw_release_stream(sruntime);
1105                         return ret;
1106                 }
1107         }
1108
1109         return 0;
1110 }
1111
1112 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
1113                                struct snd_soc_dai *dai)
1114 {
1115         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1116
1117         sdw_release_stream(ctrl->sruntime[dai->id]);
1118         ctrl->sruntime[dai->id] = NULL;
1119         pm_runtime_mark_last_busy(ctrl->dev);
1120         pm_runtime_put_autosuspend(ctrl->dev);
1121
1122 }
1123
1124 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
1125         .hw_params = qcom_swrm_hw_params,
1126         .hw_free = qcom_swrm_hw_free,
1127         .startup = qcom_swrm_startup,
1128         .shutdown = qcom_swrm_shutdown,
1129         .set_stream = qcom_swrm_set_sdw_stream,
1130         .get_stream = qcom_swrm_get_sdw_stream,
1131 };
1132
1133 static const struct snd_soc_component_driver qcom_swrm_dai_component = {
1134         .name = "soundwire",
1135 };
1136
1137 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1138 {
1139         int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1140         struct snd_soc_dai_driver *dais;
1141         struct snd_soc_pcm_stream *stream;
1142         struct device *dev = ctrl->dev;
1143         int i;
1144
1145         /* PDM dais are only tested for now */
1146         dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
1147         if (!dais)
1148                 return -ENOMEM;
1149
1150         for (i = 0; i < num_dais; i++) {
1151                 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
1152                 if (!dais[i].name)
1153                         return -ENOMEM;
1154
1155                 if (i < ctrl->num_dout_ports)
1156                         stream = &dais[i].playback;
1157                 else
1158                         stream = &dais[i].capture;
1159
1160                 stream->channels_min = 1;
1161                 stream->channels_max = 1;
1162                 stream->rates = SNDRV_PCM_RATE_48000;
1163                 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
1164
1165                 dais[i].ops = &qcom_swrm_pdm_dai_ops;
1166                 dais[i].id = i;
1167         }
1168
1169         return devm_snd_soc_register_component(ctrl->dev,
1170                                                 &qcom_swrm_dai_component,
1171                                                 dais, num_dais);
1172 }
1173
1174 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1175 {
1176         struct device_node *np = ctrl->dev->of_node;
1177         u8 off1[QCOM_SDW_MAX_PORTS];
1178         u8 off2[QCOM_SDW_MAX_PORTS];
1179         u8 si[QCOM_SDW_MAX_PORTS];
1180         u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
1181         u8 hstart[QCOM_SDW_MAX_PORTS];
1182         u8 hstop[QCOM_SDW_MAX_PORTS];
1183         u8 word_length[QCOM_SDW_MAX_PORTS];
1184         u8 blk_group_count[QCOM_SDW_MAX_PORTS];
1185         u8 lane_control[QCOM_SDW_MAX_PORTS];
1186         int i, ret, nports, val;
1187
1188         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1189
1190         ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1191         ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1192
1193         ret = of_property_read_u32(np, "qcom,din-ports", &val);
1194         if (ret)
1195                 return ret;
1196
1197         if (val > ctrl->num_din_ports)
1198                 return -EINVAL;
1199
1200         ctrl->num_din_ports = val;
1201
1202         ret = of_property_read_u32(np, "qcom,dout-ports", &val);
1203         if (ret)
1204                 return ret;
1205
1206         if (val > ctrl->num_dout_ports)
1207                 return -EINVAL;
1208
1209         ctrl->num_dout_ports = val;
1210
1211         nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1212         /* Valid port numbers are from 1-14, so mask out port 0 explicitly */
1213         set_bit(0, &ctrl->dout_port_mask);
1214         set_bit(0, &ctrl->din_port_mask);
1215
1216         ret = of_property_read_u8_array(np, "qcom,ports-offset1",
1217                                         off1, nports);
1218         if (ret)
1219                 return ret;
1220
1221         ret = of_property_read_u8_array(np, "qcom,ports-offset2",
1222                                         off2, nports);
1223         if (ret)
1224                 return ret;
1225
1226         ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
1227                                         si, nports);
1228         if (ret)
1229                 return ret;
1230
1231         ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
1232                                         bp_mode, nports);
1233         if (ret) {
1234                 if (ctrl->version <= 0x01030000)
1235                         memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1236                 else
1237                         return ret;
1238         }
1239
1240         memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1241         of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports);
1242
1243         memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1244         of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports);
1245
1246         memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1247         of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports);
1248
1249         memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1250         of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports);
1251
1252         memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1253         of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports);
1254
1255         for (i = 0; i < nports; i++) {
1256                 /* Valid port number range is from 1-14 */
1257                 ctrl->pconfig[i + 1].si = si[i];
1258                 ctrl->pconfig[i + 1].off1 = off1[i];
1259                 ctrl->pconfig[i + 1].off2 = off2[i];
1260                 ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
1261                 ctrl->pconfig[i + 1].hstart = hstart[i];
1262                 ctrl->pconfig[i + 1].hstop = hstop[i];
1263                 ctrl->pconfig[i + 1].word_length = word_length[i];
1264                 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
1265                 ctrl->pconfig[i + 1].lane_control = lane_control[i];
1266         }
1267
1268         return 0;
1269 }
1270
1271 #ifdef CONFIG_DEBUG_FS
1272 static int swrm_reg_show(struct seq_file *s_file, void *data)
1273 {
1274         struct qcom_swrm_ctrl *swrm = s_file->private;
1275         int reg, reg_val, ret;
1276
1277         ret = pm_runtime_resume_and_get(swrm->dev);
1278         if (ret < 0 && ret != -EACCES) {
1279                 dev_err_ratelimited(swrm->dev,
1280                                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
1281                                     __func__, ret);
1282                 return ret;
1283         }
1284
1285         for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) {
1286                 swrm->reg_read(swrm, reg, &reg_val);
1287                 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
1288         }
1289         pm_runtime_mark_last_busy(swrm->dev);
1290         pm_runtime_put_autosuspend(swrm->dev);
1291
1292
1293         return 0;
1294 }
1295 DEFINE_SHOW_ATTRIBUTE(swrm_reg);
1296 #endif
1297
1298 static int qcom_swrm_probe(struct platform_device *pdev)
1299 {
1300         struct device *dev = &pdev->dev;
1301         struct sdw_master_prop *prop;
1302         struct sdw_bus_params *params;
1303         struct qcom_swrm_ctrl *ctrl;
1304         const struct qcom_swrm_data *data;
1305         int ret;
1306         u32 val;
1307
1308         ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1309         if (!ctrl)
1310                 return -ENOMEM;
1311
1312         data = of_device_get_match_data(dev);
1313         ctrl->rows_index = sdw_find_row_index(data->default_rows);
1314         ctrl->cols_index = sdw_find_col_index(data->default_cols);
1315 #if IS_REACHABLE(CONFIG_SLIMBUS)
1316         if (dev->parent->bus == &slimbus_bus) {
1317 #else
1318         if (false) {
1319 #endif
1320                 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1321                 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1322                 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1323                 if (!ctrl->regmap)
1324                         return -EINVAL;
1325         } else {
1326                 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1327                 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1328                 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1329                 if (IS_ERR(ctrl->mmio))
1330                         return PTR_ERR(ctrl->mmio);
1331         }
1332
1333         if (data->sw_clk_gate_required) {
1334                 ctrl->audio_cgcr = devm_reset_control_get_exclusive(dev, "swr_audio_cgcr");
1335                 if (IS_ERR_OR_NULL(ctrl->audio_cgcr)) {
1336                         dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n");
1337                         ret = PTR_ERR(ctrl->audio_cgcr);
1338                         goto err_init;
1339                 }
1340         }
1341
1342         ctrl->irq = of_irq_get(dev->of_node, 0);
1343         if (ctrl->irq < 0) {
1344                 ret = ctrl->irq;
1345                 goto err_init;
1346         }
1347
1348         ctrl->hclk = devm_clk_get(dev, "iface");
1349         if (IS_ERR(ctrl->hclk)) {
1350                 ret = PTR_ERR(ctrl->hclk);
1351                 goto err_init;
1352         }
1353
1354         clk_prepare_enable(ctrl->hclk);
1355
1356         ctrl->dev = dev;
1357         dev_set_drvdata(&pdev->dev, ctrl);
1358         mutex_init(&ctrl->port_lock);
1359         init_completion(&ctrl->broadcast);
1360         init_completion(&ctrl->enumeration);
1361
1362         ctrl->bus.ops = &qcom_swrm_ops;
1363         ctrl->bus.port_ops = &qcom_swrm_port_ops;
1364         ctrl->bus.compute_params = &qcom_swrm_compute_params;
1365         ctrl->bus.clk_stop_timeout = 300;
1366
1367         ret = qcom_swrm_get_port_config(ctrl);
1368         if (ret)
1369                 goto err_clk;
1370
1371         params = &ctrl->bus.params;
1372         params->max_dr_freq = DEFAULT_CLK_FREQ;
1373         params->curr_dr_freq = DEFAULT_CLK_FREQ;
1374         params->col = data->default_cols;
1375         params->row = data->default_rows;
1376         ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1377         params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1378         params->next_bank = !params->curr_bank;
1379
1380         prop = &ctrl->bus.prop;
1381         prop->max_clk_freq = DEFAULT_CLK_FREQ;
1382         prop->num_clk_gears = 0;
1383         prop->num_clk_freq = MAX_FREQ_NUM;
1384         prop->clk_freq = &qcom_swrm_freq_tbl[0];
1385         prop->default_col = data->default_cols;
1386         prop->default_row = data->default_rows;
1387
1388         ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1389
1390         ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1391                                         qcom_swrm_irq_handler,
1392                                         IRQF_TRIGGER_RISING |
1393                                         IRQF_ONESHOT,
1394                                         "soundwire", ctrl);
1395         if (ret) {
1396                 dev_err(dev, "Failed to request soundwire irq\n");
1397                 goto err_clk;
1398         }
1399
1400         ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1401         if (ctrl->wake_irq > 0) {
1402                 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1403                                                 qcom_swrm_wake_irq_handler,
1404                                                 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1405                                                 "swr_wake_irq", ctrl);
1406                 if (ret) {
1407                         dev_err(dev, "Failed to request soundwire wake irq\n");
1408                         goto err_init;
1409                 }
1410         }
1411
1412         ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1413         if (ret) {
1414                 dev_err(dev, "Failed to register Soundwire controller (%d)\n",
1415                         ret);
1416                 goto err_clk;
1417         }
1418
1419         qcom_swrm_init(ctrl);
1420         wait_for_completion_timeout(&ctrl->enumeration,
1421                                     msecs_to_jiffies(TIMEOUT_MS));
1422         ret = qcom_swrm_register_dais(ctrl);
1423         if (ret)
1424                 goto err_master_add;
1425
1426         dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
1427                  (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1428                  ctrl->version & 0xffff);
1429
1430         pm_runtime_set_autosuspend_delay(dev, 3000);
1431         pm_runtime_use_autosuspend(dev);
1432         pm_runtime_mark_last_busy(dev);
1433         pm_runtime_set_active(dev);
1434         pm_runtime_enable(dev);
1435
1436         /* Clk stop is not supported on WSA Soundwire masters */
1437         if (ctrl->version <= 0x01030000) {
1438                 ctrl->clock_stop_not_supported = true;
1439         } else {
1440                 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1441                 if (val == MASTER_ID_WSA)
1442                         ctrl->clock_stop_not_supported = true;
1443         }
1444
1445 #ifdef CONFIG_DEBUG_FS
1446         ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1447         debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1448                             &swrm_reg_fops);
1449 #endif
1450
1451         return 0;
1452
1453 err_master_add:
1454         sdw_bus_master_delete(&ctrl->bus);
1455 err_clk:
1456         clk_disable_unprepare(ctrl->hclk);
1457 err_init:
1458         return ret;
1459 }
1460
1461 static int qcom_swrm_remove(struct platform_device *pdev)
1462 {
1463         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1464
1465         sdw_bus_master_delete(&ctrl->bus);
1466         clk_disable_unprepare(ctrl->hclk);
1467
1468         return 0;
1469 }
1470
1471 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm)
1472 {
1473         int retry = SWRM_LINK_STATUS_RETRY_CNT;
1474         int comp_sts;
1475
1476         do {
1477                 swrm->reg_read(swrm, SWRM_COMP_STATUS, &comp_sts);
1478
1479                 if (comp_sts & SWRM_FRM_GEN_ENABLED)
1480                         return true;
1481
1482                 usleep_range(500, 510);
1483         } while (retry--);
1484
1485         dev_err(swrm->dev, "%s: link status not %s\n", __func__,
1486                 comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
1487
1488         return false;
1489 }
1490
1491 static int __maybe_unused swrm_runtime_resume(struct device *dev)
1492 {
1493         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1494         int ret;
1495
1496         if (ctrl->wake_irq > 0) {
1497                 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1498                         disable_irq_nosync(ctrl->wake_irq);
1499         }
1500
1501         clk_prepare_enable(ctrl->hclk);
1502
1503         if (ctrl->clock_stop_not_supported) {
1504                 reinit_completion(&ctrl->enumeration);
1505                 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1506                 usleep_range(100, 105);
1507
1508                 qcom_swrm_init(ctrl);
1509
1510                 usleep_range(100, 105);
1511                 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1512                         dev_err(ctrl->dev, "link failed to connect\n");
1513
1514                 /* wait for hw enumeration to complete */
1515                 wait_for_completion_timeout(&ctrl->enumeration,
1516                                             msecs_to_jiffies(TIMEOUT_MS));
1517                 qcom_swrm_get_device_status(ctrl);
1518                 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1519         } else {
1520                 reset_control_reset(ctrl->audio_cgcr);
1521
1522                 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1523                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR,
1524                         SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
1525
1526                 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1527                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
1528                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
1529
1530                 usleep_range(100, 105);
1531                 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1532                         dev_err(ctrl->dev, "link failed to connect\n");
1533
1534                 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1535                 if (ret < 0)
1536                         dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1537         }
1538
1539         return 0;
1540 }
1541
1542 static int __maybe_unused swrm_runtime_suspend(struct device *dev)
1543 {
1544         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1545         int ret;
1546
1547         if (!ctrl->clock_stop_not_supported) {
1548                 /* Mask bus clash interrupt */
1549                 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1550                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
1551                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
1552                 /* Prepare slaves for clock stop */
1553                 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1554                 if (ret < 0 && ret != -ENODATA) {
1555                         dev_err(dev, "prepare clock stop failed %d", ret);
1556                         return ret;
1557                 }
1558
1559                 ret = sdw_bus_clk_stop(&ctrl->bus);
1560                 if (ret < 0 && ret != -ENODATA) {
1561                         dev_err(dev, "bus clock stop failed %d", ret);
1562                         return ret;
1563                 }
1564         }
1565
1566         clk_disable_unprepare(ctrl->hclk);
1567
1568         usleep_range(300, 305);
1569
1570         if (ctrl->wake_irq > 0) {
1571                 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1572                         enable_irq(ctrl->wake_irq);
1573         }
1574
1575         return 0;
1576 }
1577
1578 static const struct dev_pm_ops swrm_dev_pm_ops = {
1579         SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL)
1580 };
1581
1582 static const struct of_device_id qcom_swrm_of_match[] = {
1583         { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1584         { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1585         { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
1586         {/* sentinel */},
1587 };
1588
1589 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
1590
1591 static struct platform_driver qcom_swrm_driver = {
1592         .probe  = &qcom_swrm_probe,
1593         .remove = &qcom_swrm_remove,
1594         .driver = {
1595                 .name   = "qcom-soundwire",
1596                 .of_match_table = qcom_swrm_of_match,
1597                 .pm = &swrm_dev_pm_ops,
1598         }
1599 };
1600 module_platform_driver(qcom_swrm_driver);
1601
1602 MODULE_DESCRIPTION("Qualcomm soundwire driver");
1603 MODULE_LICENSE("GPL v2");