drivers/soundwire/qcom.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2019, Linaro Limited
   3
   4 #include <linux/clk.h>
   5 #include <linux/completion.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/io.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/debugfs.h>
  11 #include <linux/of.h>
  12 #include <linux/of_irq.h>
  13 #include <linux/of_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regmap.h>
  16 #include <linux/reset.h>
  17 #include <linux/slab.h>
  18 #include <linux/pm_wakeirq.h>
  19 #include <linux/slimbus.h>
  20 #include <linux/soundwire/sdw.h>
  21 #include <linux/soundwire/sdw_registers.h>
  22 #include <sound/pcm_params.h>
  23 #include <sound/soc.h>
  24 #include "bus.h"
  25
  26 #define SWRM_COMP_SW_RESET                                      0x008
  27 #define SWRM_COMP_STATUS                                        0x014
  28 #define SWRM_LINK_MANAGER_EE                                    0x018
  29 #define SWRM_EE_CPU                                             1
  30 #define SWRM_FRM_GEN_ENABLED                                    BIT(0)
  31 #define SWRM_VERSION_1_3_0                                      0x01030000
  32 #define SWRM_VERSION_1_5_1                                      0x01050001
  33 #define SWRM_VERSION_1_7_0                                      0x01070000
  34 #define SWRM_VERSION_2_0_0                                      0x02000000
  35 #define SWRM_COMP_HW_VERSION                                    0x00
  36 #define SWRM_COMP_CFG_ADDR                                      0x04
  37 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK                    BIT(1)
  38 #define SWRM_COMP_CFG_ENABLE_MSK                                BIT(0)
  39 #define SWRM_COMP_PARAMS                                        0x100
  40 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH                          GENMASK(14, 10)
  41 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH                          GENMASK(19, 15)
  42 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK                        GENMASK(4, 0)
  43 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK                         GENMASK(9, 5)
  44 #define SWRM_COMP_MASTER_ID                                     0x104
  45 #define SWRM_V1_3_INTERRUPT_STATUS                              0x200
  46 #define SWRM_V2_0_INTERRUPT_STATUS                              0x5000
  47 #define SWRM_INTERRUPT_STATUS_RMSK                              GENMASK(16, 0)
  48 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ                    BIT(0)
  49 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED                BIT(1)
  50 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS          BIT(2)
  51 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET                  BIT(3)
  52 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  BIT(4)
  53 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 BIT(5)
  54 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW              BIT(6)
  55 #define SWRM_INTERRUPT_STATUS_CMD_ERROR                         BIT(7)
  56 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION               BIT(8)
  57 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH         BIT(9)
  58 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           BIT(10)
  59 #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED                  BIT(11)
  60 #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL           BIT(12)
  61 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2             BIT(13)
  62 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2              BIT(14)
  63 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP               BIT(16)
  64 #define SWRM_INTERRUPT_MAX                                      17
  65 #define SWRM_V1_3_INTERRUPT_MASK_ADDR                           0x204
  66 #define SWRM_V1_3_INTERRUPT_CLEAR                               0x208
  67 #define SWRM_V2_0_INTERRUPT_CLEAR                               0x5008
  68 #define SWRM_V1_3_INTERRUPT_CPU_EN                              0x210
  69 #define SWRM_V2_0_INTERRUPT_CPU_EN                              0x5004
  70 #define SWRM_V1_3_CMD_FIFO_WR_CMD                               0x300
  71 #define SWRM_V2_0_CMD_FIFO_WR_CMD                               0x5020
  72 #define SWRM_V1_3_CMD_FIFO_RD_CMD                               0x304
  73 #define SWRM_V2_0_CMD_FIFO_RD_CMD                               0x5024
  74 #define SWRM_CMD_FIFO_CMD                                       0x308
  75 #define SWRM_CMD_FIFO_FLUSH                                     0x1
  76 #define SWRM_V1_3_CMD_FIFO_STATUS                               0x30C
  77 #define SWRM_V2_0_CMD_FIFO_STATUS                               0x5050
  78 #define SWRM_RD_CMD_FIFO_CNT_MASK                               GENMASK(20, 16)
  79 #define SWRM_WR_CMD_FIFO_CNT_MASK                               GENMASK(12, 8)
  80 #define SWRM_CMD_FIFO_CFG_ADDR                                  0x314
  81 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE                        BIT(31)
  82 #define SWRM_RD_WR_CMD_RETRIES                                  0x7
  83 #define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR                         0x318
  84 #define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR                         0x5040
  85 #define SWRM_RD_FIFO_CMD_ID_MASK                                GENMASK(11, 8)
  86 #define SWRM_ENUMERATOR_CFG_ADDR                                0x500
  87 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m)               (0x530 + 0x8 * (m))
  88 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m)               (0x534 + 0x8 * (m))
  89 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m)                (0x101C + 0x40 * (m))
  90 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK                  GENMASK(2, 0)
  91 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK                  GENMASK(7, 3)
  92 #define SWRM_MCP_BUS_CTRL                                       0x1044
  93 #define SWRM_MCP_BUS_CLK_START                                  BIT(1)
  94 #define SWRM_MCP_CFG_ADDR                                       0x1048
  95 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK               GENMASK(21, 17)
  96 #define SWRM_DEF_CMD_NO_PINGS                                   0x1f
  97 #define SWRM_MCP_STATUS                                         0x104C
  98 #define SWRM_MCP_STATUS_BANK_NUM_MASK                           BIT(0)
  99 #define SWRM_MCP_SLV_STATUS                                     0x1090
 100 #define SWRM_MCP_SLV_STATUS_MASK                                GENMASK(1, 0)
 101 #define SWRM_MCP_SLV_STATUS_SZ                                  2
 102 #define SWRM_DP_PORT_CTRL_BANK(n, m)    (0x1124 + 0x100 * (n - 1) + 0x40 * m)
 103 #define SWRM_DP_PORT_CTRL_2_BANK(n, m)  (0x1128 + 0x100 * (n - 1) + 0x40 * m)
 104 #define SWRM_DP_BLOCK_CTRL_1(n)         (0x112C + 0x100 * (n - 1))
 105 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m)  (0x1130 + 0x100 * (n - 1) + 0x40 * m)
 106 #define SWRM_DP_PORT_HCTRL_BANK(n, m)   (0x1134 + 0x100 * (n - 1) + 0x40 * m)
 107 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m)  (0x1138 + 0x100 * (n - 1) + 0x40 * m)
 108 #define SWRM_DP_SAMPLECTRL2_BANK(n, m)  (0x113C + 0x100 * (n - 1) + 0x40 * m)
 109 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n)   (0x1054 + 0x100 * (n - 1))
 110 #define SWR_V1_3_MSTR_MAX_REG_ADDR                              0x1740
 111 #define SWR_V2_0_MSTR_MAX_REG_ADDR                              0x50ac
 112
 113 #define SWRM_V2_0_CLK_CTRL                                      0x5060
 114 #define SWRM_V2_0_CLK_CTRL_CLK_START                            BIT(0)
 115 #define SWRM_V2_0_LINK_STATUS                                   0x5064
 116
 117 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT                          0x18
 118 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT                          0x10
 119 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT                          0x08
 120 #define SWRM_AHB_BRIDGE_WR_DATA_0                               0xc85
 121 #define SWRM_AHB_BRIDGE_WR_ADDR_0                               0xc89
 122 #define SWRM_AHB_BRIDGE_RD_ADDR_0                               0xc8d
 123 #define SWRM_AHB_BRIDGE_RD_DATA_0                               0xc91
 124
 125 #define SWRM_REG_VAL_PACK(data, dev, id, reg)   \
 126                         ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
 127
 128 #define MAX_FREQ_NUM                                            1
 129 #define TIMEOUT_MS                                              100
 130 #define QCOM_SWRM_MAX_RD_LEN                                    0x1
 131 #define QCOM_SDW_MAX_PORTS                                      14
 132 #define DEFAULT_CLK_FREQ                                        9600000
 133 #define SWRM_MAX_DAIS                                           0xF
 134 #define SWR_INVALID_PARAM                                       0xFF
 135 #define SWR_HSTOP_MAX_VAL                                       0xF
 136 #define SWR_HSTART_MIN_VAL                                      0x0
 137 #define SWR_BROADCAST_CMD_ID                                    0x0F
 138 #define SWR_MAX_CMD_ID                                          14
 139 #define MAX_FIFO_RD_RETRY                                       3
 140 #define SWR_OVERFLOW_RETRY_COUNT                                30
 141 #define SWRM_LINK_STATUS_RETRY_CNT                              100
 142
 143 enum {
 144         MASTER_ID_WSA = 1,
 145         MASTER_ID_RX,
 146         MASTER_ID_TX
 147 };
 148
 149 struct qcom_swrm_port_config {
 150         u16 si;
 151         u8 off1;
 152         u8 off2;
 153         u8 bp_mode;
 154         u8 hstart;
 155         u8 hstop;
 156         u8 word_length;
 157         u8 blk_group_count;
 158         u8 lane_control;
 159 };
 160
 161 /*
 162  * Internal IDs for different register layouts.  Only few registers differ per
 163  * each variant, so the list of IDs below does not include all of registers.
 164  */
 165 enum {
 166         SWRM_REG_FRAME_GEN_ENABLED,
 167         SWRM_REG_INTERRUPT_STATUS,
 168         SWRM_REG_INTERRUPT_MASK_ADDR,
 169         SWRM_REG_INTERRUPT_CLEAR,
 170         SWRM_REG_INTERRUPT_CPU_EN,
 171         SWRM_REG_CMD_FIFO_WR_CMD,
 172         SWRM_REG_CMD_FIFO_RD_CMD,
 173         SWRM_REG_CMD_FIFO_STATUS,
 174         SWRM_REG_CMD_FIFO_RD_FIFO_ADDR,
 175 };
 176
 177 struct qcom_swrm_ctrl {
 178         struct sdw_bus bus;
 179         struct device *dev;
 180         struct regmap *regmap;
 181         u32 max_reg;
 182         const unsigned int *reg_layout;
 183         void __iomem *mmio;
 184         struct reset_control *audio_cgcr;
 185 #ifdef CONFIG_DEBUG_FS
 186         struct dentry *debugfs;
 187 #endif
 188         struct completion broadcast;
 189         struct completion enumeration;
 190         /* Port alloc/free lock */
 191         struct mutex port_lock;
 192         struct clk *hclk;
 193         int irq;
 194         unsigned int version;
 195         int wake_irq;
 196         int num_din_ports;
 197         int num_dout_ports;
 198         int cols_index;
 199         int rows_index;
 200         unsigned long dout_port_mask;
 201         unsigned long din_port_mask;
 202         u32 intr_mask;
 203         u8 rcmd_id;
 204         u8 wcmd_id;
 205         struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS];
 206         struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
 207         enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
 208         int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
 209         int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
 210         u32 slave_status;
 211         u32 wr_fifo_depth;
 212         u32 rd_fifo_depth;
 213         bool clock_stop_not_supported;
 214 };
 215
 216 struct qcom_swrm_data {
 217         u32 default_cols;
 218         u32 default_rows;
 219         bool sw_clk_gate_required;
 220         u32 max_reg;
 221         const unsigned int *reg_layout;
 222 };
 223
 224 static const unsigned int swrm_v1_3_reg_layout[] = {
 225         [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_COMP_STATUS,
 226         [SWRM_REG_INTERRUPT_STATUS] = SWRM_V1_3_INTERRUPT_STATUS,
 227         [SWRM_REG_INTERRUPT_MASK_ADDR] = SWRM_V1_3_INTERRUPT_MASK_ADDR,
 228         [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V1_3_INTERRUPT_CLEAR,
 229         [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V1_3_INTERRUPT_CPU_EN,
 230         [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V1_3_CMD_FIFO_WR_CMD,
 231         [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD,
 232         [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V1_3_CMD_FIFO_STATUS,
 233         [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR,
 234 };
 235
 236 static const struct qcom_swrm_data swrm_v1_3_data = {
 237         .default_rows = 48,
 238         .default_cols = 16,
 239         .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
 240         .reg_layout = swrm_v1_3_reg_layout,
 241 };
 242
 243 static const struct qcom_swrm_data swrm_v1_5_data = {
 244         .default_rows = 50,
 245         .default_cols = 16,
 246         .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
 247         .reg_layout = swrm_v1_3_reg_layout,
 248 };
 249
 250 static const struct qcom_swrm_data swrm_v1_6_data = {
 251         .default_rows = 50,
 252         .default_cols = 16,
 253         .sw_clk_gate_required = true,
 254         .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
 255         .reg_layout = swrm_v1_3_reg_layout,
 256 };
 257
 258 static const unsigned int swrm_v2_0_reg_layout[] = {
 259         [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS,
 260         [SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS,
 261         [SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */
 262         [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR,
 263         [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN,
 264         [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD,
 265         [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD,
 266         [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS,
 267         [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR,
 268 };
 269
 270 static const struct qcom_swrm_data swrm_v2_0_data = {
 271         .default_rows = 50,
 272         .default_cols = 16,
 273         .sw_clk_gate_required = true,
 274         .max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR,
 275         .reg_layout = swrm_v2_0_reg_layout,
 276 };
 277
 278 #define to_qcom_sdw(b)  container_of(b, struct qcom_swrm_ctrl, bus)
 279
 280 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 281                                   u32 *val)
 282 {
 283         struct regmap *wcd_regmap = ctrl->regmap;
 284         int ret;
 285
 286         /* pg register + offset */
 287         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
 288                           (u8 *)&reg, 4);
 289         if (ret < 0)
 290                 return SDW_CMD_FAIL;
 291
 292         ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
 293                                val, 4);
 294         if (ret < 0)
 295                 return SDW_CMD_FAIL;
 296
 297         return SDW_CMD_OK;
 298 }
 299
 300 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
 301                                    int reg, int val)
 302 {
 303         struct regmap *wcd_regmap = ctrl->regmap;
 304         int ret;
 305         /* pg register + offset */
 306         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
 307                           (u8 *)&val, 4);
 308         if (ret)
 309                 return SDW_CMD_FAIL;
 310
 311         /* write address register */
 312         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
 313                           (u8 *)&reg, 4);
 314         if (ret)
 315                 return SDW_CMD_FAIL;
 316
 317         return SDW_CMD_OK;
 318 }
 319
 320 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 321                                   u32 *val)
 322 {
 323         *val = readl(ctrl->mmio + reg);
 324         return SDW_CMD_OK;
 325 }
 326
 327 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
 328                                    int val)
 329 {
 330         writel(val, ctrl->mmio + reg);
 331         return SDW_CMD_OK;
 332 }
 333
 334 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
 335                                    u8 dev_addr, u16 reg_addr)
 336 {
 337         u32 val;
 338         u8 id = *cmd_id;
 339
 340         if (id != SWR_BROADCAST_CMD_ID) {
 341                 if (id < SWR_MAX_CMD_ID)
 342                         id += 1;
 343                 else
 344                         id = 0;
 345                 *cmd_id = id;
 346         }
 347         val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
 348
 349         return val;
 350 }
 351
 352 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl)
 353 {
 354         u32 fifo_outstanding_data, value;
 355         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 356
 357         do {
 358                 /* Check for fifo underflow during read */
 359                 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 360                                &value);
 361                 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
 362
 363                 /* Check if read data is available in read fifo */
 364                 if (fifo_outstanding_data > 0)
 365                         return 0;
 366
 367                 usleep_range(500, 510);
 368         } while (fifo_retry_count--);
 369
 370         if (fifo_outstanding_data == 0) {
 371                 dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__);
 372                 return -EIO;
 373         }
 374
 375         return 0;
 376 }
 377
 378 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl)
 379 {
 380         u32 fifo_outstanding_cmds, value;
 381         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 382
 383         do {
 384                 /* Check for fifo overflow during write */
 385                 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 386                                &value);
 387                 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
 388
 389                 /* Check for space in write fifo before writing */
 390                 if (fifo_outstanding_cmds < ctrl->wr_fifo_depth)
 391                         return 0;
 392
 393                 usleep_range(500, 510);
 394         } while (fifo_retry_count--);
 395
 396         if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) {
 397                 dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__);
 398                 return -EIO;
 399         }
 400
 401         return 0;
 402 }
 403
 404 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,
 405                                      u8 dev_addr, u16 reg_addr)
 406 {
 407
 408         u32 val;
 409         int ret = 0;
 410         u8 cmd_id = 0x0;
 411
 412         if (dev_addr == SDW_BROADCAST_DEV_NUM) {
 413                 cmd_id = SWR_BROADCAST_CMD_ID;
 414                 val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
 415                                               dev_addr, reg_addr);
 416         } else {
 417                 val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data,
 418                                               dev_addr, reg_addr);
 419         }
 420
 421         if (swrm_wait_for_wr_fifo_avail(ctrl))
 422                 return SDW_CMD_FAIL_OTHER;
 423
 424         if (cmd_id == SWR_BROADCAST_CMD_ID)
 425                 reinit_completion(&ctrl->broadcast);
 426
 427         /* Its assumed that write is okay as we do not get any status back */
 428         ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val);
 429
 430         if (ctrl->version <= SWRM_VERSION_1_3_0)
 431                 usleep_range(150, 155);
 432
 433         if (cmd_id == SWR_BROADCAST_CMD_ID) {
 434                 /*
 435                  * sleep for 10ms for MSM soundwire variant to allow broadcast
 436                  * command to complete.
 437                  */
 438                 ret = wait_for_completion_timeout(&ctrl->broadcast,
 439                                                   msecs_to_jiffies(TIMEOUT_MS));
 440                 if (!ret)
 441                         ret = SDW_CMD_IGNORED;
 442                 else
 443                         ret = SDW_CMD_OK;
 444
 445         } else {
 446                 ret = SDW_CMD_OK;
 447         }
 448         return ret;
 449 }
 450
 451 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,
 452                                      u8 dev_addr, u16 reg_addr,
 453                                      u32 len, u8 *rval)
 454 {
 455         u32 cmd_data, cmd_id, val, retry_attempt = 0;
 456
 457         val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr);
 458
 459         /*
 460          * Check for outstanding cmd wrt. write fifo depth to avoid
 461          * overflow as read will also increase write fifo cnt.
 462          */
 463         swrm_wait_for_wr_fifo_avail(ctrl);
 464
 465         /* wait for FIFO RD to complete to avoid overflow */
 466         usleep_range(100, 105);
 467         ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val);
 468         /* wait for FIFO RD CMD complete to avoid overflow */
 469         usleep_range(250, 255);
 470
 471         if (swrm_wait_for_rd_fifo_avail(ctrl))
 472                 return SDW_CMD_FAIL_OTHER;
 473
 474         do {
 475                 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR],
 476                                &cmd_data);
 477                 rval[0] = cmd_data & 0xFF;
 478                 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
 479
 480                 if (cmd_id != ctrl->rcmd_id) {
 481                         if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
 482                                 /* wait 500 us before retry on fifo read failure */
 483                                 usleep_range(500, 505);
 484                                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD,
 485                                                 SWRM_CMD_FIFO_FLUSH);
 486                                 ctrl->reg_write(ctrl,
 487                                                 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD],
 488                                                 val);
 489                         }
 490                         retry_attempt++;
 491                 } else {
 492                         return SDW_CMD_OK;
 493                 }
 494
 495         } while (retry_attempt < MAX_FIFO_RD_RETRY);
 496
 497         dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
 498                 dev_num: 0x%x, cmd_data: 0x%x\n",
 499                 reg_addr, ctrl->rcmd_id, dev_addr, cmd_data);
 500
 501         return SDW_CMD_IGNORED;
 502 }
 503
 504 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
 505 {
 506         u32 val, status;
 507         int dev_num;
 508
 509         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 510
 511         for (dev_num = 1; dev_num <= SDW_MAX_DEVICES; dev_num++) {
 512                 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
 513
 514                 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
 515                         ctrl->status[dev_num] = status;
 516                         return dev_num;
 517                 }
 518         }
 519
 520         return -EINVAL;
 521 }
 522
 523 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
 524 {
 525         u32 val;
 526         int i;
 527
 528         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 529         ctrl->slave_status = val;
 530
 531         for (i = 1; i <= SDW_MAX_DEVICES; i++) {
 532                 u32 s;
 533
 534                 s = (val >> (i * 2));
 535                 s &= SWRM_MCP_SLV_STATUS_MASK;
 536                 ctrl->status[i] = s;
 537         }
 538 }
 539
 540 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
 541                                         struct sdw_slave *slave, int devnum)
 542 {
 543         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 544         u32 status;
 545
 546         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
 547         status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
 548         status &= SWRM_MCP_SLV_STATUS_MASK;
 549
 550         if (status == SDW_SLAVE_ATTACHED) {
 551                 if (slave)
 552                         slave->dev_num = devnum;
 553                 mutex_lock(&bus->bus_lock);
 554                 set_bit(devnum, bus->assigned);
 555                 mutex_unlock(&bus->bus_lock);
 556         }
 557 }
 558
 559 static int qcom_swrm_enumerate(struct sdw_bus *bus)
 560 {
 561         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 562         struct sdw_slave *slave, *_s;
 563         struct sdw_slave_id id;
 564         u32 val1, val2;
 565         bool found;
 566         u64 addr;
 567         int i;
 568         char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
 569
 570         for (i = 1; i <= SDW_MAX_DEVICES; i++) {
 571                 /* do not continue if the status is Not Present  */
 572                 if (!ctrl->status[i])
 573                         continue;
 574
 575                 /*SCP_Devid5 - Devid 4*/
 576                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
 577
 578                 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
 579                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
 580
 581                 if (!val1 && !val2)
 582                         break;
 583
 584                 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
 585                         ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
 586                         ((u64)buf1[0] << 40);
 587
 588                 sdw_extract_slave_id(bus, addr, &id);
 589                 found = false;
 590                 /* Now compare with entries */
 591                 list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
 592                         if (sdw_compare_devid(slave, id) == 0) {
 593                                 qcom_swrm_set_slave_dev_num(bus, slave, i);
 594                                 found = true;
 595                                 break;
 596                         }
 597                 }
 598
 599                 if (!found) {
 600                         qcom_swrm_set_slave_dev_num(bus, NULL, i);
 601                         sdw_slave_add(bus, &id, NULL);
 602                 }
 603         }
 604
 605         complete(&ctrl->enumeration);
 606         return 0;
 607 }
 608
 609 static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id)
 610 {
 611         struct qcom_swrm_ctrl *ctrl = dev_id;
 612         int ret;
 613
 614         ret = pm_runtime_resume_and_get(ctrl->dev);
 615         if (ret < 0 && ret != -EACCES) {
 616                 dev_err_ratelimited(ctrl->dev,
 617                                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
 618                                     __func__, ret);
 619                 return ret;
 620         }
 621
 622         if (ctrl->wake_irq > 0) {
 623                 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
 624                         disable_irq_nosync(ctrl->wake_irq);
 625         }
 626
 627         pm_runtime_mark_last_busy(ctrl->dev);
 628         pm_runtime_put_autosuspend(ctrl->dev);
 629
 630         return IRQ_HANDLED;
 631 }
 632
 633 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
 634 {
 635         struct qcom_swrm_ctrl *ctrl = dev_id;
 636         u32 value, intr_sts, intr_sts_masked, slave_status;
 637         u32 i;
 638         int devnum;
 639         int ret = IRQ_HANDLED;
 640         clk_prepare_enable(ctrl->hclk);
 641
 642         ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
 643                        &intr_sts);
 644         intr_sts_masked = intr_sts & ctrl->intr_mask;
 645
 646         do {
 647                 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
 648                         value = intr_sts_masked & BIT(i);
 649                         if (!value)
 650                                 continue;
 651
 652                         switch (value) {
 653                         case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
 654                                 devnum = qcom_swrm_get_alert_slave_dev_num(ctrl);
 655                                 if (devnum < 0) {
 656                                         dev_err_ratelimited(ctrl->dev,
 657                                             "no slave alert found.spurious interrupt\n");
 658                                 } else {
 659                                         sdw_handle_slave_status(&ctrl->bus, ctrl->status);
 660                                 }
 661
 662                                 break;
 663                         case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
 664                         case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
 665                                 dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n");
 666                                 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status);
 667                                 if (ctrl->slave_status == slave_status) {
 668                                         dev_dbg(ctrl->dev, "Slave status not changed %x\n",
 669                                                 slave_status);
 670                                 } else {
 671                                         qcom_swrm_get_device_status(ctrl);
 672                                         qcom_swrm_enumerate(&ctrl->bus);
 673                                         sdw_handle_slave_status(&ctrl->bus, ctrl->status);
 674                                 }
 675                                 break;
 676                         case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
 677                                 dev_err_ratelimited(ctrl->dev,
 678                                                 "%s: SWR bus clsh detected\n",
 679                                                 __func__);
 680                                 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
 681                                 ctrl->reg_write(ctrl,
 682                                                 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
 683                                                 ctrl->intr_mask);
 684                                 break;
 685                         case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
 686                                 ctrl->reg_read(ctrl,
 687                                                ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 688                                                &value);
 689                                 dev_err_ratelimited(ctrl->dev,
 690                                         "%s: SWR read FIFO overflow fifo status 0x%x\n",
 691                                         __func__, value);
 692                                 break;
 693                         case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
 694                                 ctrl->reg_read(ctrl,
 695                                                ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 696                                                &value);
 697                                 dev_err_ratelimited(ctrl->dev,
 698                                         "%s: SWR read FIFO underflow fifo status 0x%x\n",
 699                                         __func__, value);
 700                                 break;
 701                         case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
 702                                 ctrl->reg_read(ctrl,
 703                                                ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 704                                                &value);
 705                                 dev_err(ctrl->dev,
 706                                         "%s: SWR write FIFO overflow fifo status %x\n",
 707                                         __func__, value);
 708                                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
 709                                 break;
 710                         case SWRM_INTERRUPT_STATUS_CMD_ERROR:
 711                                 ctrl->reg_read(ctrl,
 712                                                ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 713                                                &value);
 714                                 dev_err_ratelimited(ctrl->dev,
 715                                         "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
 716                                         __func__, value);
 717                                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
 718                                 break;
 719                         case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
 720                                 dev_err_ratelimited(ctrl->dev,
 721                                                 "%s: SWR Port collision detected\n",
 722                                                 __func__);
 723                                 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
 724                                 ctrl->reg_write(ctrl,
 725                                                 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
 726                                                 ctrl->intr_mask);
 727                                 break;
 728                         case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
 729                                 dev_err_ratelimited(ctrl->dev,
 730                                         "%s: SWR read enable valid mismatch\n",
 731                                         __func__);
 732                                 ctrl->intr_mask &=
 733                                         ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
 734                                 ctrl->reg_write(ctrl,
 735                                                 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
 736                                                 ctrl->intr_mask);
 737                                 break;
 738                         case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
 739                                 complete(&ctrl->broadcast);
 740                                 break;
 741                         case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
 742                                 break;
 743                         case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
 744                                 break;
 745                         case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
 746                                 break;
 747                         default:
 748                                 dev_err_ratelimited(ctrl->dev,
 749                                                 "%s: SWR unknown interrupt value: %d\n",
 750                                                 __func__, value);
 751                                 ret = IRQ_NONE;
 752                                 break;
 753                         }
 754                 }
 755                 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
 756                                 intr_sts);
 757                 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
 758                                &intr_sts);
 759                 intr_sts_masked = intr_sts & ctrl->intr_mask;
 760         } while (intr_sts_masked);
 761
 762         clk_disable_unprepare(ctrl->hclk);
 763         return ret;
 764 }
 765
 766 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
 767 {
 768         u32 val;
 769
 770         /* Clear Rows and Cols */
 771         val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
 772         val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
 773
 774         reset_control_reset(ctrl->audio_cgcr);
 775
 776         ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
 777
 778         /* Enable Auto enumeration */
 779         ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
 780
 781         ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
 782         /* Mask soundwire interrupts */
 783         if (ctrl->version < SWRM_VERSION_2_0_0)
 784                 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
 785                                 SWRM_INTERRUPT_STATUS_RMSK);
 786
 787         /* Configure No pings */
 788         ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
 789         u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
 790         ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
 791
 792         if (ctrl->version == SWRM_VERSION_1_7_0) {
 793                 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
 794                 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
 795                                 SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
 796         } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
 797                 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
 798                 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
 799                                 SWRM_V2_0_CLK_CTRL_CLK_START);
 800         } else {
 801                 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
 802         }
 803
 804         /* Configure number of retries of a read/write cmd */
 805         if (ctrl->version >= SWRM_VERSION_1_5_1) {
 806                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 807                                 SWRM_RD_WR_CMD_RETRIES |
 808                                 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
 809         } else {
 810                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 811                                 SWRM_RD_WR_CMD_RETRIES);
 812         }
 813
 814         /* Set IRQ to PULSE */
 815         ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
 816                         SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
 817                         SWRM_COMP_CFG_ENABLE_MSK);
 818
 819         /* enable CPU IRQs */
 820         if (ctrl->mmio) {
 821                 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
 822                                 SWRM_INTERRUPT_STATUS_RMSK);
 823         }
 824         ctrl->slave_status = 0;
 825         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
 826         ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
 827         ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
 828
 829         return 0;
 830 }
 831
 832 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
 833                                                     struct sdw_msg *msg)
 834 {
 835         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 836         int ret, i, len;
 837
 838         if (msg->flags == SDW_MSG_FLAG_READ) {
 839                 for (i = 0; i < msg->len;) {
 840                         if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
 841                                 len = msg->len - i;
 842                         else
 843                                 len = QCOM_SWRM_MAX_RD_LEN;
 844
 845                         ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
 846                                                         msg->addr + i, len,
 847                                                        &msg->buf[i]);
 848                         if (ret)
 849                                 return ret;
 850
 851                         i = i + len;
 852                 }
 853         } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
 854                 for (i = 0; i < msg->len; i++) {
 855                         ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
 856                                                         msg->dev_num,
 857                                                        msg->addr + i);
 858                         if (ret)
 859                                 return SDW_CMD_IGNORED;
 860                 }
 861         }
 862
 863         return SDW_CMD_OK;
 864 }
 865
 866 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
 867 {
 868         u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
 869         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 870         u32 val;
 871
 872         ctrl->reg_read(ctrl, reg, &val);
 873
 874         u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
 875         u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
 876
 877         return ctrl->reg_write(ctrl, reg, val);
 878 }
 879
 880 static int qcom_swrm_port_params(struct sdw_bus *bus,
 881                                  struct sdw_port_params *p_params,
 882                                  unsigned int bank)
 883 {
 884         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 885
 886         return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
 887                                p_params->bps - 1);
 888
 889 }
 890
 891 static int qcom_swrm_transport_params(struct sdw_bus *bus,
 892                                       struct sdw_transport_params *params,
 893                                       enum sdw_reg_bank bank)
 894 {
 895         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 896         struct qcom_swrm_port_config *pcfg;
 897         u32 value;
 898         int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
 899         int ret;
 900
 901         pcfg = &ctrl->pconfig[params->port_num];
 902
 903         value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
 904         value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
 905         value |= pcfg->si & 0xff;
 906
 907         ret = ctrl->reg_write(ctrl, reg, value);
 908         if (ret)
 909                 goto err;
 910
 911         if (pcfg->si > 0xff) {
 912                 value = (pcfg->si >> 8) & 0xff;
 913                 reg = SWRM_DP_SAMPLECTRL2_BANK(params->port_num, bank);
 914                 ret = ctrl->reg_write(ctrl, reg, value);
 915                 if (ret)
 916                         goto err;
 917         }
 918
 919         if (pcfg->lane_control != SWR_INVALID_PARAM) {
 920                 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
 921                 value = pcfg->lane_control;
 922                 ret = ctrl->reg_write(ctrl, reg, value);
 923                 if (ret)
 924                         goto err;
 925         }
 926
 927         if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
 928                 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
 929                 value = pcfg->blk_group_count;
 930                 ret = ctrl->reg_write(ctrl, reg, value);
 931                 if (ret)
 932                         goto err;
 933         }
 934
 935         if (pcfg->hstart != SWR_INVALID_PARAM
 936                         && pcfg->hstop != SWR_INVALID_PARAM) {
 937                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
 938                 value = (pcfg->hstop << 4) | pcfg->hstart;
 939                 ret = ctrl->reg_write(ctrl, reg, value);
 940         } else {
 941                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
 942                 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
 943                 ret = ctrl->reg_write(ctrl, reg, value);
 944         }
 945
 946         if (ret)
 947                 goto err;
 948
 949         if (pcfg->bp_mode != SWR_INVALID_PARAM) {
 950                 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
 951                 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
 952         }
 953
 954 err:
 955         return ret;
 956 }
 957
 958 static int qcom_swrm_port_enable(struct sdw_bus *bus,
 959                                  struct sdw_enable_ch *enable_ch,
 960                                  unsigned int bank)
 961 {
 962         u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
 963         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 964         u32 val;
 965
 966         ctrl->reg_read(ctrl, reg, &val);
 967
 968         if (enable_ch->enable)
 969                 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 970         else
 971                 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 972
 973         return ctrl->reg_write(ctrl, reg, val);
 974 }
 975
 976 static const struct sdw_master_port_ops qcom_swrm_port_ops = {
 977         .dpn_set_port_params = qcom_swrm_port_params,
 978         .dpn_set_port_transport_params = qcom_swrm_transport_params,
 979         .dpn_port_enable_ch = qcom_swrm_port_enable,
 980 };
 981
 982 static const struct sdw_master_ops qcom_swrm_ops = {
 983         .xfer_msg = qcom_swrm_xfer_msg,
 984         .pre_bank_switch = qcom_swrm_pre_bank_switch,
 985 };
 986
 987 static int qcom_swrm_compute_params(struct sdw_bus *bus)
 988 {
 989         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 990         struct sdw_master_runtime *m_rt;
 991         struct sdw_slave_runtime *s_rt;
 992         struct sdw_port_runtime *p_rt;
 993         struct qcom_swrm_port_config *pcfg;
 994         struct sdw_slave *slave;
 995         unsigned int m_port;
 996         int i = 1;
 997
 998         list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
 999                 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
1000                         pcfg = &ctrl->pconfig[p_rt->num];
1001                         p_rt->transport_params.port_num = p_rt->num;
1002                         if (pcfg->word_length != SWR_INVALID_PARAM) {
1003                                 sdw_fill_port_params(&p_rt->port_params,
1004                                              p_rt->num,  pcfg->word_length + 1,
1005                                              SDW_PORT_FLOW_MODE_ISOCH,
1006                                              SDW_PORT_DATA_MODE_NORMAL);
1007                         }
1008
1009                 }
1010
1011                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
1012                         slave = s_rt->slave;
1013                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
1014                                 m_port = slave->m_port_map[p_rt->num];
1015                                 /* port config starts at offset 0 so -1 from actual port number */
1016                                 if (m_port)
1017                                         pcfg = &ctrl->pconfig[m_port];
1018                                 else
1019                                         pcfg = &ctrl->pconfig[i];
1020                                 p_rt->transport_params.port_num = p_rt->num;
1021                                 p_rt->transport_params.sample_interval =
1022                                         pcfg->si + 1;
1023                                 p_rt->transport_params.offset1 = pcfg->off1;
1024                                 p_rt->transport_params.offset2 = pcfg->off2;
1025                                 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
1026                                 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
1027
1028                                 p_rt->transport_params.hstart = pcfg->hstart;
1029                                 p_rt->transport_params.hstop = pcfg->hstop;
1030                                 p_rt->transport_params.lane_ctrl = pcfg->lane_control;
1031                                 if (pcfg->word_length != SWR_INVALID_PARAM) {
1032                                         sdw_fill_port_params(&p_rt->port_params,
1033                                                      p_rt->num,
1034                                                      pcfg->word_length + 1,
1035                                                      SDW_PORT_FLOW_MODE_ISOCH,
1036                                                      SDW_PORT_DATA_MODE_NORMAL);
1037                                 }
1038                                 i++;
1039                         }
1040                 }
1041         }
1042
1043         return 0;
1044 }
1045
1046 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
1047         DEFAULT_CLK_FREQ,
1048 };
1049
1050 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
1051                                         struct sdw_stream_runtime *stream)
1052 {
1053         struct sdw_master_runtime *m_rt;
1054         struct sdw_port_runtime *p_rt;
1055         unsigned long *port_mask;
1056
1057         mutex_lock(&ctrl->port_lock);
1058
1059         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1060                 if (m_rt->direction == SDW_DATA_DIR_RX)
1061                         port_mask = &ctrl->dout_port_mask;
1062                 else
1063                         port_mask = &ctrl->din_port_mask;
1064
1065                 list_for_each_entry(p_rt, &m_rt->port_list, port_node)
1066                         clear_bit(p_rt->num, port_mask);
1067         }
1068
1069         mutex_unlock(&ctrl->port_lock);
1070 }
1071
1072 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
1073                                         struct sdw_stream_runtime *stream,
1074                                        struct snd_pcm_hw_params *params,
1075                                        int direction)
1076 {
1077         struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
1078         struct sdw_stream_config sconfig;
1079         struct sdw_master_runtime *m_rt;
1080         struct sdw_slave_runtime *s_rt;
1081         struct sdw_port_runtime *p_rt;
1082         struct sdw_slave *slave;
1083         unsigned long *port_mask;
1084         int i, maxport, pn, nports = 0, ret = 0;
1085         unsigned int m_port;
1086
1087         mutex_lock(&ctrl->port_lock);
1088         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1089                 if (m_rt->direction == SDW_DATA_DIR_RX) {
1090                         maxport = ctrl->num_dout_ports;
1091                         port_mask = &ctrl->dout_port_mask;
1092                 } else {
1093                         maxport = ctrl->num_din_ports;
1094                         port_mask = &ctrl->din_port_mask;
1095                 }
1096
1097                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
1098                         slave = s_rt->slave;
1099                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
1100                                 m_port = slave->m_port_map[p_rt->num];
1101                                 /* Port numbers start from 1 - 14*/
1102                                 if (m_port)
1103                                         pn = m_port;
1104                                 else
1105                                         pn = find_first_zero_bit(port_mask, maxport);
1106
1107                                 if (pn > maxport) {
1108                                         dev_err(ctrl->dev, "All ports busy\n");
1109                                         ret = -EBUSY;
1110                                         goto err;
1111                                 }
1112                                 set_bit(pn, port_mask);
1113                                 pconfig[nports].num = pn;
1114                                 pconfig[nports].ch_mask = p_rt->ch_mask;
1115                                 nports++;
1116                         }
1117                 }
1118         }
1119
1120         if (direction == SNDRV_PCM_STREAM_CAPTURE)
1121                 sconfig.direction = SDW_DATA_DIR_TX;
1122         else
1123                 sconfig.direction = SDW_DATA_DIR_RX;
1124
1125         /* hw parameters wil be ignored as we only support PDM */
1126         sconfig.ch_count = 1;
1127         sconfig.frame_rate = params_rate(params);
1128         sconfig.type = stream->type;
1129         sconfig.bps = 1;
1130         sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
1131                               nports, stream);
1132 err:
1133         if (ret) {
1134                 for (i = 0; i < nports; i++)
1135                         clear_bit(pconfig[i].num, port_mask);
1136         }
1137
1138         mutex_unlock(&ctrl->port_lock);
1139
1140         return ret;
1141 }
1142
1143 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
1144                                struct snd_pcm_hw_params *params,
1145                               struct snd_soc_dai *dai)
1146 {
1147         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1148         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1149         int ret;
1150
1151         ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
1152                                            substream->stream);
1153         if (ret)
1154                 qcom_swrm_stream_free_ports(ctrl, sruntime);
1155
1156         return ret;
1157 }
1158
1159 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
1160                              struct snd_soc_dai *dai)
1161 {
1162         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1163         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1164
1165         qcom_swrm_stream_free_ports(ctrl, sruntime);
1166         sdw_stream_remove_master(&ctrl->bus, sruntime);
1167
1168         return 0;
1169 }
1170
1171 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
1172                                     void *stream, int direction)
1173 {
1174         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1175
1176         ctrl->sruntime[dai->id] = stream;
1177
1178         return 0;
1179 }
1180
1181 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
1182 {
1183         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1184
1185         return ctrl->sruntime[dai->id];
1186 }
1187
1188 static int qcom_swrm_startup(struct snd_pcm_substream *substream,
1189                              struct snd_soc_dai *dai)
1190 {
1191         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1192         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1193         struct sdw_stream_runtime *sruntime;
1194         struct snd_soc_dai *codec_dai;
1195         int ret, i;
1196
1197         ret = pm_runtime_resume_and_get(ctrl->dev);
1198         if (ret < 0 && ret != -EACCES) {
1199                 dev_err_ratelimited(ctrl->dev,
1200                                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
1201                                     __func__, ret);
1202                 return ret;
1203         }
1204
1205         sruntime = sdw_alloc_stream(dai->name);
1206         if (!sruntime)
1207                 return -ENOMEM;
1208
1209         ctrl->sruntime[dai->id] = sruntime;
1210
1211         for_each_rtd_codec_dais(rtd, i, codec_dai) {
1212                 ret = snd_soc_dai_set_stream(codec_dai, sruntime,
1213                                              substream->stream);
1214                 if (ret < 0 && ret != -ENOTSUPP) {
1215                         dev_err(dai->dev, "Failed to set sdw stream on %s\n",
1216                                 codec_dai->name);
1217                         sdw_release_stream(sruntime);
1218                         return ret;
1219                 }
1220         }
1221
1222         return 0;
1223 }
1224
1225 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
1226                                struct snd_soc_dai *dai)
1227 {
1228         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1229
1230         sdw_release_stream(ctrl->sruntime[dai->id]);
1231         ctrl->sruntime[dai->id] = NULL;
1232         pm_runtime_mark_last_busy(ctrl->dev);
1233         pm_runtime_put_autosuspend(ctrl->dev);
1234
1235 }
1236
1237 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
1238         .hw_params = qcom_swrm_hw_params,
1239         .hw_free = qcom_swrm_hw_free,
1240         .startup = qcom_swrm_startup,
1241         .shutdown = qcom_swrm_shutdown,
1242         .set_stream = qcom_swrm_set_sdw_stream,
1243         .get_stream = qcom_swrm_get_sdw_stream,
1244 };
1245
1246 static const struct snd_soc_component_driver qcom_swrm_dai_component = {
1247         .name = "soundwire",
1248 };
1249
1250 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1251 {
1252         int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1253         struct snd_soc_dai_driver *dais;
1254         struct snd_soc_pcm_stream *stream;
1255         struct device *dev = ctrl->dev;
1256         int i;
1257
1258         /* PDM dais are only tested for now */
1259         dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
1260         if (!dais)
1261                 return -ENOMEM;
1262
1263         for (i = 0; i < num_dais; i++) {
1264                 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
1265                 if (!dais[i].name)
1266                         return -ENOMEM;
1267
1268                 if (i < ctrl->num_dout_ports)
1269                         stream = &dais[i].playback;
1270                 else
1271                         stream = &dais[i].capture;
1272
1273                 stream->channels_min = 1;
1274                 stream->channels_max = 1;
1275                 stream->rates = SNDRV_PCM_RATE_48000;
1276                 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
1277
1278                 dais[i].ops = &qcom_swrm_pdm_dai_ops;
1279                 dais[i].id = i;
1280         }
1281
1282         return devm_snd_soc_register_component(ctrl->dev,
1283                                                 &qcom_swrm_dai_component,
1284                                                 dais, num_dais);
1285 }
1286
1287 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1288 {
1289         struct device_node *np = ctrl->dev->of_node;
1290         u8 off1[QCOM_SDW_MAX_PORTS];
1291         u8 off2[QCOM_SDW_MAX_PORTS];
1292         u16 si[QCOM_SDW_MAX_PORTS];
1293         u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
1294         u8 hstart[QCOM_SDW_MAX_PORTS];
1295         u8 hstop[QCOM_SDW_MAX_PORTS];
1296         u8 word_length[QCOM_SDW_MAX_PORTS];
1297         u8 blk_group_count[QCOM_SDW_MAX_PORTS];
1298         u8 lane_control[QCOM_SDW_MAX_PORTS];
1299         int i, ret, nports, val;
1300         bool si_16 = false;
1301
1302         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1303
1304         ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1305         ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1306
1307         ret = of_property_read_u32(np, "qcom,din-ports", &val);
1308         if (ret)
1309                 return ret;
1310
1311         if (val > ctrl->num_din_ports)
1312                 return -EINVAL;
1313
1314         ctrl->num_din_ports = val;
1315
1316         ret = of_property_read_u32(np, "qcom,dout-ports", &val);
1317         if (ret)
1318                 return ret;
1319
1320         if (val > ctrl->num_dout_ports)
1321                 return -EINVAL;
1322
1323         ctrl->num_dout_ports = val;
1324
1325         nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1326         if (nports > QCOM_SDW_MAX_PORTS)
1327                 return -EINVAL;
1328
1329         /* Valid port numbers are from 1-14, so mask out port 0 explicitly */
1330         set_bit(0, &ctrl->dout_port_mask);
1331         set_bit(0, &ctrl->din_port_mask);
1332
1333         ret = of_property_read_u8_array(np, "qcom,ports-offset1",
1334                                         off1, nports);
1335         if (ret)
1336                 return ret;
1337
1338         ret = of_property_read_u8_array(np, "qcom,ports-offset2",
1339                                         off2, nports);
1340         if (ret)
1341                 return ret;
1342
1343         ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
1344                                         (u8 *)si, nports);
1345         if (ret) {
1346                 ret = of_property_read_u16_array(np, "qcom,ports-sinterval",
1347                                                  si, nports);
1348                 if (ret)
1349                         return ret;
1350                 si_16 = true;
1351         }
1352
1353         ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
1354                                         bp_mode, nports);
1355         if (ret) {
1356                 if (ctrl->version <= SWRM_VERSION_1_3_0)
1357                         memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1358                 else
1359                         return ret;
1360         }
1361
1362         memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1363         of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports);
1364
1365         memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1366         of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports);
1367
1368         memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1369         of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports);
1370
1371         memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1372         of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports);
1373
1374         memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1375         of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports);
1376
1377         for (i = 0; i < nports; i++) {
1378                 /* Valid port number range is from 1-14 */
1379                 if (si_16)
1380                         ctrl->pconfig[i + 1].si = si[i];
1381                 else
1382                         ctrl->pconfig[i + 1].si = ((u8 *)si)[i];
1383                 ctrl->pconfig[i + 1].off1 = off1[i];
1384                 ctrl->pconfig[i + 1].off2 = off2[i];
1385                 ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
1386                 ctrl->pconfig[i + 1].hstart = hstart[i];
1387                 ctrl->pconfig[i + 1].hstop = hstop[i];
1388                 ctrl->pconfig[i + 1].word_length = word_length[i];
1389                 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
1390                 ctrl->pconfig[i + 1].lane_control = lane_control[i];
1391         }
1392
1393         return 0;
1394 }
1395
1396 #ifdef CONFIG_DEBUG_FS
1397 static int swrm_reg_show(struct seq_file *s_file, void *data)
1398 {
1399         struct qcom_swrm_ctrl *ctrl = s_file->private;
1400         int reg, reg_val, ret;
1401
1402         ret = pm_runtime_resume_and_get(ctrl->dev);
1403         if (ret < 0 && ret != -EACCES) {
1404                 dev_err_ratelimited(ctrl->dev,
1405                                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
1406                                     __func__, ret);
1407                 return ret;
1408         }
1409
1410         for (reg = 0; reg <= ctrl->max_reg; reg += 4) {
1411                 ctrl->reg_read(ctrl, reg, &reg_val);
1412                 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
1413         }
1414         pm_runtime_mark_last_busy(ctrl->dev);
1415         pm_runtime_put_autosuspend(ctrl->dev);
1416
1417
1418         return 0;
1419 }
1420 DEFINE_SHOW_ATTRIBUTE(swrm_reg);
1421 #endif
1422
1423 static int qcom_swrm_probe(struct platform_device *pdev)
1424 {
1425         struct device *dev = &pdev->dev;
1426         struct sdw_master_prop *prop;
1427         struct sdw_bus_params *params;
1428         struct qcom_swrm_ctrl *ctrl;
1429         const struct qcom_swrm_data *data;
1430         int ret;
1431         u32 val;
1432
1433         ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1434         if (!ctrl)
1435                 return -ENOMEM;
1436
1437         data = of_device_get_match_data(dev);
1438         ctrl->max_reg = data->max_reg;
1439         ctrl->reg_layout = data->reg_layout;
1440         ctrl->rows_index = sdw_find_row_index(data->default_rows);
1441         ctrl->cols_index = sdw_find_col_index(data->default_cols);
1442 #if IS_REACHABLE(CONFIG_SLIMBUS)
1443         if (dev->parent->bus == &slimbus_bus) {
1444 #else
1445         if (false) {
1446 #endif
1447                 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1448                 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1449                 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1450                 if (!ctrl->regmap)
1451                         return -EINVAL;
1452         } else {
1453                 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1454                 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1455                 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1456                 if (IS_ERR(ctrl->mmio))
1457                         return PTR_ERR(ctrl->mmio);
1458         }
1459
1460         if (data->sw_clk_gate_required) {
1461                 ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr");
1462                 if (IS_ERR(ctrl->audio_cgcr)) {
1463                         dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n");
1464                         ret = PTR_ERR(ctrl->audio_cgcr);
1465                         goto err_init;
1466                 }
1467         }
1468
1469         ctrl->irq = of_irq_get(dev->of_node, 0);
1470         if (ctrl->irq < 0) {
1471                 ret = ctrl->irq;
1472                 goto err_init;
1473         }
1474
1475         ctrl->hclk = devm_clk_get(dev, "iface");
1476         if (IS_ERR(ctrl->hclk)) {
1477                 ret = PTR_ERR(ctrl->hclk);
1478                 goto err_init;
1479         }
1480
1481         clk_prepare_enable(ctrl->hclk);
1482
1483         ctrl->dev = dev;
1484         dev_set_drvdata(&pdev->dev, ctrl);
1485         mutex_init(&ctrl->port_lock);
1486         init_completion(&ctrl->broadcast);
1487         init_completion(&ctrl->enumeration);
1488
1489         ctrl->bus.ops = &qcom_swrm_ops;
1490         ctrl->bus.port_ops = &qcom_swrm_port_ops;
1491         ctrl->bus.compute_params = &qcom_swrm_compute_params;
1492         ctrl->bus.clk_stop_timeout = 300;
1493
1494         ret = qcom_swrm_get_port_config(ctrl);
1495         if (ret)
1496                 goto err_clk;
1497
1498         params = &ctrl->bus.params;
1499         params->max_dr_freq = DEFAULT_CLK_FREQ;
1500         params->curr_dr_freq = DEFAULT_CLK_FREQ;
1501         params->col = data->default_cols;
1502         params->row = data->default_rows;
1503         ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1504         params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1505         params->next_bank = !params->curr_bank;
1506
1507         prop = &ctrl->bus.prop;
1508         prop->max_clk_freq = DEFAULT_CLK_FREQ;
1509         prop->num_clk_gears = 0;
1510         prop->num_clk_freq = MAX_FREQ_NUM;
1511         prop->clk_freq = &qcom_swrm_freq_tbl[0];
1512         prop->default_col = data->default_cols;
1513         prop->default_row = data->default_rows;
1514
1515         ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1516
1517         ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1518                                         qcom_swrm_irq_handler,
1519                                         IRQF_TRIGGER_RISING |
1520                                         IRQF_ONESHOT,
1521                                         "soundwire", ctrl);
1522         if (ret) {
1523                 dev_err(dev, "Failed to request soundwire irq\n");
1524                 goto err_clk;
1525         }
1526
1527         ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1528         if (ctrl->wake_irq > 0) {
1529                 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1530                                                 qcom_swrm_wake_irq_handler,
1531                                                 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1532                                                 "swr_wake_irq", ctrl);
1533                 if (ret) {
1534                         dev_err(dev, "Failed to request soundwire wake irq\n");
1535                         goto err_init;
1536                 }
1537         }
1538
1539         ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1540         if (ret) {
1541                 dev_err(dev, "Failed to register Soundwire controller (%d)\n",
1542                         ret);
1543                 goto err_clk;
1544         }
1545
1546         qcom_swrm_init(ctrl);
1547         wait_for_completion_timeout(&ctrl->enumeration,
1548                                     msecs_to_jiffies(TIMEOUT_MS));
1549         ret = qcom_swrm_register_dais(ctrl);
1550         if (ret)
1551                 goto err_master_add;
1552
1553         dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
1554                  (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1555                  ctrl->version & 0xffff);
1556
1557         pm_runtime_set_autosuspend_delay(dev, 3000);
1558         pm_runtime_use_autosuspend(dev);
1559         pm_runtime_mark_last_busy(dev);
1560         pm_runtime_set_active(dev);
1561         pm_runtime_enable(dev);
1562
1563         /* Clk stop is not supported on WSA Soundwire masters */
1564         if (ctrl->version <= SWRM_VERSION_1_3_0) {
1565                 ctrl->clock_stop_not_supported = true;
1566         } else {
1567                 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1568                 if (val == MASTER_ID_WSA)
1569                         ctrl->clock_stop_not_supported = true;
1570         }
1571
1572 #ifdef CONFIG_DEBUG_FS
1573         ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1574         debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1575                             &swrm_reg_fops);
1576 #endif
1577
1578         return 0;
1579
1580 err_master_add:
1581         sdw_bus_master_delete(&ctrl->bus);
1582 err_clk:
1583         clk_disable_unprepare(ctrl->hclk);
1584 err_init:
1585         return ret;
1586 }
1587
1588 static int qcom_swrm_remove(struct platform_device *pdev)
1589 {
1590         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1591
1592         sdw_bus_master_delete(&ctrl->bus);
1593         clk_disable_unprepare(ctrl->hclk);
1594
1595         return 0;
1596 }
1597
1598 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl)
1599 {
1600         int retry = SWRM_LINK_STATUS_RETRY_CNT;
1601         int comp_sts;
1602
1603         do {
1604                 ctrl->reg_read(ctrl, SWRM_COMP_STATUS, &comp_sts);
1605
1606                 if (comp_sts & SWRM_FRM_GEN_ENABLED)
1607                         return true;
1608
1609                 usleep_range(500, 510);
1610         } while (retry--);
1611
1612         dev_err(ctrl->dev, "%s: link status not %s\n", __func__,
1613                 comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
1614
1615         return false;
1616 }
1617
1618 static int __maybe_unused swrm_runtime_resume(struct device *dev)
1619 {
1620         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1621         int ret;
1622
1623         if (ctrl->wake_irq > 0) {
1624                 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1625                         disable_irq_nosync(ctrl->wake_irq);
1626         }
1627
1628         clk_prepare_enable(ctrl->hclk);
1629
1630         if (ctrl->clock_stop_not_supported) {
1631                 reinit_completion(&ctrl->enumeration);
1632                 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1633                 usleep_range(100, 105);
1634
1635                 qcom_swrm_init(ctrl);
1636
1637                 usleep_range(100, 105);
1638                 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1639                         dev_err(ctrl->dev, "link failed to connect\n");
1640
1641                 /* wait for hw enumeration to complete */
1642                 wait_for_completion_timeout(&ctrl->enumeration,
1643                                             msecs_to_jiffies(TIMEOUT_MS));
1644                 qcom_swrm_get_device_status(ctrl);
1645                 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1646         } else {
1647                 reset_control_reset(ctrl->audio_cgcr);
1648
1649                 if (ctrl->version == SWRM_VERSION_1_7_0) {
1650                         ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1651                         ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1652                                         SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
1653                 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
1654                         ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1655                         ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
1656                                         SWRM_V2_0_CLK_CTRL_CLK_START);
1657                 } else {
1658                         ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1659                 }
1660                 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1661                         SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
1662
1663                 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1664                 if (ctrl->version < SWRM_VERSION_2_0_0)
1665                         ctrl->reg_write(ctrl,
1666                                         ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1667                                         ctrl->intr_mask);
1668                 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1669                                 ctrl->intr_mask);
1670
1671                 usleep_range(100, 105);
1672                 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1673                         dev_err(ctrl->dev, "link failed to connect\n");
1674
1675                 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1676                 if (ret < 0)
1677                         dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1678         }
1679
1680         return 0;
1681 }
1682
1683 static int __maybe_unused swrm_runtime_suspend(struct device *dev)
1684 {
1685         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1686         int ret;
1687
1688         if (!ctrl->clock_stop_not_supported) {
1689                 /* Mask bus clash interrupt */
1690                 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1691                 if (ctrl->version < SWRM_VERSION_2_0_0)
1692                         ctrl->reg_write(ctrl,
1693                                         ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1694                                         ctrl->intr_mask);
1695                 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1696                                 ctrl->intr_mask);
1697                 /* Prepare slaves for clock stop */
1698                 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1699                 if (ret < 0 && ret != -ENODATA) {
1700                         dev_err(dev, "prepare clock stop failed %d", ret);
1701                         return ret;
1702                 }
1703
1704                 ret = sdw_bus_clk_stop(&ctrl->bus);
1705                 if (ret < 0 && ret != -ENODATA) {
1706                         dev_err(dev, "bus clock stop failed %d", ret);
1707                         return ret;
1708                 }
1709         }
1710
1711         clk_disable_unprepare(ctrl->hclk);
1712
1713         usleep_range(300, 305);
1714
1715         if (ctrl->wake_irq > 0) {
1716                 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1717                         enable_irq(ctrl->wake_irq);
1718         }
1719
1720         return 0;
1721 }
1722
1723 static const struct dev_pm_ops swrm_dev_pm_ops = {
1724         SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL)
1725 };
1726
1727 static const struct of_device_id qcom_swrm_of_match[] = {
1728         { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1729         { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1730         { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
1731         { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data },
1732         { .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data },
1733         {/* sentinel */},
1734 };
1735
1736 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
1737
1738 static struct platform_driver qcom_swrm_driver = {
1739         .probe  = &qcom_swrm_probe,
1740         .remove = &qcom_swrm_remove,
1741         .driver = {
1742                 .name   = "qcom-soundwire",
1743                 .of_match_table = qcom_swrm_of_match,
1744                 .pm = &swrm_dev_pm_ops,
1745         }
1746 };
1747 module_platform_driver(qcom_swrm_driver);
1748
1749 MODULE_DESCRIPTION("Qualcomm soundwire driver");
1750 MODULE_LICENSE("GPL v2");