drivers/soundwire/qcom.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2019, Linaro Limited
   3
   4 #include <linux/clk.h>
   5 #include <linux/completion.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/io.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/debugfs.h>
  11 #include <linux/of.h>
  12 #include <linux/of_irq.h>
  13 #include <linux/of_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regmap.h>
  16 #include <linux/reset.h>
  17 #include <linux/slab.h>
  18 #include <linux/pm_wakeirq.h>
  19 #include <linux/slimbus.h>
  20 #include <linux/soundwire/sdw.h>
  21 #include <linux/soundwire/sdw_registers.h>
  22 #include <sound/pcm_params.h>
  23 #include <sound/soc.h>
  24 #include "bus.h"
  25
  26 #define SWRM_COMP_SW_RESET                                      0x008
  27 #define SWRM_COMP_STATUS                                        0x014
  28 #define SWRM_LINK_MANAGER_EE                                    0x018
  29 #define SWRM_EE_CPU                                             1
  30 #define SWRM_FRM_GEN_ENABLED                                    BIT(0)
  31 #define SWRM_VERSION_1_3_0                                      0x01030000
  32 #define SWRM_VERSION_1_5_1                                      0x01050001
  33 #define SWRM_VERSION_1_7_0                                      0x01070000
  34 #define SWRM_VERSION_2_0_0                                      0x02000000
  35 #define SWRM_COMP_HW_VERSION                                    0x00
  36 #define SWRM_COMP_CFG_ADDR                                      0x04
  37 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK                    BIT(1)
  38 #define SWRM_COMP_CFG_ENABLE_MSK                                BIT(0)
  39 #define SWRM_COMP_PARAMS                                        0x100
  40 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH                          GENMASK(14, 10)
  41 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH                          GENMASK(19, 15)
  42 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK                        GENMASK(4, 0)
  43 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK                         GENMASK(9, 5)
  44 #define SWRM_COMP_MASTER_ID                                     0x104
  45 #define SWRM_V1_3_INTERRUPT_STATUS                              0x200
  46 #define SWRM_V2_0_INTERRUPT_STATUS                              0x5000
  47 #define SWRM_INTERRUPT_STATUS_RMSK                              GENMASK(16, 0)
  48 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ                    BIT(0)
  49 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED                BIT(1)
  50 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS          BIT(2)
  51 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET                  BIT(3)
  52 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  BIT(4)
  53 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 BIT(5)
  54 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW              BIT(6)
  55 #define SWRM_INTERRUPT_STATUS_CMD_ERROR                         BIT(7)
  56 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION               BIT(8)
  57 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH         BIT(9)
  58 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           BIT(10)
  59 #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED                  BIT(11)
  60 #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL           BIT(12)
  61 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2             BIT(13)
  62 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2              BIT(14)
  63 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP               BIT(16)
  64 #define SWRM_INTERRUPT_MAX                                      17
  65 #define SWRM_V1_3_INTERRUPT_MASK_ADDR                           0x204
  66 #define SWRM_V1_3_INTERRUPT_CLEAR                               0x208
  67 #define SWRM_V2_0_INTERRUPT_CLEAR                               0x5008
  68 #define SWRM_V1_3_INTERRUPT_CPU_EN                              0x210
  69 #define SWRM_V2_0_INTERRUPT_CPU_EN                              0x5004
  70 #define SWRM_V1_3_CMD_FIFO_WR_CMD                               0x300
  71 #define SWRM_V2_0_CMD_FIFO_WR_CMD                               0x5020
  72 #define SWRM_V1_3_CMD_FIFO_RD_CMD                               0x304
  73 #define SWRM_V2_0_CMD_FIFO_RD_CMD                               0x5024
  74 #define SWRM_CMD_FIFO_CMD                                       0x308
  75 #define SWRM_CMD_FIFO_FLUSH                                     0x1
  76 #define SWRM_V1_3_CMD_FIFO_STATUS                               0x30C
  77 #define SWRM_V2_0_CMD_FIFO_STATUS                               0x5050
  78 #define SWRM_RD_CMD_FIFO_CNT_MASK                               GENMASK(20, 16)
  79 #define SWRM_WR_CMD_FIFO_CNT_MASK                               GENMASK(12, 8)
  80 #define SWRM_CMD_FIFO_CFG_ADDR                                  0x314
  81 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE                        BIT(31)
  82 #define SWRM_RD_WR_CMD_RETRIES                                  0x7
  83 #define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR                         0x318
  84 #define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR                         0x5040
  85 #define SWRM_RD_FIFO_CMD_ID_MASK                                GENMASK(11, 8)
  86 #define SWRM_ENUMERATOR_CFG_ADDR                                0x500
  87 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m)               (0x530 + 0x8 * (m))
  88 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m)               (0x534 + 0x8 * (m))
  89 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m)                (0x101C + 0x40 * (m))
  90 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK                  GENMASK(2, 0)
  91 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK                  GENMASK(7, 3)
  92 #define SWRM_MCP_BUS_CTRL                                       0x1044
  93 #define SWRM_MCP_BUS_CLK_START                                  BIT(1)
  94 #define SWRM_MCP_CFG_ADDR                                       0x1048
  95 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK               GENMASK(21, 17)
  96 #define SWRM_DEF_CMD_NO_PINGS                                   0x1f
  97 #define SWRM_MCP_STATUS                                         0x104C
  98 #define SWRM_MCP_STATUS_BANK_NUM_MASK                           BIT(0)
  99 #define SWRM_MCP_SLV_STATUS                                     0x1090
 100 #define SWRM_MCP_SLV_STATUS_MASK                                GENMASK(1, 0)
 101 #define SWRM_MCP_SLV_STATUS_SZ                                  2
 102 #define SWRM_DP_PORT_CTRL_BANK(n, m)    (0x1124 + 0x100 * (n - 1) + 0x40 * m)
 103 #define SWRM_DP_PORT_CTRL_2_BANK(n, m)  (0x1128 + 0x100 * (n - 1) + 0x40 * m)
 104 #define SWRM_DP_BLOCK_CTRL_1(n)         (0x112C + 0x100 * (n - 1))
 105 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m)  (0x1130 + 0x100 * (n - 1) + 0x40 * m)
 106 #define SWRM_DP_PORT_HCTRL_BANK(n, m)   (0x1134 + 0x100 * (n - 1) + 0x40 * m)
 107 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m)  (0x1138 + 0x100 * (n - 1) + 0x40 * m)
 108 #define SWRM_DP_SAMPLECTRL2_BANK(n, m)  (0x113C + 0x100 * (n - 1) + 0x40 * m)
 109 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n)   (0x1054 + 0x100 * (n - 1))
 110 #define SWR_V1_3_MSTR_MAX_REG_ADDR                              0x1740
 111 #define SWR_V2_0_MSTR_MAX_REG_ADDR                              0x50ac
 112
 113 #define SWRM_V2_0_CLK_CTRL                                      0x5060
 114 #define SWRM_V2_0_CLK_CTRL_CLK_START                            BIT(0)
 115 #define SWRM_V2_0_LINK_STATUS                                   0x5064
 116
 117 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT                          0x18
 118 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT                          0x10
 119 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT                          0x08
 120 #define SWRM_AHB_BRIDGE_WR_DATA_0                               0xc85
 121 #define SWRM_AHB_BRIDGE_WR_ADDR_0                               0xc89
 122 #define SWRM_AHB_BRIDGE_RD_ADDR_0                               0xc8d
 123 #define SWRM_AHB_BRIDGE_RD_DATA_0                               0xc91
 124
 125 #define SWRM_REG_VAL_PACK(data, dev, id, reg)   \
 126                         ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
 127
 128 #define MAX_FREQ_NUM                                            1
 129 #define TIMEOUT_MS                                              100
 130 #define QCOM_SWRM_MAX_RD_LEN                                    0x1
 131 #define QCOM_SDW_MAX_PORTS                                      14
 132 #define DEFAULT_CLK_FREQ                                        9600000
 133 #define SWRM_MAX_DAIS                                           0xF
 134 #define SWR_INVALID_PARAM                                       0xFF
 135 #define SWR_HSTOP_MAX_VAL                                       0xF
 136 #define SWR_HSTART_MIN_VAL                                      0x0
 137 #define SWR_BROADCAST_CMD_ID                                    0x0F
 138 #define SWR_MAX_CMD_ID                                          14
 139 #define MAX_FIFO_RD_RETRY                                       3
 140 #define SWR_OVERFLOW_RETRY_COUNT                                30
 141 #define SWRM_LINK_STATUS_RETRY_CNT                              100
 142
 143 enum {
 144         MASTER_ID_WSA = 1,
 145         MASTER_ID_RX,
 146         MASTER_ID_TX
 147 };
 148
 149 struct qcom_swrm_port_config {
 150         u16 si;
 151         u8 off1;
 152         u8 off2;
 153         u8 bp_mode;
 154         u8 hstart;
 155         u8 hstop;
 156         u8 word_length;
 157         u8 blk_group_count;
 158         u8 lane_control;
 159 };
 160
 161 /*
 162  * Internal IDs for different register layouts.  Only few registers differ per
 163  * each variant, so the list of IDs below does not include all of registers.
 164  */
 165 enum {
 166         SWRM_REG_FRAME_GEN_ENABLED,
 167         SWRM_REG_INTERRUPT_STATUS,
 168         SWRM_REG_INTERRUPT_MASK_ADDR,
 169         SWRM_REG_INTERRUPT_CLEAR,
 170         SWRM_REG_INTERRUPT_CPU_EN,
 171         SWRM_REG_CMD_FIFO_WR_CMD,
 172         SWRM_REG_CMD_FIFO_RD_CMD,
 173         SWRM_REG_CMD_FIFO_STATUS,
 174         SWRM_REG_CMD_FIFO_RD_FIFO_ADDR,
 175 };
 176
 177 struct qcom_swrm_ctrl {
 178         struct sdw_bus bus;
 179         struct device *dev;
 180         struct regmap *regmap;
 181         u32 max_reg;
 182         const unsigned int *reg_layout;
 183         void __iomem *mmio;
 184         struct reset_control *audio_cgcr;
 185 #ifdef CONFIG_DEBUG_FS
 186         struct dentry *debugfs;
 187 #endif
 188         struct completion broadcast;
 189         struct completion enumeration;
 190         /* Port alloc/free lock */
 191         struct mutex port_lock;
 192         struct clk *hclk;
 193         int irq;
 194         unsigned int version;
 195         int wake_irq;
 196         int num_din_ports;
 197         int num_dout_ports;
 198         int cols_index;
 199         int rows_index;
 200         unsigned long dout_port_mask;
 201         unsigned long din_port_mask;
 202         u32 intr_mask;
 203         u8 rcmd_id;
 204         u8 wcmd_id;
 205         struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS];
 206         struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
 207         enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
 208         int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
 209         int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
 210         u32 slave_status;
 211         u32 wr_fifo_depth;
 212         u32 rd_fifo_depth;
 213         bool clock_stop_not_supported;
 214 };
 215
 216 struct qcom_swrm_data {
 217         u32 default_cols;
 218         u32 default_rows;
 219         bool sw_clk_gate_required;
 220         u32 max_reg;
 221         const unsigned int *reg_layout;
 222 };
 223
 224 static const unsigned int swrm_v1_3_reg_layout[] = {
 225         [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_COMP_STATUS,
 226         [SWRM_REG_INTERRUPT_STATUS] = SWRM_V1_3_INTERRUPT_STATUS,
 227         [SWRM_REG_INTERRUPT_MASK_ADDR] = SWRM_V1_3_INTERRUPT_MASK_ADDR,
 228         [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V1_3_INTERRUPT_CLEAR,
 229         [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V1_3_INTERRUPT_CPU_EN,
 230         [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V1_3_CMD_FIFO_WR_CMD,
 231         [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD,
 232         [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V1_3_CMD_FIFO_STATUS,
 233         [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR,
 234 };
 235
 236 static const struct qcom_swrm_data swrm_v1_3_data = {
 237         .default_rows = 48,
 238         .default_cols = 16,
 239         .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
 240         .reg_layout = swrm_v1_3_reg_layout,
 241 };
 242
 243 static const struct qcom_swrm_data swrm_v1_5_data = {
 244         .default_rows = 50,
 245         .default_cols = 16,
 246         .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
 247         .reg_layout = swrm_v1_3_reg_layout,
 248 };
 249
 250 static const struct qcom_swrm_data swrm_v1_6_data = {
 251         .default_rows = 50,
 252         .default_cols = 16,
 253         .sw_clk_gate_required = true,
 254         .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
 255         .reg_layout = swrm_v1_3_reg_layout,
 256 };
 257
 258 static const unsigned int swrm_v2_0_reg_layout[] = {
 259         [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS,
 260         [SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS,
 261         [SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */
 262         [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR,
 263         [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN,
 264         [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD,
 265         [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD,
 266         [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS,
 267         [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR,
 268 };
 269
 270 static const struct qcom_swrm_data swrm_v2_0_data = {
 271         .default_rows = 50,
 272         .default_cols = 16,
 273         .sw_clk_gate_required = true,
 274         .max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR,
 275         .reg_layout = swrm_v2_0_reg_layout,
 276 };
 277
 278 #define to_qcom_sdw(b)  container_of(b, struct qcom_swrm_ctrl, bus)
 279
 280 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 281                                   u32 *val)
 282 {
 283         struct regmap *wcd_regmap = ctrl->regmap;
 284         int ret;
 285
 286         /* pg register + offset */
 287         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
 288                           (u8 *)&reg, 4);
 289         if (ret < 0)
 290                 return SDW_CMD_FAIL;
 291
 292         ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
 293                                val, 4);
 294         if (ret < 0)
 295                 return SDW_CMD_FAIL;
 296
 297         return SDW_CMD_OK;
 298 }
 299
 300 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
 301                                    int reg, int val)
 302 {
 303         struct regmap *wcd_regmap = ctrl->regmap;
 304         int ret;
 305         /* pg register + offset */
 306         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
 307                           (u8 *)&val, 4);
 308         if (ret)
 309                 return SDW_CMD_FAIL;
 310
 311         /* write address register */
 312         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
 313                           (u8 *)&reg, 4);
 314         if (ret)
 315                 return SDW_CMD_FAIL;
 316
 317         return SDW_CMD_OK;
 318 }
 319
 320 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 321                                   u32 *val)
 322 {
 323         *val = readl(ctrl->mmio + reg);
 324         return SDW_CMD_OK;
 325 }
 326
 327 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
 328                                    int val)
 329 {
 330         writel(val, ctrl->mmio + reg);
 331         return SDW_CMD_OK;
 332 }
 333
 334 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
 335                                    u8 dev_addr, u16 reg_addr)
 336 {
 337         u32 val;
 338         u8 id = *cmd_id;
 339
 340         if (id != SWR_BROADCAST_CMD_ID) {
 341                 if (id < SWR_MAX_CMD_ID)
 342                         id += 1;
 343                 else
 344                         id = 0;
 345                 *cmd_id = id;
 346         }
 347         val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
 348
 349         return val;
 350 }
 351
 352 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl)
 353 {
 354         u32 fifo_outstanding_data, value;
 355         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 356
 357         do {
 358                 /* Check for fifo underflow during read */
 359                 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 360                                &value);
 361                 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
 362
 363                 /* Check if read data is available in read fifo */
 364                 if (fifo_outstanding_data > 0)
 365                         return 0;
 366
 367                 usleep_range(500, 510);
 368         } while (fifo_retry_count--);
 369
 370         if (fifo_outstanding_data == 0) {
 371                 dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__);
 372                 return -EIO;
 373         }
 374
 375         return 0;
 376 }
 377
 378 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl)
 379 {
 380         u32 fifo_outstanding_cmds, value;
 381         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 382
 383         do {
 384                 /* Check for fifo overflow during write */
 385                 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 386                                &value);
 387                 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
 388
 389                 /* Check for space in write fifo before writing */
 390                 if (fifo_outstanding_cmds < ctrl->wr_fifo_depth)
 391                         return 0;
 392
 393                 usleep_range(500, 510);
 394         } while (fifo_retry_count--);
 395
 396         if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) {
 397                 dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__);
 398                 return -EIO;
 399         }
 400
 401         return 0;
 402 }
 403
 404 static bool swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl *ctrl)
 405 {
 406         u32 fifo_outstanding_cmds, value;
 407         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 408
 409         /* Check for fifo overflow during write */
 410         ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
 411         fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
 412
 413         if (fifo_outstanding_cmds) {
 414                 while (fifo_retry_count) {
 415                         usleep_range(500, 510);
 416                         ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
 417                         fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
 418                         fifo_retry_count--;
 419                         if (fifo_outstanding_cmds == 0)
 420                                 return true;
 421                 }
 422         } else {
 423                 return true;
 424         }
 425
 426
 427         return false;
 428 }
 429
 430 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,
 431                                      u8 dev_addr, u16 reg_addr)
 432 {
 433
 434         u32 val;
 435         int ret = 0;
 436         u8 cmd_id = 0x0;
 437
 438         if (dev_addr == SDW_BROADCAST_DEV_NUM) {
 439                 cmd_id = SWR_BROADCAST_CMD_ID;
 440                 val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
 441                                               dev_addr, reg_addr);
 442         } else {
 443                 val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data,
 444                                               dev_addr, reg_addr);
 445         }
 446
 447         if (swrm_wait_for_wr_fifo_avail(ctrl))
 448                 return SDW_CMD_FAIL_OTHER;
 449
 450         if (cmd_id == SWR_BROADCAST_CMD_ID)
 451                 reinit_completion(&ctrl->broadcast);
 452
 453         /* Its assumed that write is okay as we do not get any status back */
 454         ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val);
 455
 456         if (ctrl->version <= SWRM_VERSION_1_3_0)
 457                 usleep_range(150, 155);
 458
 459         if (cmd_id == SWR_BROADCAST_CMD_ID) {
 460                 swrm_wait_for_wr_fifo_done(ctrl);
 461                 /*
 462                  * sleep for 10ms for MSM soundwire variant to allow broadcast
 463                  * command to complete.
 464                  */
 465                 ret = wait_for_completion_timeout(&ctrl->broadcast,
 466                                                   msecs_to_jiffies(TIMEOUT_MS));
 467                 if (!ret)
 468                         ret = SDW_CMD_IGNORED;
 469                 else
 470                         ret = SDW_CMD_OK;
 471
 472         } else {
 473                 ret = SDW_CMD_OK;
 474         }
 475         return ret;
 476 }
 477
 478 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,
 479                                      u8 dev_addr, u16 reg_addr,
 480                                      u32 len, u8 *rval)
 481 {
 482         u32 cmd_data, cmd_id, val, retry_attempt = 0;
 483
 484         val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr);
 485
 486         /*
 487          * Check for outstanding cmd wrt. write fifo depth to avoid
 488          * overflow as read will also increase write fifo cnt.
 489          */
 490         swrm_wait_for_wr_fifo_avail(ctrl);
 491
 492         /* wait for FIFO RD to complete to avoid overflow */
 493         usleep_range(100, 105);
 494         ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val);
 495         /* wait for FIFO RD CMD complete to avoid overflow */
 496         usleep_range(250, 255);
 497
 498         if (swrm_wait_for_rd_fifo_avail(ctrl))
 499                 return SDW_CMD_FAIL_OTHER;
 500
 501         do {
 502                 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR],
 503                                &cmd_data);
 504                 rval[0] = cmd_data & 0xFF;
 505                 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
 506
 507                 if (cmd_id != ctrl->rcmd_id) {
 508                         if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
 509                                 /* wait 500 us before retry on fifo read failure */
 510                                 usleep_range(500, 505);
 511                                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD,
 512                                                 SWRM_CMD_FIFO_FLUSH);
 513                                 ctrl->reg_write(ctrl,
 514                                                 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD],
 515                                                 val);
 516                         }
 517                         retry_attempt++;
 518                 } else {
 519                         return SDW_CMD_OK;
 520                 }
 521
 522         } while (retry_attempt < MAX_FIFO_RD_RETRY);
 523
 524         dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
 525                 dev_num: 0x%x, cmd_data: 0x%x\n",
 526                 reg_addr, ctrl->rcmd_id, dev_addr, cmd_data);
 527
 528         return SDW_CMD_IGNORED;
 529 }
 530
 531 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
 532 {
 533         u32 val, status;
 534         int dev_num;
 535
 536         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 537
 538         for (dev_num = 1; dev_num <= SDW_MAX_DEVICES; dev_num++) {
 539                 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
 540
 541                 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
 542                         ctrl->status[dev_num] = status;
 543                         return dev_num;
 544                 }
 545         }
 546
 547         return -EINVAL;
 548 }
 549
 550 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
 551 {
 552         u32 val;
 553         int i;
 554
 555         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 556         ctrl->slave_status = val;
 557
 558         for (i = 1; i <= SDW_MAX_DEVICES; i++) {
 559                 u32 s;
 560
 561                 s = (val >> (i * 2));
 562                 s &= SWRM_MCP_SLV_STATUS_MASK;
 563                 ctrl->status[i] = s;
 564         }
 565 }
 566
 567 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
 568                                         struct sdw_slave *slave, int devnum)
 569 {
 570         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 571         u32 status;
 572
 573         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
 574         status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
 575         status &= SWRM_MCP_SLV_STATUS_MASK;
 576
 577         if (status == SDW_SLAVE_ATTACHED) {
 578                 if (slave)
 579                         slave->dev_num = devnum;
 580                 mutex_lock(&bus->bus_lock);
 581                 set_bit(devnum, bus->assigned);
 582                 mutex_unlock(&bus->bus_lock);
 583         }
 584 }
 585
 586 static int qcom_swrm_enumerate(struct sdw_bus *bus)
 587 {
 588         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 589         struct sdw_slave *slave, *_s;
 590         struct sdw_slave_id id;
 591         u32 val1, val2;
 592         bool found;
 593         u64 addr;
 594         int i;
 595         char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
 596
 597         for (i = 1; i <= SDW_MAX_DEVICES; i++) {
 598                 /* do not continue if the status is Not Present  */
 599                 if (!ctrl->status[i])
 600                         continue;
 601
 602                 /*SCP_Devid5 - Devid 4*/
 603                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
 604
 605                 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
 606                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
 607
 608                 if (!val1 && !val2)
 609                         break;
 610
 611                 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
 612                         ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
 613                         ((u64)buf1[0] << 40);
 614
 615                 sdw_extract_slave_id(bus, addr, &id);
 616                 found = false;
 617                 /* Now compare with entries */
 618                 list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
 619                         if (sdw_compare_devid(slave, id) == 0) {
 620                                 qcom_swrm_set_slave_dev_num(bus, slave, i);
 621                                 found = true;
 622                                 break;
 623                         }
 624                 }
 625
 626                 if (!found) {
 627                         qcom_swrm_set_slave_dev_num(bus, NULL, i);
 628                         sdw_slave_add(bus, &id, NULL);
 629                 }
 630         }
 631
 632         complete(&ctrl->enumeration);
 633         return 0;
 634 }
 635
 636 static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id)
 637 {
 638         struct qcom_swrm_ctrl *ctrl = dev_id;
 639         int ret;
 640
 641         ret = pm_runtime_resume_and_get(ctrl->dev);
 642         if (ret < 0 && ret != -EACCES) {
 643                 dev_err_ratelimited(ctrl->dev,
 644                                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
 645                                     __func__, ret);
 646                 return ret;
 647         }
 648
 649         if (ctrl->wake_irq > 0) {
 650                 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
 651                         disable_irq_nosync(ctrl->wake_irq);
 652         }
 653
 654         pm_runtime_mark_last_busy(ctrl->dev);
 655         pm_runtime_put_autosuspend(ctrl->dev);
 656
 657         return IRQ_HANDLED;
 658 }
 659
 660 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
 661 {
 662         struct qcom_swrm_ctrl *ctrl = dev_id;
 663         u32 value, intr_sts, intr_sts_masked, slave_status;
 664         u32 i;
 665         int devnum;
 666         int ret = IRQ_HANDLED;
 667         clk_prepare_enable(ctrl->hclk);
 668
 669         ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
 670                        &intr_sts);
 671         intr_sts_masked = intr_sts & ctrl->intr_mask;
 672
 673         do {
 674                 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
 675                         value = intr_sts_masked & BIT(i);
 676                         if (!value)
 677                                 continue;
 678
 679                         switch (value) {
 680                         case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
 681                                 devnum = qcom_swrm_get_alert_slave_dev_num(ctrl);
 682                                 if (devnum < 0) {
 683                                         dev_err_ratelimited(ctrl->dev,
 684                                             "no slave alert found.spurious interrupt\n");
 685                                 } else {
 686                                         sdw_handle_slave_status(&ctrl->bus, ctrl->status);
 687                                 }
 688
 689                                 break;
 690                         case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
 691                         case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
 692                                 dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n");
 693                                 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status);
 694                                 if (ctrl->slave_status == slave_status) {
 695                                         dev_dbg(ctrl->dev, "Slave status not changed %x\n",
 696                                                 slave_status);
 697                                 } else {
 698                                         qcom_swrm_get_device_status(ctrl);
 699                                         qcom_swrm_enumerate(&ctrl->bus);
 700                                         sdw_handle_slave_status(&ctrl->bus, ctrl->status);
 701                                 }
 702                                 break;
 703                         case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
 704                                 dev_err_ratelimited(ctrl->dev,
 705                                                 "%s: SWR bus clsh detected\n",
 706                                                 __func__);
 707                                 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
 708                                 ctrl->reg_write(ctrl,
 709                                                 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
 710                                                 ctrl->intr_mask);
 711                                 break;
 712                         case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
 713                                 ctrl->reg_read(ctrl,
 714                                                ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 715                                                &value);
 716                                 dev_err_ratelimited(ctrl->dev,
 717                                         "%s: SWR read FIFO overflow fifo status 0x%x\n",
 718                                         __func__, value);
 719                                 break;
 720                         case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
 721                                 ctrl->reg_read(ctrl,
 722                                                ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 723                                                &value);
 724                                 dev_err_ratelimited(ctrl->dev,
 725                                         "%s: SWR read FIFO underflow fifo status 0x%x\n",
 726                                         __func__, value);
 727                                 break;
 728                         case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
 729                                 ctrl->reg_read(ctrl,
 730                                                ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 731                                                &value);
 732                                 dev_err(ctrl->dev,
 733                                         "%s: SWR write FIFO overflow fifo status %x\n",
 734                                         __func__, value);
 735                                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
 736                                 break;
 737                         case SWRM_INTERRUPT_STATUS_CMD_ERROR:
 738                                 ctrl->reg_read(ctrl,
 739                                                ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 740                                                &value);
 741                                 dev_err_ratelimited(ctrl->dev,
 742                                         "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
 743                                         __func__, value);
 744                                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
 745                                 break;
 746                         case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
 747                                 dev_err_ratelimited(ctrl->dev,
 748                                                 "%s: SWR Port collision detected\n",
 749                                                 __func__);
 750                                 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
 751                                 ctrl->reg_write(ctrl,
 752                                                 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
 753                                                 ctrl->intr_mask);
 754                                 break;
 755                         case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
 756                                 dev_err_ratelimited(ctrl->dev,
 757                                         "%s: SWR read enable valid mismatch\n",
 758                                         __func__);
 759                                 ctrl->intr_mask &=
 760                                         ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
 761                                 ctrl->reg_write(ctrl,
 762                                                 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
 763                                                 ctrl->intr_mask);
 764                                 break;
 765                         case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
 766                                 complete(&ctrl->broadcast);
 767                                 break;
 768                         case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
 769                                 break;
 770                         case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
 771                                 break;
 772                         case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
 773                                 break;
 774                         default:
 775                                 dev_err_ratelimited(ctrl->dev,
 776                                                 "%s: SWR unknown interrupt value: %d\n",
 777                                                 __func__, value);
 778                                 ret = IRQ_NONE;
 779                                 break;
 780                         }
 781                 }
 782                 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
 783                                 intr_sts);
 784                 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
 785                                &intr_sts);
 786                 intr_sts_masked = intr_sts & ctrl->intr_mask;
 787         } while (intr_sts_masked);
 788
 789         clk_disable_unprepare(ctrl->hclk);
 790         return ret;
 791 }
 792
 793 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
 794 {
 795         u32 val;
 796
 797         /* Clear Rows and Cols */
 798         val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
 799         val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
 800
 801         reset_control_reset(ctrl->audio_cgcr);
 802
 803         ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
 804
 805         /* Enable Auto enumeration */
 806         ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
 807
 808         ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
 809         /* Mask soundwire interrupts */
 810         if (ctrl->version < SWRM_VERSION_2_0_0)
 811                 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
 812                                 SWRM_INTERRUPT_STATUS_RMSK);
 813
 814         /* Configure No pings */
 815         ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
 816         u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
 817         ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
 818
 819         if (ctrl->version == SWRM_VERSION_1_7_0) {
 820                 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
 821                 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
 822                                 SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
 823         } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
 824                 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
 825                 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
 826                                 SWRM_V2_0_CLK_CTRL_CLK_START);
 827         } else {
 828                 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
 829         }
 830
 831         /* Configure number of retries of a read/write cmd */
 832         if (ctrl->version >= SWRM_VERSION_1_5_1) {
 833                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 834                                 SWRM_RD_WR_CMD_RETRIES |
 835                                 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
 836         } else {
 837                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 838                                 SWRM_RD_WR_CMD_RETRIES);
 839         }
 840
 841         /* Set IRQ to PULSE */
 842         ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
 843                         SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
 844                         SWRM_COMP_CFG_ENABLE_MSK);
 845
 846         /* enable CPU IRQs */
 847         if (ctrl->mmio) {
 848                 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
 849                                 SWRM_INTERRUPT_STATUS_RMSK);
 850         }
 851         ctrl->slave_status = 0;
 852         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
 853         ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
 854         ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
 855
 856         return 0;
 857 }
 858
 859 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
 860                                                     struct sdw_msg *msg)
 861 {
 862         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 863         int ret, i, len;
 864
 865         if (msg->flags == SDW_MSG_FLAG_READ) {
 866                 for (i = 0; i < msg->len;) {
 867                         if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
 868                                 len = msg->len - i;
 869                         else
 870                                 len = QCOM_SWRM_MAX_RD_LEN;
 871
 872                         ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
 873                                                         msg->addr + i, len,
 874                                                        &msg->buf[i]);
 875                         if (ret)
 876                                 return ret;
 877
 878                         i = i + len;
 879                 }
 880         } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
 881                 for (i = 0; i < msg->len; i++) {
 882                         ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
 883                                                         msg->dev_num,
 884                                                        msg->addr + i);
 885                         if (ret)
 886                                 return SDW_CMD_IGNORED;
 887                 }
 888         }
 889
 890         return SDW_CMD_OK;
 891 }
 892
 893 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
 894 {
 895         u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
 896         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 897         u32 val;
 898
 899         ctrl->reg_read(ctrl, reg, &val);
 900
 901         u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
 902         u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
 903
 904         return ctrl->reg_write(ctrl, reg, val);
 905 }
 906
 907 static int qcom_swrm_port_params(struct sdw_bus *bus,
 908                                  struct sdw_port_params *p_params,
 909                                  unsigned int bank)
 910 {
 911         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 912
 913         return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
 914                                p_params->bps - 1);
 915
 916 }
 917
 918 static int qcom_swrm_transport_params(struct sdw_bus *bus,
 919                                       struct sdw_transport_params *params,
 920                                       enum sdw_reg_bank bank)
 921 {
 922         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 923         struct qcom_swrm_port_config *pcfg;
 924         u32 value;
 925         int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
 926         int ret;
 927
 928         pcfg = &ctrl->pconfig[params->port_num];
 929
 930         value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
 931         value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
 932         value |= pcfg->si & 0xff;
 933
 934         ret = ctrl->reg_write(ctrl, reg, value);
 935         if (ret)
 936                 goto err;
 937
 938         if (pcfg->si > 0xff) {
 939                 value = (pcfg->si >> 8) & 0xff;
 940                 reg = SWRM_DP_SAMPLECTRL2_BANK(params->port_num, bank);
 941                 ret = ctrl->reg_write(ctrl, reg, value);
 942                 if (ret)
 943                         goto err;
 944         }
 945
 946         if (pcfg->lane_control != SWR_INVALID_PARAM) {
 947                 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
 948                 value = pcfg->lane_control;
 949                 ret = ctrl->reg_write(ctrl, reg, value);
 950                 if (ret)
 951                         goto err;
 952         }
 953
 954         if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
 955                 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
 956                 value = pcfg->blk_group_count;
 957                 ret = ctrl->reg_write(ctrl, reg, value);
 958                 if (ret)
 959                         goto err;
 960         }
 961
 962         if (pcfg->hstart != SWR_INVALID_PARAM
 963                         && pcfg->hstop != SWR_INVALID_PARAM) {
 964                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
 965                 value = (pcfg->hstop << 4) | pcfg->hstart;
 966                 ret = ctrl->reg_write(ctrl, reg, value);
 967         } else {
 968                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
 969                 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
 970                 ret = ctrl->reg_write(ctrl, reg, value);
 971         }
 972
 973         if (ret)
 974                 goto err;
 975
 976         if (pcfg->bp_mode != SWR_INVALID_PARAM) {
 977                 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
 978                 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
 979         }
 980
 981 err:
 982         return ret;
 983 }
 984
 985 static int qcom_swrm_port_enable(struct sdw_bus *bus,
 986                                  struct sdw_enable_ch *enable_ch,
 987                                  unsigned int bank)
 988 {
 989         u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
 990         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 991         u32 val;
 992
 993         ctrl->reg_read(ctrl, reg, &val);
 994
 995         if (enable_ch->enable)
 996                 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 997         else
 998                 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 999
1000         return ctrl->reg_write(ctrl, reg, val);
1001 }
1002
1003 static const struct sdw_master_port_ops qcom_swrm_port_ops = {
1004         .dpn_set_port_params = qcom_swrm_port_params,
1005         .dpn_set_port_transport_params = qcom_swrm_transport_params,
1006         .dpn_port_enable_ch = qcom_swrm_port_enable,
1007 };
1008
1009 static const struct sdw_master_ops qcom_swrm_ops = {
1010         .xfer_msg = qcom_swrm_xfer_msg,
1011         .pre_bank_switch = qcom_swrm_pre_bank_switch,
1012 };
1013
1014 static int qcom_swrm_compute_params(struct sdw_bus *bus)
1015 {
1016         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1017         struct sdw_master_runtime *m_rt;
1018         struct sdw_slave_runtime *s_rt;
1019         struct sdw_port_runtime *p_rt;
1020         struct qcom_swrm_port_config *pcfg;
1021         struct sdw_slave *slave;
1022         unsigned int m_port;
1023         int i = 1;
1024
1025         list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
1026                 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
1027                         pcfg = &ctrl->pconfig[p_rt->num];
1028                         p_rt->transport_params.port_num = p_rt->num;
1029                         if (pcfg->word_length != SWR_INVALID_PARAM) {
1030                                 sdw_fill_port_params(&p_rt->port_params,
1031                                              p_rt->num,  pcfg->word_length + 1,
1032                                              SDW_PORT_FLOW_MODE_ISOCH,
1033                                              SDW_PORT_DATA_MODE_NORMAL);
1034                         }
1035
1036                 }
1037
1038                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
1039                         slave = s_rt->slave;
1040                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
1041                                 m_port = slave->m_port_map[p_rt->num];
1042                                 /* port config starts at offset 0 so -1 from actual port number */
1043                                 if (m_port)
1044                                         pcfg = &ctrl->pconfig[m_port];
1045                                 else
1046                                         pcfg = &ctrl->pconfig[i];
1047                                 p_rt->transport_params.port_num = p_rt->num;
1048                                 p_rt->transport_params.sample_interval =
1049                                         pcfg->si + 1;
1050                                 p_rt->transport_params.offset1 = pcfg->off1;
1051                                 p_rt->transport_params.offset2 = pcfg->off2;
1052                                 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
1053                                 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
1054
1055                                 p_rt->transport_params.hstart = pcfg->hstart;
1056                                 p_rt->transport_params.hstop = pcfg->hstop;
1057                                 p_rt->transport_params.lane_ctrl = pcfg->lane_control;
1058                                 if (pcfg->word_length != SWR_INVALID_PARAM) {
1059                                         sdw_fill_port_params(&p_rt->port_params,
1060                                                      p_rt->num,
1061                                                      pcfg->word_length + 1,
1062                                                      SDW_PORT_FLOW_MODE_ISOCH,
1063                                                      SDW_PORT_DATA_MODE_NORMAL);
1064                                 }
1065                                 i++;
1066                         }
1067                 }
1068         }
1069
1070         return 0;
1071 }
1072
1073 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
1074         DEFAULT_CLK_FREQ,
1075 };
1076
1077 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
1078                                         struct sdw_stream_runtime *stream)
1079 {
1080         struct sdw_master_runtime *m_rt;
1081         struct sdw_port_runtime *p_rt;
1082         unsigned long *port_mask;
1083
1084         mutex_lock(&ctrl->port_lock);
1085
1086         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1087                 if (m_rt->direction == SDW_DATA_DIR_RX)
1088                         port_mask = &ctrl->dout_port_mask;
1089                 else
1090                         port_mask = &ctrl->din_port_mask;
1091
1092                 list_for_each_entry(p_rt, &m_rt->port_list, port_node)
1093                         clear_bit(p_rt->num, port_mask);
1094         }
1095
1096         mutex_unlock(&ctrl->port_lock);
1097 }
1098
1099 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
1100                                         struct sdw_stream_runtime *stream,
1101                                        struct snd_pcm_hw_params *params,
1102                                        int direction)
1103 {
1104         struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
1105         struct sdw_stream_config sconfig;
1106         struct sdw_master_runtime *m_rt;
1107         struct sdw_slave_runtime *s_rt;
1108         struct sdw_port_runtime *p_rt;
1109         struct sdw_slave *slave;
1110         unsigned long *port_mask;
1111         int i, maxport, pn, nports = 0, ret = 0;
1112         unsigned int m_port;
1113
1114         mutex_lock(&ctrl->port_lock);
1115         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1116                 if (m_rt->direction == SDW_DATA_DIR_RX) {
1117                         maxport = ctrl->num_dout_ports;
1118                         port_mask = &ctrl->dout_port_mask;
1119                 } else {
1120                         maxport = ctrl->num_din_ports;
1121                         port_mask = &ctrl->din_port_mask;
1122                 }
1123
1124                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
1125                         slave = s_rt->slave;
1126                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
1127                                 m_port = slave->m_port_map[p_rt->num];
1128                                 /* Port numbers start from 1 - 14*/
1129                                 if (m_port)
1130                                         pn = m_port;
1131                                 else
1132                                         pn = find_first_zero_bit(port_mask, maxport);
1133
1134                                 if (pn > maxport) {
1135                                         dev_err(ctrl->dev, "All ports busy\n");
1136                                         ret = -EBUSY;
1137                                         goto err;
1138                                 }
1139                                 set_bit(pn, port_mask);
1140                                 pconfig[nports].num = pn;
1141                                 pconfig[nports].ch_mask = p_rt->ch_mask;
1142                                 nports++;
1143                         }
1144                 }
1145         }
1146
1147         if (direction == SNDRV_PCM_STREAM_CAPTURE)
1148                 sconfig.direction = SDW_DATA_DIR_TX;
1149         else
1150                 sconfig.direction = SDW_DATA_DIR_RX;
1151
1152         /* hw parameters wil be ignored as we only support PDM */
1153         sconfig.ch_count = 1;
1154         sconfig.frame_rate = params_rate(params);
1155         sconfig.type = stream->type;
1156         sconfig.bps = 1;
1157         sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
1158                               nports, stream);
1159 err:
1160         if (ret) {
1161                 for (i = 0; i < nports; i++)
1162                         clear_bit(pconfig[i].num, port_mask);
1163         }
1164
1165         mutex_unlock(&ctrl->port_lock);
1166
1167         return ret;
1168 }
1169
1170 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
1171                                struct snd_pcm_hw_params *params,
1172                               struct snd_soc_dai *dai)
1173 {
1174         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1175         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1176         int ret;
1177
1178         ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
1179                                            substream->stream);
1180         if (ret)
1181                 qcom_swrm_stream_free_ports(ctrl, sruntime);
1182
1183         return ret;
1184 }
1185
1186 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
1187                              struct snd_soc_dai *dai)
1188 {
1189         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1190         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1191
1192         qcom_swrm_stream_free_ports(ctrl, sruntime);
1193         sdw_stream_remove_master(&ctrl->bus, sruntime);
1194
1195         return 0;
1196 }
1197
1198 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
1199                                     void *stream, int direction)
1200 {
1201         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1202
1203         ctrl->sruntime[dai->id] = stream;
1204
1205         return 0;
1206 }
1207
1208 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
1209 {
1210         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1211
1212         return ctrl->sruntime[dai->id];
1213 }
1214
1215 static int qcom_swrm_startup(struct snd_pcm_substream *substream,
1216                              struct snd_soc_dai *dai)
1217 {
1218         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1219         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1220         struct sdw_stream_runtime *sruntime;
1221         struct snd_soc_dai *codec_dai;
1222         int ret, i;
1223
1224         ret = pm_runtime_resume_and_get(ctrl->dev);
1225         if (ret < 0 && ret != -EACCES) {
1226                 dev_err_ratelimited(ctrl->dev,
1227                                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
1228                                     __func__, ret);
1229                 return ret;
1230         }
1231
1232         sruntime = sdw_alloc_stream(dai->name);
1233         if (!sruntime)
1234                 return -ENOMEM;
1235
1236         ctrl->sruntime[dai->id] = sruntime;
1237
1238         for_each_rtd_codec_dais(rtd, i, codec_dai) {
1239                 ret = snd_soc_dai_set_stream(codec_dai, sruntime,
1240                                              substream->stream);
1241                 if (ret < 0 && ret != -ENOTSUPP) {
1242                         dev_err(dai->dev, "Failed to set sdw stream on %s\n",
1243                                 codec_dai->name);
1244                         sdw_release_stream(sruntime);
1245                         return ret;
1246                 }
1247         }
1248
1249         return 0;
1250 }
1251
1252 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
1253                                struct snd_soc_dai *dai)
1254 {
1255         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1256
1257         swrm_wait_for_wr_fifo_done(ctrl);
1258         sdw_release_stream(ctrl->sruntime[dai->id]);
1259         ctrl->sruntime[dai->id] = NULL;
1260         pm_runtime_mark_last_busy(ctrl->dev);
1261         pm_runtime_put_autosuspend(ctrl->dev);
1262
1263 }
1264
1265 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
1266         .hw_params = qcom_swrm_hw_params,
1267         .hw_free = qcom_swrm_hw_free,
1268         .startup = qcom_swrm_startup,
1269         .shutdown = qcom_swrm_shutdown,
1270         .set_stream = qcom_swrm_set_sdw_stream,
1271         .get_stream = qcom_swrm_get_sdw_stream,
1272 };
1273
1274 static const struct snd_soc_component_driver qcom_swrm_dai_component = {
1275         .name = "soundwire",
1276 };
1277
1278 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1279 {
1280         int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1281         struct snd_soc_dai_driver *dais;
1282         struct snd_soc_pcm_stream *stream;
1283         struct device *dev = ctrl->dev;
1284         int i;
1285
1286         /* PDM dais are only tested for now */
1287         dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
1288         if (!dais)
1289                 return -ENOMEM;
1290
1291         for (i = 0; i < num_dais; i++) {
1292                 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
1293                 if (!dais[i].name)
1294                         return -ENOMEM;
1295
1296                 if (i < ctrl->num_dout_ports)
1297                         stream = &dais[i].playback;
1298                 else
1299                         stream = &dais[i].capture;
1300
1301                 stream->channels_min = 1;
1302                 stream->channels_max = 1;
1303                 stream->rates = SNDRV_PCM_RATE_48000;
1304                 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
1305
1306                 dais[i].ops = &qcom_swrm_pdm_dai_ops;
1307                 dais[i].id = i;
1308         }
1309
1310         return devm_snd_soc_register_component(ctrl->dev,
1311                                                 &qcom_swrm_dai_component,
1312                                                 dais, num_dais);
1313 }
1314
1315 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1316 {
1317         struct device_node *np = ctrl->dev->of_node;
1318         u8 off1[QCOM_SDW_MAX_PORTS];
1319         u8 off2[QCOM_SDW_MAX_PORTS];
1320         u16 si[QCOM_SDW_MAX_PORTS];
1321         u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
1322         u8 hstart[QCOM_SDW_MAX_PORTS];
1323         u8 hstop[QCOM_SDW_MAX_PORTS];
1324         u8 word_length[QCOM_SDW_MAX_PORTS];
1325         u8 blk_group_count[QCOM_SDW_MAX_PORTS];
1326         u8 lane_control[QCOM_SDW_MAX_PORTS];
1327         int i, ret, nports, val;
1328         bool si_16 = false;
1329
1330         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1331
1332         ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1333         ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1334
1335         ret = of_property_read_u32(np, "qcom,din-ports", &val);
1336         if (ret)
1337                 return ret;
1338
1339         if (val > ctrl->num_din_ports)
1340                 return -EINVAL;
1341
1342         ctrl->num_din_ports = val;
1343
1344         ret = of_property_read_u32(np, "qcom,dout-ports", &val);
1345         if (ret)
1346                 return ret;
1347
1348         if (val > ctrl->num_dout_ports)
1349                 return -EINVAL;
1350
1351         ctrl->num_dout_ports = val;
1352
1353         nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1354         if (nports > QCOM_SDW_MAX_PORTS)
1355                 return -EINVAL;
1356
1357         /* Valid port numbers are from 1-14, so mask out port 0 explicitly */
1358         set_bit(0, &ctrl->dout_port_mask);
1359         set_bit(0, &ctrl->din_port_mask);
1360
1361         ret = of_property_read_u8_array(np, "qcom,ports-offset1",
1362                                         off1, nports);
1363         if (ret)
1364                 return ret;
1365
1366         ret = of_property_read_u8_array(np, "qcom,ports-offset2",
1367                                         off2, nports);
1368         if (ret)
1369                 return ret;
1370
1371         ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
1372                                         (u8 *)si, nports);
1373         if (ret) {
1374                 ret = of_property_read_u16_array(np, "qcom,ports-sinterval",
1375                                                  si, nports);
1376                 if (ret)
1377                         return ret;
1378                 si_16 = true;
1379         }
1380
1381         ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
1382                                         bp_mode, nports);
1383         if (ret) {
1384                 if (ctrl->version <= SWRM_VERSION_1_3_0)
1385                         memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1386                 else
1387                         return ret;
1388         }
1389
1390         memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1391         of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports);
1392
1393         memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1394         of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports);
1395
1396         memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1397         of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports);
1398
1399         memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1400         of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports);
1401
1402         memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1403         of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports);
1404
1405         for (i = 0; i < nports; i++) {
1406                 /* Valid port number range is from 1-14 */
1407                 if (si_16)
1408                         ctrl->pconfig[i + 1].si = si[i];
1409                 else
1410                         ctrl->pconfig[i + 1].si = ((u8 *)si)[i];
1411                 ctrl->pconfig[i + 1].off1 = off1[i];
1412                 ctrl->pconfig[i + 1].off2 = off2[i];
1413                 ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
1414                 ctrl->pconfig[i + 1].hstart = hstart[i];
1415                 ctrl->pconfig[i + 1].hstop = hstop[i];
1416                 ctrl->pconfig[i + 1].word_length = word_length[i];
1417                 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
1418                 ctrl->pconfig[i + 1].lane_control = lane_control[i];
1419         }
1420
1421         return 0;
1422 }
1423
1424 #ifdef CONFIG_DEBUG_FS
1425 static int swrm_reg_show(struct seq_file *s_file, void *data)
1426 {
1427         struct qcom_swrm_ctrl *ctrl = s_file->private;
1428         int reg, reg_val, ret;
1429
1430         ret = pm_runtime_resume_and_get(ctrl->dev);
1431         if (ret < 0 && ret != -EACCES) {
1432                 dev_err_ratelimited(ctrl->dev,
1433                                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
1434                                     __func__, ret);
1435                 return ret;
1436         }
1437
1438         for (reg = 0; reg <= ctrl->max_reg; reg += 4) {
1439                 ctrl->reg_read(ctrl, reg, &reg_val);
1440                 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
1441         }
1442         pm_runtime_mark_last_busy(ctrl->dev);
1443         pm_runtime_put_autosuspend(ctrl->dev);
1444
1445
1446         return 0;
1447 }
1448 DEFINE_SHOW_ATTRIBUTE(swrm_reg);
1449 #endif
1450
1451 static int qcom_swrm_probe(struct platform_device *pdev)
1452 {
1453         struct device *dev = &pdev->dev;
1454         struct sdw_master_prop *prop;
1455         struct sdw_bus_params *params;
1456         struct qcom_swrm_ctrl *ctrl;
1457         const struct qcom_swrm_data *data;
1458         int ret;
1459         u32 val;
1460
1461         ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1462         if (!ctrl)
1463                 return -ENOMEM;
1464
1465         data = of_device_get_match_data(dev);
1466         ctrl->max_reg = data->max_reg;
1467         ctrl->reg_layout = data->reg_layout;
1468         ctrl->rows_index = sdw_find_row_index(data->default_rows);
1469         ctrl->cols_index = sdw_find_col_index(data->default_cols);
1470 #if IS_REACHABLE(CONFIG_SLIMBUS)
1471         if (dev->parent->bus == &slimbus_bus) {
1472 #else
1473         if (false) {
1474 #endif
1475                 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1476                 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1477                 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1478                 if (!ctrl->regmap)
1479                         return -EINVAL;
1480         } else {
1481                 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1482                 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1483                 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1484                 if (IS_ERR(ctrl->mmio))
1485                         return PTR_ERR(ctrl->mmio);
1486         }
1487
1488         if (data->sw_clk_gate_required) {
1489                 ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr");
1490                 if (IS_ERR(ctrl->audio_cgcr)) {
1491                         dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n");
1492                         ret = PTR_ERR(ctrl->audio_cgcr);
1493                         goto err_init;
1494                 }
1495         }
1496
1497         ctrl->irq = of_irq_get(dev->of_node, 0);
1498         if (ctrl->irq < 0) {
1499                 ret = ctrl->irq;
1500                 goto err_init;
1501         }
1502
1503         ctrl->hclk = devm_clk_get(dev, "iface");
1504         if (IS_ERR(ctrl->hclk)) {
1505                 ret = PTR_ERR(ctrl->hclk);
1506                 goto err_init;
1507         }
1508
1509         clk_prepare_enable(ctrl->hclk);
1510
1511         ctrl->dev = dev;
1512         dev_set_drvdata(&pdev->dev, ctrl);
1513         mutex_init(&ctrl->port_lock);
1514         init_completion(&ctrl->broadcast);
1515         init_completion(&ctrl->enumeration);
1516
1517         ctrl->bus.ops = &qcom_swrm_ops;
1518         ctrl->bus.port_ops = &qcom_swrm_port_ops;
1519         ctrl->bus.compute_params = &qcom_swrm_compute_params;
1520         ctrl->bus.clk_stop_timeout = 300;
1521
1522         ret = qcom_swrm_get_port_config(ctrl);
1523         if (ret)
1524                 goto err_clk;
1525
1526         params = &ctrl->bus.params;
1527         params->max_dr_freq = DEFAULT_CLK_FREQ;
1528         params->curr_dr_freq = DEFAULT_CLK_FREQ;
1529         params->col = data->default_cols;
1530         params->row = data->default_rows;
1531         ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1532         params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1533         params->next_bank = !params->curr_bank;
1534
1535         prop = &ctrl->bus.prop;
1536         prop->max_clk_freq = DEFAULT_CLK_FREQ;
1537         prop->num_clk_gears = 0;
1538         prop->num_clk_freq = MAX_FREQ_NUM;
1539         prop->clk_freq = &qcom_swrm_freq_tbl[0];
1540         prop->default_col = data->default_cols;
1541         prop->default_row = data->default_rows;
1542
1543         ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1544
1545         ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1546                                         qcom_swrm_irq_handler,
1547                                         IRQF_TRIGGER_RISING |
1548                                         IRQF_ONESHOT,
1549                                         "soundwire", ctrl);
1550         if (ret) {
1551                 dev_err(dev, "Failed to request soundwire irq\n");
1552                 goto err_clk;
1553         }
1554
1555         ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1556         if (ctrl->wake_irq > 0) {
1557                 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1558                                                 qcom_swrm_wake_irq_handler,
1559                                                 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1560                                                 "swr_wake_irq", ctrl);
1561                 if (ret) {
1562                         dev_err(dev, "Failed to request soundwire wake irq\n");
1563                         goto err_init;
1564                 }
1565         }
1566
1567         ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1568         if (ret) {
1569                 dev_err(dev, "Failed to register Soundwire controller (%d)\n",
1570                         ret);
1571                 goto err_clk;
1572         }
1573
1574         qcom_swrm_init(ctrl);
1575         wait_for_completion_timeout(&ctrl->enumeration,
1576                                     msecs_to_jiffies(TIMEOUT_MS));
1577         ret = qcom_swrm_register_dais(ctrl);
1578         if (ret)
1579                 goto err_master_add;
1580
1581         dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
1582                  (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1583                  ctrl->version & 0xffff);
1584
1585         pm_runtime_set_autosuspend_delay(dev, 3000);
1586         pm_runtime_use_autosuspend(dev);
1587         pm_runtime_mark_last_busy(dev);
1588         pm_runtime_set_active(dev);
1589         pm_runtime_enable(dev);
1590
1591         /* Clk stop is not supported on WSA Soundwire masters */
1592         if (ctrl->version <= SWRM_VERSION_1_3_0) {
1593                 ctrl->clock_stop_not_supported = true;
1594         } else {
1595                 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1596                 if (val == MASTER_ID_WSA)
1597                         ctrl->clock_stop_not_supported = true;
1598         }
1599
1600 #ifdef CONFIG_DEBUG_FS
1601         ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1602         debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1603                             &swrm_reg_fops);
1604 #endif
1605
1606         return 0;
1607
1608 err_master_add:
1609         sdw_bus_master_delete(&ctrl->bus);
1610 err_clk:
1611         clk_disable_unprepare(ctrl->hclk);
1612 err_init:
1613         return ret;
1614 }
1615
1616 static int qcom_swrm_remove(struct platform_device *pdev)
1617 {
1618         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1619
1620         sdw_bus_master_delete(&ctrl->bus);
1621         clk_disable_unprepare(ctrl->hclk);
1622
1623         return 0;
1624 }
1625
1626 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl)
1627 {
1628         int retry = SWRM_LINK_STATUS_RETRY_CNT;
1629         int comp_sts;
1630
1631         do {
1632                 ctrl->reg_read(ctrl, SWRM_COMP_STATUS, &comp_sts);
1633
1634                 if (comp_sts & SWRM_FRM_GEN_ENABLED)
1635                         return true;
1636
1637                 usleep_range(500, 510);
1638         } while (retry--);
1639
1640         dev_err(ctrl->dev, "%s: link status not %s\n", __func__,
1641                 comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
1642
1643         return false;
1644 }
1645
1646 static int __maybe_unused swrm_runtime_resume(struct device *dev)
1647 {
1648         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1649         int ret;
1650
1651         if (ctrl->wake_irq > 0) {
1652                 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1653                         disable_irq_nosync(ctrl->wake_irq);
1654         }
1655
1656         clk_prepare_enable(ctrl->hclk);
1657
1658         if (ctrl->clock_stop_not_supported) {
1659                 reinit_completion(&ctrl->enumeration);
1660                 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1661                 usleep_range(100, 105);
1662
1663                 qcom_swrm_init(ctrl);
1664
1665                 usleep_range(100, 105);
1666                 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1667                         dev_err(ctrl->dev, "link failed to connect\n");
1668
1669                 /* wait for hw enumeration to complete */
1670                 wait_for_completion_timeout(&ctrl->enumeration,
1671                                             msecs_to_jiffies(TIMEOUT_MS));
1672                 qcom_swrm_get_device_status(ctrl);
1673                 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1674         } else {
1675                 reset_control_reset(ctrl->audio_cgcr);
1676
1677                 if (ctrl->version == SWRM_VERSION_1_7_0) {
1678                         ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1679                         ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1680                                         SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
1681                 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
1682                         ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1683                         ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
1684                                         SWRM_V2_0_CLK_CTRL_CLK_START);
1685                 } else {
1686                         ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1687                 }
1688                 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1689                         SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
1690
1691                 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1692                 if (ctrl->version < SWRM_VERSION_2_0_0)
1693                         ctrl->reg_write(ctrl,
1694                                         ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1695                                         ctrl->intr_mask);
1696                 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1697                                 ctrl->intr_mask);
1698
1699                 usleep_range(100, 105);
1700                 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1701                         dev_err(ctrl->dev, "link failed to connect\n");
1702
1703                 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1704                 if (ret < 0)
1705                         dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1706         }
1707
1708         return 0;
1709 }
1710
1711 static int __maybe_unused swrm_runtime_suspend(struct device *dev)
1712 {
1713         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1714         int ret;
1715
1716         swrm_wait_for_wr_fifo_done(ctrl);
1717         if (!ctrl->clock_stop_not_supported) {
1718                 /* Mask bus clash interrupt */
1719                 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1720                 if (ctrl->version < SWRM_VERSION_2_0_0)
1721                         ctrl->reg_write(ctrl,
1722                                         ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1723                                         ctrl->intr_mask);
1724                 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1725                                 ctrl->intr_mask);
1726                 /* Prepare slaves for clock stop */
1727                 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1728                 if (ret < 0 && ret != -ENODATA) {
1729                         dev_err(dev, "prepare clock stop failed %d", ret);
1730                         return ret;
1731                 }
1732
1733                 ret = sdw_bus_clk_stop(&ctrl->bus);
1734                 if (ret < 0 && ret != -ENODATA) {
1735                         dev_err(dev, "bus clock stop failed %d", ret);
1736                         return ret;
1737                 }
1738         }
1739
1740         clk_disable_unprepare(ctrl->hclk);
1741
1742         usleep_range(300, 305);
1743
1744         if (ctrl->wake_irq > 0) {
1745                 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1746                         enable_irq(ctrl->wake_irq);
1747         }
1748
1749         return 0;
1750 }
1751
1752 static const struct dev_pm_ops swrm_dev_pm_ops = {
1753         SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL)
1754 };
1755
1756 static const struct of_device_id qcom_swrm_of_match[] = {
1757         { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1758         { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1759         { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
1760         { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data },
1761         { .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data },
1762         {/* sentinel */},
1763 };
1764
1765 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
1766
1767 static struct platform_driver qcom_swrm_driver = {
1768         .probe  = &qcom_swrm_probe,
1769         .remove = &qcom_swrm_remove,
1770         .driver = {
1771                 .name   = "qcom-soundwire",
1772                 .of_match_table = qcom_swrm_of_match,
1773                 .pm = &swrm_dev_pm_ops,
1774         }
1775 };
1776 module_platform_driver(qcom_swrm_driver);
1777
1778 MODULE_DESCRIPTION("Qualcomm soundwire driver");
1779 MODULE_LICENSE("GPL v2");