drivers/soundwire/intel.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 // Copyright(c) 2015-17 Intel Corporation.
   3
   4 /*
   5  * Soundwire Intel Master Driver
   6  */
   7
   8 #include <linux/acpi.h>
   9 #include <linux/debugfs.h>
  10 #include <linux/delay.h>
  11 #include <linux/module.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/auxiliary_bus.h>
  15 #include <sound/pcm_params.h>
  16 #include <linux/pm_runtime.h>
  17 #include <sound/soc.h>
  18 #include <linux/soundwire/sdw_registers.h>
  19 #include <linux/soundwire/sdw.h>
  20 #include <linux/soundwire/sdw_intel.h>
  21 #include "cadence_master.h"
  22 #include "bus.h"
  23 #include "intel.h"
  24
  25 #define INTEL_MASTER_SUSPEND_DELAY_MS   3000
  26 #define INTEL_MASTER_RESET_ITERATIONS   10
  27
  28 /*
  29  * debug/config flags for the Intel SoundWire Master.
  30  *
  31  * Since we may have multiple masters active, we can have up to 8
  32  * flags reused in each byte, with master0 using the ls-byte, etc.
  33  */
  34
  35 #define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME             BIT(0)
  36 #define SDW_INTEL_MASTER_DISABLE_CLOCK_STOP             BIT(1)
  37 #define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE        BIT(2)
  38 #define SDW_INTEL_MASTER_DISABLE_MULTI_LINK             BIT(3)
  39
  40 static int md_flags;
  41 module_param_named(sdw_md_flags, md_flags, int, 0444);
  42 MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");
  43
  44 enum intel_pdi_type {
  45         INTEL_PDI_IN = 0,
  46         INTEL_PDI_OUT = 1,
  47         INTEL_PDI_BD = 2,
  48 };
  49
  50 #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
  51
  52 /*
  53  * Read, write helpers for HW registers
  54  */
  55 static inline int intel_readl(void __iomem *base, int offset)
  56 {
  57         return readl(base + offset);
  58 }
  59
  60 static inline void intel_writel(void __iomem *base, int offset, int value)
  61 {
  62         writel(value, base + offset);
  63 }
  64
  65 static inline u16 intel_readw(void __iomem *base, int offset)
  66 {
  67         return readw(base + offset);
  68 }
  69
  70 static inline void intel_writew(void __iomem *base, int offset, u16 value)
  71 {
  72         writew(value, base + offset);
  73 }
  74
  75 static int intel_wait_bit(void __iomem *base, int offset, u32 mask, u32 target)
  76 {
  77         int timeout = 10;
  78         u32 reg_read;
  79
  80         do {
  81                 reg_read = readl(base + offset);
  82                 if ((reg_read & mask) == target)
  83                         return 0;
  84
  85                 timeout--;
  86                 usleep_range(50, 100);
  87         } while (timeout != 0);
  88
  89         return -EAGAIN;
  90 }
  91
  92 static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
  93 {
  94         writel(value, base + offset);
  95         return intel_wait_bit(base, offset, mask, 0);
  96 }
  97
  98 static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
  99 {
 100         writel(value, base + offset);
 101         return intel_wait_bit(base, offset, mask, mask);
 102 }
 103
 104 /*
 105  * debugfs
 106  */
 107 #ifdef CONFIG_DEBUG_FS
 108
 109 #define RD_BUF (2 * PAGE_SIZE)
 110
 111 static ssize_t intel_sprintf(void __iomem *mem, bool l,
 112                              char *buf, size_t pos, unsigned int reg)
 113 {
 114         int value;
 115
 116         if (l)
 117                 value = intel_readl(mem, reg);
 118         else
 119                 value = intel_readw(mem, reg);
 120
 121         return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value);
 122 }
 123
 124 static int intel_reg_show(struct seq_file *s_file, void *data)
 125 {
 126         struct sdw_intel *sdw = s_file->private;
 127         void __iomem *s = sdw->link_res->shim;
 128         void __iomem *a = sdw->link_res->alh;
 129         char *buf;
 130         ssize_t ret;
 131         int i, j;
 132         unsigned int links, reg;
 133
 134         buf = kzalloc(RD_BUF, GFP_KERNEL);
 135         if (!buf)
 136                 return -ENOMEM;
 137
 138         links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0);
 139
 140         ret = scnprintf(buf, RD_BUF, "Register  Value\n");
 141         ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n");
 142
 143         for (i = 0; i < links; i++) {
 144                 reg = SDW_SHIM_LCAP + i * 4;
 145                 ret += intel_sprintf(s, true, buf, ret, reg);
 146         }
 147
 148         for (i = 0; i < links; i++) {
 149                 ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i);
 150                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i));
 151                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i));
 152                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i));
 153                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i));
 154                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i));
 155                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i));
 156
 157                 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n");
 158
 159                 /*
 160                  * the value 10 is the number of PDIs. We will need a
 161                  * cleanup to remove hard-coded Intel configurations
 162                  * from cadence_master.c
 163                  */
 164                 for (j = 0; j < 10; j++) {
 165                         ret += intel_sprintf(s, false, buf, ret,
 166                                         SDW_SHIM_PCMSYCHM(i, j));
 167                         ret += intel_sprintf(s, false, buf, ret,
 168                                         SDW_SHIM_PCMSYCHC(i, j));
 169                 }
 170                 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n");
 171
 172                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i));
 173                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i));
 174                 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i));
 175         }
 176
 177         ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n");
 178         ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN);
 179         ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS);
 180
 181         ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n");
 182         for (i = 0; i < SDW_ALH_NUM_STREAMS; i++)
 183                 ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i));
 184
 185         seq_printf(s_file, "%s", buf);
 186         kfree(buf);
 187
 188         return 0;
 189 }
 190 DEFINE_SHOW_ATTRIBUTE(intel_reg);
 191
 192 static int intel_set_m_datamode(void *data, u64 value)
 193 {
 194         struct sdw_intel *sdw = data;
 195         struct sdw_bus *bus = &sdw->cdns.bus;
 196
 197         if (value > SDW_PORT_DATA_MODE_STATIC_1)
 198                 return -EINVAL;
 199
 200         /* Userspace changed the hardware state behind the kernel's back */
 201         add_taint(TAINT_USER, LOCKDEP_STILL_OK);
 202
 203         bus->params.m_data_mode = value;
 204
 205         return 0;
 206 }
 207 DEFINE_DEBUGFS_ATTRIBUTE(intel_set_m_datamode_fops, NULL,
 208                          intel_set_m_datamode, "%llu\n");
 209
 210 static int intel_set_s_datamode(void *data, u64 value)
 211 {
 212         struct sdw_intel *sdw = data;
 213         struct sdw_bus *bus = &sdw->cdns.bus;
 214
 215         if (value > SDW_PORT_DATA_MODE_STATIC_1)
 216                 return -EINVAL;
 217
 218         /* Userspace changed the hardware state behind the kernel's back */
 219         add_taint(TAINT_USER, LOCKDEP_STILL_OK);
 220
 221         bus->params.s_data_mode = value;
 222
 223         return 0;
 224 }
 225 DEFINE_DEBUGFS_ATTRIBUTE(intel_set_s_datamode_fops, NULL,
 226                          intel_set_s_datamode, "%llu\n");
 227
 228 static void intel_debugfs_init(struct sdw_intel *sdw)
 229 {
 230         struct dentry *root = sdw->cdns.bus.debugfs;
 231
 232         if (!root)
 233                 return;
 234
 235         sdw->debugfs = debugfs_create_dir("intel-sdw", root);
 236
 237         debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw,
 238                             &intel_reg_fops);
 239
 240         debugfs_create_file("intel-m-datamode", 0200, sdw->debugfs, sdw,
 241                             &intel_set_m_datamode_fops);
 242
 243         debugfs_create_file("intel-s-datamode", 0200, sdw->debugfs, sdw,
 244                             &intel_set_s_datamode_fops);
 245
 246         sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs);
 247 }
 248
 249 static void intel_debugfs_exit(struct sdw_intel *sdw)
 250 {
 251         debugfs_remove_recursive(sdw->debugfs);
 252 }
 253 #else
 254 static void intel_debugfs_init(struct sdw_intel *sdw) {}
 255 static void intel_debugfs_exit(struct sdw_intel *sdw) {}
 256 #endif /* CONFIG_DEBUG_FS */
 257
 258 /*
 259  * shim ops
 260  */
 261
 262 static int intel_link_power_up(struct sdw_intel *sdw)
 263 {
 264         unsigned int link_id = sdw->instance;
 265         void __iomem *shim = sdw->link_res->shim;
 266         u32 *shim_mask = sdw->link_res->shim_mask;
 267         struct sdw_bus *bus = &sdw->cdns.bus;
 268         struct sdw_master_prop *prop = &bus->prop;
 269         u32 spa_mask, cpa_mask;
 270         u32 link_control;
 271         int ret = 0;
 272         u32 syncprd;
 273         u32 sync_reg;
 274
 275         mutex_lock(sdw->link_res->shim_lock);
 276
 277         /*
 278          * The hardware relies on an internal counter, typically 4kHz,
 279          * to generate the SoundWire SSP - which defines a 'safe'
 280          * synchronization point between commands and audio transport
 281          * and allows for multi link synchronization. The SYNCPRD value
 282          * is only dependent on the oscillator clock provided to
 283          * the IP, so adjust based on _DSD properties reported in DSDT
 284          * tables. The values reported are based on either 24MHz
 285          * (CNL/CML) or 38.4 MHz (ICL/TGL+).
 286          */
 287         if (prop->mclk_freq % 6000000)
 288                 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
 289         else
 290                 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;
 291
 292         if (!*shim_mask) {
 293                 dev_dbg(sdw->cdns.dev, "%s: powering up all links\n", __func__);
 294
 295                 /* we first need to program the SyncPRD/CPU registers */
 296                 dev_dbg(sdw->cdns.dev,
 297                         "%s: first link up, programming SYNCPRD\n", __func__);
 298
 299                 /* set SyncPRD period */
 300                 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 301                 u32p_replace_bits(&sync_reg, syncprd, SDW_SHIM_SYNC_SYNCPRD);
 302
 303                 /* Set SyncCPU bit */
 304                 sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
 305                 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
 306
 307                 /* Link power up sequence */
 308                 link_control = intel_readl(shim, SDW_SHIM_LCTL);
 309
 310                 /* only power-up enabled links */
 311                 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, sdw->link_res->link_mask);
 312                 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);
 313
 314                 link_control |=  spa_mask;
 315
 316                 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
 317                 if (ret < 0) {
 318                         dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret);
 319                         goto out;
 320                 }
 321
 322                 /* SyncCPU will change once link is active */
 323                 ret = intel_wait_bit(shim, SDW_SHIM_SYNC,
 324                                      SDW_SHIM_SYNC_SYNCCPU, 0);
 325                 if (ret < 0) {
 326                         dev_err(sdw->cdns.dev,
 327                                 "Failed to set SHIM_SYNC: %d\n", ret);
 328                         goto out;
 329                 }
 330         }
 331
 332         *shim_mask |= BIT(link_id);
 333
 334         sdw->cdns.link_up = true;
 335 out:
 336         mutex_unlock(sdw->link_res->shim_lock);
 337
 338         return ret;
 339 }
 340
 341 /* this needs to be called with shim_lock */
 342 static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw)
 343 {
 344         void __iomem *shim = sdw->link_res->shim;
 345         unsigned int link_id = sdw->instance;
 346         u16 ioctl;
 347
 348         /* Switch to MIP from Glue logic */
 349         ioctl = intel_readw(shim,  SDW_SHIM_IOCTL(link_id));
 350
 351         ioctl &= ~(SDW_SHIM_IOCTL_DOE);
 352         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 353         usleep_range(10, 15);
 354
 355         ioctl &= ~(SDW_SHIM_IOCTL_DO);
 356         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 357         usleep_range(10, 15);
 358
 359         ioctl |= (SDW_SHIM_IOCTL_MIF);
 360         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 361         usleep_range(10, 15);
 362
 363         ioctl &= ~(SDW_SHIM_IOCTL_BKE);
 364         ioctl &= ~(SDW_SHIM_IOCTL_COE);
 365         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 366         usleep_range(10, 15);
 367
 368         /* at this point Master IP has full control of the I/Os */
 369 }
 370
 371 /* this needs to be called with shim_lock */
 372 static void intel_shim_master_ip_to_glue(struct sdw_intel *sdw)
 373 {
 374         unsigned int link_id = sdw->instance;
 375         void __iomem *shim = sdw->link_res->shim;
 376         u16 ioctl;
 377
 378         /* Glue logic */
 379         ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
 380         ioctl |= SDW_SHIM_IOCTL_BKE;
 381         ioctl |= SDW_SHIM_IOCTL_COE;
 382         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 383         usleep_range(10, 15);
 384
 385         ioctl &= ~(SDW_SHIM_IOCTL_MIF);
 386         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 387         usleep_range(10, 15);
 388
 389         /* at this point Integration Glue has full control of the I/Os */
 390 }
 391
 392 static int intel_shim_init(struct sdw_intel *sdw, bool clock_stop)
 393 {
 394         void __iomem *shim = sdw->link_res->shim;
 395         unsigned int link_id = sdw->instance;
 396         int ret = 0;
 397         u16 ioctl = 0, act = 0;
 398
 399         mutex_lock(sdw->link_res->shim_lock);
 400
 401         /* Initialize Shim */
 402         ioctl |= SDW_SHIM_IOCTL_BKE;
 403         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 404         usleep_range(10, 15);
 405
 406         ioctl |= SDW_SHIM_IOCTL_WPDD;
 407         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 408         usleep_range(10, 15);
 409
 410         ioctl |= SDW_SHIM_IOCTL_DO;
 411         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 412         usleep_range(10, 15);
 413
 414         ioctl |= SDW_SHIM_IOCTL_DOE;
 415         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 416         usleep_range(10, 15);
 417
 418         intel_shim_glue_to_master_ip(sdw);
 419
 420         u16p_replace_bits(&act, 0x1, SDW_SHIM_CTMCTL_DOAIS);
 421         act |= SDW_SHIM_CTMCTL_DACTQE;
 422         act |= SDW_SHIM_CTMCTL_DODS;
 423         intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
 424         usleep_range(10, 15);
 425
 426         mutex_unlock(sdw->link_res->shim_lock);
 427
 428         return ret;
 429 }
 430
 431 static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable)
 432 {
 433         void __iomem *shim = sdw->link_res->shim;
 434         unsigned int link_id = sdw->instance;
 435         u16 wake_en, wake_sts;
 436
 437         mutex_lock(sdw->link_res->shim_lock);
 438         wake_en = intel_readw(shim, SDW_SHIM_WAKEEN);
 439
 440         if (wake_enable) {
 441                 /* Enable the wakeup */
 442                 wake_en |= (SDW_SHIM_WAKEEN_ENABLE << link_id);
 443                 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
 444         } else {
 445                 /* Disable the wake up interrupt */
 446                 wake_en &= ~(SDW_SHIM_WAKEEN_ENABLE << link_id);
 447                 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
 448
 449                 /* Clear wake status */
 450                 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
 451                 wake_sts |= (SDW_SHIM_WAKESTS_STATUS << link_id);
 452                 intel_writew(shim, SDW_SHIM_WAKESTS, wake_sts);
 453         }
 454         mutex_unlock(sdw->link_res->shim_lock);
 455 }
 456
 457 static int intel_link_power_down(struct sdw_intel *sdw)
 458 {
 459         u32 link_control, spa_mask, cpa_mask;
 460         unsigned int link_id = sdw->instance;
 461         void __iomem *shim = sdw->link_res->shim;
 462         u32 *shim_mask = sdw->link_res->shim_mask;
 463         int ret = 0;
 464
 465         mutex_lock(sdw->link_res->shim_lock);
 466
 467         if (!(*shim_mask & BIT(link_id)))
 468                 dev_err(sdw->cdns.dev,
 469                         "%s: Unbalanced power-up/down calls\n", __func__);
 470
 471         sdw->cdns.link_up = false;
 472
 473         intel_shim_master_ip_to_glue(sdw);
 474
 475         *shim_mask &= ~BIT(link_id);
 476
 477         if (!*shim_mask) {
 478
 479                 dev_dbg(sdw->cdns.dev, "%s: powering down all links\n", __func__);
 480
 481                 /* Link power down sequence */
 482                 link_control = intel_readl(shim, SDW_SHIM_LCTL);
 483
 484                 /* only power-down enabled links */
 485                 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, ~sdw->link_res->link_mask);
 486                 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);
 487
 488                 link_control &=  spa_mask;
 489
 490                 ret = intel_clear_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
 491                 if (ret < 0) {
 492                         dev_err(sdw->cdns.dev, "%s: could not power down link\n", __func__);
 493
 494                         /*
 495                          * we leave the sdw->cdns.link_up flag as false since we've disabled
 496                          * the link at this point and cannot handle interrupts any longer.
 497                          */
 498                 }
 499         }
 500
 501         mutex_unlock(sdw->link_res->shim_lock);
 502
 503         return ret;
 504 }
 505
 506 static void intel_shim_sync_arm(struct sdw_intel *sdw)
 507 {
 508         void __iomem *shim = sdw->link_res->shim;
 509         u32 sync_reg;
 510
 511         mutex_lock(sdw->link_res->shim_lock);
 512
 513         /* update SYNC register */
 514         sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 515         sync_reg |= (SDW_SHIM_SYNC_CMDSYNC << sdw->instance);
 516         intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
 517
 518         mutex_unlock(sdw->link_res->shim_lock);
 519 }
 520
 521 static int intel_shim_sync_go_unlocked(struct sdw_intel *sdw)
 522 {
 523         void __iomem *shim = sdw->link_res->shim;
 524         u32 sync_reg;
 525         int ret;
 526
 527         /* Read SYNC register */
 528         sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 529
 530         /*
 531          * Set SyncGO bit to synchronously trigger a bank switch for
 532          * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
 533          * the Masters.
 534          */
 535         sync_reg |= SDW_SHIM_SYNC_SYNCGO;
 536
 537         ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
 538                               SDW_SHIM_SYNC_SYNCGO);
 539
 540         if (ret < 0)
 541                 dev_err(sdw->cdns.dev, "SyncGO clear failed: %d\n", ret);
 542
 543         return ret;
 544 }
 545
 546 static int intel_shim_sync_go(struct sdw_intel *sdw)
 547 {
 548         int ret;
 549
 550         mutex_lock(sdw->link_res->shim_lock);
 551
 552         ret = intel_shim_sync_go_unlocked(sdw);
 553
 554         mutex_unlock(sdw->link_res->shim_lock);
 555
 556         return ret;
 557 }
 558
 559 /*
 560  * PDI routines
 561  */
 562 static void intel_pdi_init(struct sdw_intel *sdw,
 563                            struct sdw_cdns_stream_config *config)
 564 {
 565         void __iomem *shim = sdw->link_res->shim;
 566         unsigned int link_id = sdw->instance;
 567         int pcm_cap, pdm_cap;
 568
 569         /* PCM Stream Capability */
 570         pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
 571
 572         config->pcm_bd = FIELD_GET(SDW_SHIM_PCMSCAP_BSS, pcm_cap);
 573         config->pcm_in = FIELD_GET(SDW_SHIM_PCMSCAP_ISS, pcm_cap);
 574         config->pcm_out = FIELD_GET(SDW_SHIM_PCMSCAP_OSS, pcm_cap);
 575
 576         dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
 577                 config->pcm_bd, config->pcm_in, config->pcm_out);
 578
 579         /* PDM Stream Capability */
 580         pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
 581
 582         config->pdm_bd = FIELD_GET(SDW_SHIM_PDMSCAP_BSS, pdm_cap);
 583         config->pdm_in = FIELD_GET(SDW_SHIM_PDMSCAP_ISS, pdm_cap);
 584         config->pdm_out = FIELD_GET(SDW_SHIM_PDMSCAP_OSS, pdm_cap);
 585
 586         dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n",
 587                 config->pdm_bd, config->pdm_in, config->pdm_out);
 588 }
 589
 590 static int
 591 intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm)
 592 {
 593         void __iomem *shim = sdw->link_res->shim;
 594         unsigned int link_id = sdw->instance;
 595         int count;
 596
 597         if (pcm) {
 598                 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
 599
 600                 /*
 601                  * WORKAROUND: on all existing Intel controllers, pdi
 602                  * number 2 reports channel count as 1 even though it
 603                  * supports 8 channels. Performing hardcoding for pdi
 604                  * number 2.
 605                  */
 606                 if (pdi_num == 2)
 607                         count = 7;
 608
 609         } else {
 610                 count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
 611                 count = FIELD_GET(SDW_SHIM_PDMSCAP_CPSS, count);
 612         }
 613
 614         /* zero based values for channel count in register */
 615         count++;
 616
 617         return count;
 618 }
 619
 620 static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
 621                                    struct sdw_cdns_pdi *pdi,
 622                                    unsigned int num_pdi,
 623                                    unsigned int *num_ch, bool pcm)
 624 {
 625         int i, ch_count = 0;
 626
 627         for (i = 0; i < num_pdi; i++) {
 628                 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm);
 629                 ch_count += pdi->ch_count;
 630                 pdi++;
 631         }
 632
 633         *num_ch = ch_count;
 634         return 0;
 635 }
 636
 637 static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
 638                                       struct sdw_cdns_streams *stream, bool pcm)
 639 {
 640         intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
 641                                 &stream->num_ch_bd, pcm);
 642
 643         intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
 644                                 &stream->num_ch_in, pcm);
 645
 646         intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
 647                                 &stream->num_ch_out, pcm);
 648
 649         return 0;
 650 }
 651
 652 static int intel_pdi_ch_update(struct sdw_intel *sdw)
 653 {
 654         /* First update PCM streams followed by PDM streams */
 655         intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true);
 656         intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false);
 657
 658         return 0;
 659 }
 660
 661 static void
 662 intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
 663 {
 664         void __iomem *shim = sdw->link_res->shim;
 665         unsigned int link_id = sdw->instance;
 666         int pdi_conf = 0;
 667
 668         /* the Bulk and PCM streams are not contiguous */
 669         pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
 670         if (pdi->num >= 2)
 671                 pdi->intel_alh_id += 2;
 672
 673         /*
 674          * Program stream parameters to stream SHIM register
 675          * This is applicable for PCM stream only.
 676          */
 677         if (pdi->type != SDW_STREAM_PCM)
 678                 return;
 679
 680         if (pdi->dir == SDW_DATA_DIR_RX)
 681                 pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
 682         else
 683                 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
 684
 685         u32p_replace_bits(&pdi_conf, pdi->intel_alh_id, SDW_SHIM_PCMSYCM_STREAM);
 686         u32p_replace_bits(&pdi_conf, pdi->l_ch_num, SDW_SHIM_PCMSYCM_LCHN);
 687         u32p_replace_bits(&pdi_conf, pdi->h_ch_num, SDW_SHIM_PCMSYCM_HCHN);
 688
 689         intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
 690 }
 691
 692 static void
 693 intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
 694 {
 695         void __iomem *alh = sdw->link_res->alh;
 696         unsigned int link_id = sdw->instance;
 697         unsigned int conf;
 698
 699         /* the Bulk and PCM streams are not contiguous */
 700         pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
 701         if (pdi->num >= 2)
 702                 pdi->intel_alh_id += 2;
 703
 704         /* Program Stream config ALH register */
 705         conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
 706
 707         u32p_replace_bits(&conf, SDW_ALH_STRMZCFG_DMAT_VAL, SDW_ALH_STRMZCFG_DMAT);
 708         u32p_replace_bits(&conf, pdi->ch_count - 1, SDW_ALH_STRMZCFG_CHN);
 709
 710         intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
 711 }
 712
 713 static int intel_params_stream(struct sdw_intel *sdw,
 714                                struct snd_pcm_substream *substream,
 715                                struct snd_soc_dai *dai,
 716                                struct snd_pcm_hw_params *hw_params,
 717                                int link_id, int alh_stream_id)
 718 {
 719         struct sdw_intel_link_res *res = sdw->link_res;
 720         struct sdw_intel_stream_params_data params_data;
 721
 722         params_data.substream = substream;
 723         params_data.dai = dai;
 724         params_data.hw_params = hw_params;
 725         params_data.link_id = link_id;
 726         params_data.alh_stream_id = alh_stream_id;
 727
 728         if (res->ops && res->ops->params_stream && res->dev)
 729                 return res->ops->params_stream(res->dev,
 730                                                &params_data);
 731         return -EIO;
 732 }
 733
 734 static int intel_free_stream(struct sdw_intel *sdw,
 735                              struct snd_pcm_substream *substream,
 736                              struct snd_soc_dai *dai,
 737                              int link_id)
 738 {
 739         struct sdw_intel_link_res *res = sdw->link_res;
 740         struct sdw_intel_stream_free_data free_data;
 741
 742         free_data.substream = substream;
 743         free_data.dai = dai;
 744         free_data.link_id = link_id;
 745
 746         if (res->ops && res->ops->free_stream && res->dev)
 747                 return res->ops->free_stream(res->dev,
 748                                              &free_data);
 749
 750         return 0;
 751 }
 752
 753 /*
 754  * bank switch routines
 755  */
 756
 757 static int intel_pre_bank_switch(struct sdw_bus *bus)
 758 {
 759         struct sdw_cdns *cdns = bus_to_cdns(bus);
 760         struct sdw_intel *sdw = cdns_to_intel(cdns);
 761
 762         /* Write to register only for multi-link */
 763         if (!bus->multi_link)
 764                 return 0;
 765
 766         intel_shim_sync_arm(sdw);
 767
 768         return 0;
 769 }
 770
 771 static int intel_post_bank_switch(struct sdw_bus *bus)
 772 {
 773         struct sdw_cdns *cdns = bus_to_cdns(bus);
 774         struct sdw_intel *sdw = cdns_to_intel(cdns);
 775         void __iomem *shim = sdw->link_res->shim;
 776         int sync_reg, ret;
 777
 778         /* Write to register only for multi-link */
 779         if (!bus->multi_link)
 780                 return 0;
 781
 782         mutex_lock(sdw->link_res->shim_lock);
 783
 784         /* Read SYNC register */
 785         sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 786
 787         /*
 788          * post_bank_switch() ops is called from the bus in loop for
 789          * all the Masters in the steam with the expectation that
 790          * we trigger the bankswitch for the only first Master in the list
 791          * and do nothing for the other Masters
 792          *
 793          * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
 794          */
 795         if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK)) {
 796                 ret = 0;
 797                 goto unlock;
 798         }
 799
 800         ret = intel_shim_sync_go_unlocked(sdw);
 801 unlock:
 802         mutex_unlock(sdw->link_res->shim_lock);
 803
 804         if (ret < 0)
 805                 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
 806
 807         return ret;
 808 }
 809
 810 /*
 811  * DAI routines
 812  */
 813
 814 static int intel_startup(struct snd_pcm_substream *substream,
 815                          struct snd_soc_dai *dai)
 816 {
 817         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
 818         int ret;
 819
 820         ret = pm_runtime_get_sync(cdns->dev);
 821         if (ret < 0 && ret != -EACCES) {
 822                 dev_err_ratelimited(cdns->dev,
 823                                     "pm_runtime_get_sync failed in %s, ret %d\n",
 824                                     __func__, ret);
 825                 pm_runtime_put_noidle(cdns->dev);
 826                 return ret;
 827         }
 828         return 0;
 829 }
 830
 831 static int intel_hw_params(struct snd_pcm_substream *substream,
 832                            struct snd_pcm_hw_params *params,
 833                            struct snd_soc_dai *dai)
 834 {
 835         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
 836         struct sdw_intel *sdw = cdns_to_intel(cdns);
 837         struct sdw_cdns_dma_data *dma;
 838         struct sdw_cdns_pdi *pdi;
 839         struct sdw_stream_config sconfig;
 840         struct sdw_port_config *pconfig;
 841         int ch, dir;
 842         int ret;
 843         bool pcm = true;
 844
 845         dma = snd_soc_dai_get_dma_data(dai, substream);
 846         if (!dma)
 847                 return -EIO;
 848
 849         ch = params_channels(params);
 850         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 851                 dir = SDW_DATA_DIR_RX;
 852         else
 853                 dir = SDW_DATA_DIR_TX;
 854
 855         if (dma->stream_type == SDW_STREAM_PDM)
 856                 pcm = false;
 857
 858         if (pcm)
 859                 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id);
 860         else
 861                 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pdm, ch, dir, dai->id);
 862
 863         if (!pdi) {
 864                 ret = -EINVAL;
 865                 goto error;
 866         }
 867
 868         /* do run-time configurations for SHIM, ALH and PDI/PORT */
 869         intel_pdi_shim_configure(sdw, pdi);
 870         intel_pdi_alh_configure(sdw, pdi);
 871         sdw_cdns_config_stream(cdns, ch, dir, pdi);
 872
 873         /* store pdi and hw_params, may be needed in prepare step */
 874         dma->suspended = false;
 875         dma->pdi = pdi;
 876         dma->hw_params = params;
 877
 878         /* Inform DSP about PDI stream number */
 879         ret = intel_params_stream(sdw, substream, dai, params,
 880                                   sdw->instance,
 881                                   pdi->intel_alh_id);
 882         if (ret)
 883                 goto error;
 884
 885         sconfig.direction = dir;
 886         sconfig.ch_count = ch;
 887         sconfig.frame_rate = params_rate(params);
 888         sconfig.type = dma->stream_type;
 889
 890         if (dma->stream_type == SDW_STREAM_PDM) {
 891                 sconfig.frame_rate *= 50;
 892                 sconfig.bps = 1;
 893         } else {
 894                 sconfig.bps = snd_pcm_format_width(params_format(params));
 895         }
 896
 897         /* Port configuration */
 898         pconfig = kzalloc(sizeof(*pconfig), GFP_KERNEL);
 899         if (!pconfig) {
 900                 ret =  -ENOMEM;
 901                 goto error;
 902         }
 903
 904         pconfig->num = pdi->num;
 905         pconfig->ch_mask = (1 << ch) - 1;
 906
 907         ret = sdw_stream_add_master(&cdns->bus, &sconfig,
 908                                     pconfig, 1, dma->stream);
 909         if (ret)
 910                 dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
 911
 912         kfree(pconfig);
 913 error:
 914         return ret;
 915 }
 916
 917 static int intel_prepare(struct snd_pcm_substream *substream,
 918                          struct snd_soc_dai *dai)
 919 {
 920         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
 921         struct sdw_intel *sdw = cdns_to_intel(cdns);
 922         struct sdw_cdns_dma_data *dma;
 923         int ch, dir;
 924         int ret = 0;
 925
 926         dma = snd_soc_dai_get_dma_data(dai, substream);
 927         if (!dma) {
 928                 dev_err(dai->dev, "failed to get dma data in %s\n",
 929                         __func__);
 930                 return -EIO;
 931         }
 932
 933         if (dma->suspended) {
 934                 dma->suspended = false;
 935
 936                 /*
 937                  * .prepare() is called after system resume, where we
 938                  * need to reinitialize the SHIM/ALH/Cadence IP.
 939                  * .prepare() is also called to deal with underflows,
 940                  * but in those cases we cannot touch ALH/SHIM
 941                  * registers
 942                  */
 943
 944                 /* configure stream */
 945                 ch = params_channels(dma->hw_params);
 946                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 947                         dir = SDW_DATA_DIR_RX;
 948                 else
 949                         dir = SDW_DATA_DIR_TX;
 950
 951                 intel_pdi_shim_configure(sdw, dma->pdi);
 952                 intel_pdi_alh_configure(sdw, dma->pdi);
 953                 sdw_cdns_config_stream(cdns, ch, dir, dma->pdi);
 954
 955                 /* Inform DSP about PDI stream number */
 956                 ret = intel_params_stream(sdw, substream, dai,
 957                                           dma->hw_params,
 958                                           sdw->instance,
 959                                           dma->pdi->intel_alh_id);
 960         }
 961
 962         return ret;
 963 }
 964
 965 static int
 966 intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
 967 {
 968         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
 969         struct sdw_intel *sdw = cdns_to_intel(cdns);
 970         struct sdw_cdns_dma_data *dma;
 971         int ret;
 972
 973         dma = snd_soc_dai_get_dma_data(dai, substream);
 974         if (!dma)
 975                 return -EIO;
 976
 977         /*
 978          * The sdw stream state will transition to RELEASED when stream->
 979          * master_list is empty. So the stream state will transition to
 980          * DEPREPARED for the first cpu-dai and to RELEASED for the last
 981          * cpu-dai.
 982          */
 983         ret = sdw_stream_remove_master(&cdns->bus, dma->stream);
 984         if (ret < 0) {
 985                 dev_err(dai->dev, "remove master from stream %s failed: %d\n",
 986                         dma->stream->name, ret);
 987                 return ret;
 988         }
 989
 990         ret = intel_free_stream(sdw, substream, dai, sdw->instance);
 991         if (ret < 0) {
 992                 dev_err(dai->dev, "intel_free_stream: failed %d\n", ret);
 993                 return ret;
 994         }
 995
 996         dma->hw_params = NULL;
 997         dma->pdi = NULL;
 998
 999         return 0;
1000 }
1001
1002 static void intel_shutdown(struct snd_pcm_substream *substream,
1003                            struct snd_soc_dai *dai)
1004 {
1005         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
1006
1007         pm_runtime_mark_last_busy(cdns->dev);
1008         pm_runtime_put_autosuspend(cdns->dev);
1009 }
1010
1011 static int intel_component_dais_suspend(struct snd_soc_component *component)
1012 {
1013         struct sdw_cdns_dma_data *dma;
1014         struct snd_soc_dai *dai;
1015
1016         for_each_component_dais(component, dai) {
1017                 /*
1018                  * we don't have a .suspend dai_ops, and we don't have access
1019                  * to the substream, so let's mark both capture and playback
1020                  * DMA contexts as suspended
1021                  */
1022                 dma = dai->playback_dma_data;
1023                 if (dma)
1024                         dma->suspended = true;
1025
1026                 dma = dai->capture_dma_data;
1027                 if (dma)
1028                         dma->suspended = true;
1029         }
1030
1031         return 0;
1032 }
1033
1034 static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
1035                                     void *stream, int direction)
1036 {
1037         return cdns_set_sdw_stream(dai, stream, true, direction);
1038 }
1039
1040 static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai,
1041                                     void *stream, int direction)
1042 {
1043         return cdns_set_sdw_stream(dai, stream, false, direction);
1044 }
1045
1046 static void *intel_get_sdw_stream(struct snd_soc_dai *dai,
1047                                   int direction)
1048 {
1049         struct sdw_cdns_dma_data *dma;
1050
1051         if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1052                 dma = dai->playback_dma_data;
1053         else
1054                 dma = dai->capture_dma_data;
1055
1056         if (!dma)
1057                 return ERR_PTR(-EINVAL);
1058
1059         return dma->stream;
1060 }
1061
1062 static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
1063         .startup = intel_startup,
1064         .hw_params = intel_hw_params,
1065         .prepare = intel_prepare,
1066         .hw_free = intel_hw_free,
1067         .shutdown = intel_shutdown,
1068         .set_sdw_stream = intel_pcm_set_sdw_stream,
1069         .get_sdw_stream = intel_get_sdw_stream,
1070 };
1071
1072 static const struct snd_soc_dai_ops intel_pdm_dai_ops = {
1073         .startup = intel_startup,
1074         .hw_params = intel_hw_params,
1075         .prepare = intel_prepare,
1076         .hw_free = intel_hw_free,
1077         .shutdown = intel_shutdown,
1078         .set_sdw_stream = intel_pdm_set_sdw_stream,
1079         .get_sdw_stream = intel_get_sdw_stream,
1080 };
1081
1082 static const struct snd_soc_component_driver dai_component = {
1083         .name           = "soundwire",
1084         .suspend        = intel_component_dais_suspend
1085 };
1086
1087 static int intel_create_dai(struct sdw_cdns *cdns,
1088                             struct snd_soc_dai_driver *dais,
1089                             enum intel_pdi_type type,
1090                             u32 num, u32 off, u32 max_ch, bool pcm)
1091 {
1092         int i;
1093
1094         if (num == 0)
1095                 return 0;
1096
1097          /* TODO: Read supported rates/formats from hardware */
1098         for (i = off; i < (off + num); i++) {
1099                 dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL,
1100                                               "SDW%d Pin%d",
1101                                               cdns->instance, i);
1102                 if (!dais[i].name)
1103                         return -ENOMEM;
1104
1105                 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
1106                         dais[i].playback.channels_min = 1;
1107                         dais[i].playback.channels_max = max_ch;
1108                         dais[i].playback.rates = SNDRV_PCM_RATE_48000;
1109                         dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
1110                 }
1111
1112                 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
1113                         dais[i].capture.channels_min = 1;
1114                         dais[i].capture.channels_max = max_ch;
1115                         dais[i].capture.rates = SNDRV_PCM_RATE_48000;
1116                         dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
1117                 }
1118
1119                 if (pcm)
1120                         dais[i].ops = &intel_pcm_dai_ops;
1121                 else
1122                         dais[i].ops = &intel_pdm_dai_ops;
1123         }
1124
1125         return 0;
1126 }
1127
1128 static int intel_register_dai(struct sdw_intel *sdw)
1129 {
1130         struct sdw_cdns *cdns = &sdw->cdns;
1131         struct sdw_cdns_streams *stream;
1132         struct snd_soc_dai_driver *dais;
1133         int num_dai, ret, off = 0;
1134
1135         /* DAIs are created based on total number of PDIs supported */
1136         num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi;
1137
1138         dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
1139         if (!dais)
1140                 return -ENOMEM;
1141
1142         /* Create PCM DAIs */
1143         stream = &cdns->pcm;
1144
1145         ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in,
1146                                off, stream->num_ch_in, true);
1147         if (ret)
1148                 return ret;
1149
1150         off += cdns->pcm.num_in;
1151         ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
1152                                off, stream->num_ch_out, true);
1153         if (ret)
1154                 return ret;
1155
1156         off += cdns->pcm.num_out;
1157         ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
1158                                off, stream->num_ch_bd, true);
1159         if (ret)
1160                 return ret;
1161
1162         /* Create PDM DAIs */
1163         stream = &cdns->pdm;
1164         off += cdns->pcm.num_bd;
1165         ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in,
1166                                off, stream->num_ch_in, false);
1167         if (ret)
1168                 return ret;
1169
1170         off += cdns->pdm.num_in;
1171         ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out,
1172                                off, stream->num_ch_out, false);
1173         if (ret)
1174                 return ret;
1175
1176         off += cdns->pdm.num_out;
1177         ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd,
1178                                off, stream->num_ch_bd, false);
1179         if (ret)
1180                 return ret;
1181
1182         return snd_soc_register_component(cdns->dev, &dai_component,
1183                                           dais, num_dai);
1184 }
1185
1186 static int sdw_master_read_intel_prop(struct sdw_bus *bus)
1187 {
1188         struct sdw_master_prop *prop = &bus->prop;
1189         struct fwnode_handle *link;
1190         char name[32];
1191         u32 quirk_mask;
1192
1193         /* Find master handle */
1194         snprintf(name, sizeof(name),
1195                  "mipi-sdw-link-%d-subproperties", bus->link_id);
1196
1197         link = device_get_named_child_node(bus->dev, name);
1198         if (!link) {
1199                 dev_err(bus->dev, "Master node %s not found\n", name);
1200                 return -EIO;
1201         }
1202
1203         fwnode_property_read_u32(link,
1204                                  "intel-sdw-ip-clock",
1205                                  &prop->mclk_freq);
1206
1207         /* the values reported by BIOS are the 2x clock, not the bus clock */
1208         prop->mclk_freq /= 2;
1209
1210         fwnode_property_read_u32(link,
1211                                  "intel-quirk-mask",
1212                                  &quirk_mask);
1213
1214         if (quirk_mask & SDW_INTEL_QUIRK_MASK_BUS_DISABLE)
1215                 prop->hw_disabled = true;
1216
1217         prop->quirks = SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH |
1218                 SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY;
1219
1220         return 0;
1221 }
1222
1223 static int intel_prop_read(struct sdw_bus *bus)
1224 {
1225         /* Initialize with default handler to read all DisCo properties */
1226         sdw_master_read_prop(bus);
1227
1228         /* read Intel-specific properties */
1229         sdw_master_read_intel_prop(bus);
1230
1231         return 0;
1232 }
1233
1234 static struct sdw_master_ops sdw_intel_ops = {
1235         .read_prop = sdw_master_read_prop,
1236         .override_adr = sdw_dmi_override_adr,
1237         .xfer_msg = cdns_xfer_msg,
1238         .xfer_msg_defer = cdns_xfer_msg_defer,
1239         .reset_page_addr = cdns_reset_page_addr,
1240         .set_bus_conf = cdns_bus_conf,
1241         .pre_bank_switch = intel_pre_bank_switch,
1242         .post_bank_switch = intel_post_bank_switch,
1243 };
1244
1245 static int intel_init(struct sdw_intel *sdw)
1246 {
1247         bool clock_stop;
1248
1249         /* Initialize shim and controller */
1250         intel_link_power_up(sdw);
1251
1252         clock_stop = sdw_cdns_is_clock_stop(&sdw->cdns);
1253
1254         intel_shim_init(sdw, clock_stop);
1255
1256         return 0;
1257 }
1258
1259 /*
1260  * probe and init (aux_dev_id argument is required by function prototype but not used)
1261  */
1262 static int intel_link_probe(struct auxiliary_device *auxdev,
1263                             const struct auxiliary_device_id *aux_dev_id)
1264
1265 {
1266         struct device *dev = &auxdev->dev;
1267         struct sdw_intel_link_dev *ldev = auxiliary_dev_to_sdw_intel_link_dev(auxdev);
1268         struct sdw_intel *sdw;
1269         struct sdw_cdns *cdns;
1270         struct sdw_bus *bus;
1271         int ret;
1272
1273         sdw = devm_kzalloc(dev, sizeof(*sdw), GFP_KERNEL);
1274         if (!sdw)
1275                 return -ENOMEM;
1276
1277         cdns = &sdw->cdns;
1278         bus = &cdns->bus;
1279
1280         sdw->instance = auxdev->id;
1281         sdw->link_res = &ldev->link_res;
1282         cdns->dev = dev;
1283         cdns->registers = sdw->link_res->registers;
1284         cdns->instance = sdw->instance;
1285         cdns->msg_count = 0;
1286
1287         bus->link_id = auxdev->id;
1288
1289         sdw_cdns_probe(cdns);
1290
1291         /* Set property read ops */
1292         sdw_intel_ops.read_prop = intel_prop_read;
1293         bus->ops = &sdw_intel_ops;
1294
1295         /* set driver data, accessed by snd_soc_dai_get_drvdata() */
1296         dev_set_drvdata(dev, cdns);
1297
1298         /* use generic bandwidth allocation algorithm */
1299         sdw->cdns.bus.compute_params = sdw_compute_params;
1300
1301         /* avoid resuming from pm_runtime suspend if it's not required */
1302         dev_pm_set_driver_flags(dev, DPM_FLAG_SMART_SUSPEND);
1303
1304         ret = sdw_bus_master_add(bus, dev, dev->fwnode);
1305         if (ret) {
1306                 dev_err(dev, "sdw_bus_master_add fail: %d\n", ret);
1307                 return ret;
1308         }
1309
1310         if (bus->prop.hw_disabled)
1311                 dev_info(dev,
1312                          "SoundWire master %d is disabled, will be ignored\n",
1313                          bus->link_id);
1314         /*
1315          * Ignore BIOS err_threshold, it's a really bad idea when dealing
1316          * with multiple hardware synchronized links
1317          */
1318         bus->prop.err_threshold = 0;
1319
1320         return 0;
1321 }
1322
1323 int intel_link_startup(struct auxiliary_device *auxdev)
1324 {
1325         struct sdw_cdns_stream_config config;
1326         struct device *dev = &auxdev->dev;
1327         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1328         struct sdw_intel *sdw = cdns_to_intel(cdns);
1329         struct sdw_bus *bus = &cdns->bus;
1330         int link_flags;
1331         bool multi_link;
1332         u32 clock_stop_quirks;
1333         int ret;
1334
1335         if (bus->prop.hw_disabled) {
1336                 dev_info(dev,
1337                          "SoundWire master %d is disabled, ignoring\n",
1338                          sdw->instance);
1339                 return 0;
1340         }
1341
1342         link_flags = md_flags >> (bus->link_id * 8);
1343         multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);
1344         if (!multi_link) {
1345                 dev_dbg(dev, "Multi-link is disabled\n");
1346                 bus->multi_link = false;
1347         } else {
1348                 /*
1349                  * hardware-based synchronization is required regardless
1350                  * of the number of segments used by a stream: SSP-based
1351                  * synchronization is gated by gsync when the multi-master
1352                  * mode is set.
1353                  */
1354                 bus->multi_link = true;
1355                 bus->hw_sync_min_links = 1;
1356         }
1357
1358         /* Initialize shim, controller */
1359         ret = intel_init(sdw);
1360         if (ret)
1361                 goto err_init;
1362
1363         /* Read the PDI config and initialize cadence PDI */
1364         intel_pdi_init(sdw, &config);
1365         ret = sdw_cdns_pdi_init(cdns, config);
1366         if (ret)
1367                 goto err_init;
1368
1369         intel_pdi_ch_update(sdw);
1370
1371         ret = sdw_cdns_enable_interrupt(cdns, true);
1372         if (ret < 0) {
1373                 dev_err(dev, "cannot enable interrupts\n");
1374                 goto err_init;
1375         }
1376
1377         /*
1378          * follow recommended programming flows to avoid timeouts when
1379          * gsync is enabled
1380          */
1381         if (multi_link)
1382                 intel_shim_sync_arm(sdw);
1383
1384         ret = sdw_cdns_init(cdns);
1385         if (ret < 0) {
1386                 dev_err(dev, "unable to initialize Cadence IP\n");
1387                 goto err_interrupt;
1388         }
1389
1390         ret = sdw_cdns_exit_reset(cdns);
1391         if (ret < 0) {
1392                 dev_err(dev, "unable to exit bus reset sequence\n");
1393                 goto err_interrupt;
1394         }
1395
1396         if (multi_link) {
1397                 ret = intel_shim_sync_go(sdw);
1398                 if (ret < 0) {
1399                         dev_err(dev, "sync go failed: %d\n", ret);
1400                         goto err_interrupt;
1401                 }
1402         }
1403         sdw_cdns_check_self_clearing_bits(cdns, __func__,
1404                                           true, INTEL_MASTER_RESET_ITERATIONS);
1405
1406         /* Register DAIs */
1407         ret = intel_register_dai(sdw);
1408         if (ret) {
1409                 dev_err(dev, "DAI registration failed: %d\n", ret);
1410                 goto err_interrupt;
1411         }
1412
1413         intel_debugfs_init(sdw);
1414
1415         /* Enable runtime PM */
1416         if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME)) {
1417                 pm_runtime_set_autosuspend_delay(dev,
1418                                                  INTEL_MASTER_SUSPEND_DELAY_MS);
1419                 pm_runtime_use_autosuspend(dev);
1420                 pm_runtime_mark_last_busy(dev);
1421
1422                 pm_runtime_set_active(dev);
1423                 pm_runtime_enable(dev);
1424         }
1425
1426         clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1427         if (clock_stop_quirks & SDW_INTEL_CLK_STOP_NOT_ALLOWED) {
1428                 /*
1429                  * To keep the clock running we need to prevent
1430                  * pm_runtime suspend from happening by increasing the
1431                  * reference count.
1432                  * This quirk is specified by the parent PCI device in
1433                  * case of specific latency requirements. It will have
1434                  * no effect if pm_runtime is disabled by the user via
1435                  * a module parameter for testing purposes.
1436                  */
1437                 pm_runtime_get_noresume(dev);
1438         }
1439
1440         /*
1441          * The runtime PM status of Slave devices is "Unsupported"
1442          * until they report as ATTACHED. If they don't, e.g. because
1443          * there are no Slave devices populated or if the power-on is
1444          * delayed or dependent on a power switch, the Master will
1445          * remain active and prevent its parent from suspending.
1446          *
1447          * Conditionally force the pm_runtime core to re-evaluate the
1448          * Master status in the absence of any Slave activity. A quirk
1449          * is provided to e.g. deal with Slaves that may be powered on
1450          * with a delay. A more complete solution would require the
1451          * definition of Master properties.
1452          */
1453         if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE))
1454                 pm_runtime_idle(dev);
1455
1456         sdw->startup_done = true;
1457         return 0;
1458
1459 err_interrupt:
1460         sdw_cdns_enable_interrupt(cdns, false);
1461 err_init:
1462         return ret;
1463 }
1464
1465 static void intel_link_remove(struct auxiliary_device *auxdev)
1466 {
1467         struct device *dev = &auxdev->dev;
1468         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1469         struct sdw_intel *sdw = cdns_to_intel(cdns);
1470         struct sdw_bus *bus = &cdns->bus;
1471
1472         /*
1473          * Since pm_runtime is already disabled, we don't decrease
1474          * the refcount when the clock_stop_quirk is
1475          * SDW_INTEL_CLK_STOP_NOT_ALLOWED
1476          */
1477         if (!bus->prop.hw_disabled) {
1478                 intel_debugfs_exit(sdw);
1479                 sdw_cdns_enable_interrupt(cdns, false);
1480                 snd_soc_unregister_component(dev);
1481         }
1482         sdw_bus_master_delete(bus);
1483 }
1484
1485 int intel_link_process_wakeen_event(struct auxiliary_device *auxdev)
1486 {
1487         struct device *dev = &auxdev->dev;
1488         struct sdw_intel *sdw;
1489         struct sdw_bus *bus;
1490         void __iomem *shim;
1491         u16 wake_sts;
1492
1493         sdw = dev_get_drvdata(dev);
1494         bus = &sdw->cdns.bus;
1495
1496         if (bus->prop.hw_disabled || !sdw->startup_done) {
1497                 dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1498                         bus->link_id);
1499                 return 0;
1500         }
1501
1502         shim = sdw->link_res->shim;
1503         wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
1504
1505         if (!(wake_sts & BIT(sdw->instance)))
1506                 return 0;
1507
1508         /* disable WAKEEN interrupt ASAP to prevent interrupt flood */
1509         intel_shim_wake(sdw, false);
1510
1511         /*
1512          * resume the Master, which will generate a bus reset and result in
1513          * Slaves re-attaching and be re-enumerated. The SoundWire physical
1514          * device which generated the wake will trigger an interrupt, which
1515          * will in turn cause the corresponding Linux Slave device to be
1516          * resumed and the Slave codec driver to check the status.
1517          */
1518         pm_request_resume(dev);
1519
1520         return 0;
1521 }
1522
1523 /*
1524  * PM calls
1525  */
1526
1527 static int intel_resume_child_device(struct device *dev, void *data)
1528 {
1529         int ret;
1530         struct sdw_slave *slave = dev_to_sdw_dev(dev);
1531
1532         if (!slave->probed) {
1533                 dev_dbg(dev, "%s: skipping device, no probed driver\n", __func__);
1534                 return 0;
1535         }
1536         if (!slave->dev_num_sticky) {
1537                 dev_dbg(dev, "%s: skipping device, never detected on bus\n", __func__);
1538                 return 0;
1539         }
1540
1541         ret = pm_request_resume(dev);
1542         if (ret < 0)
1543                 dev_err(dev, "%s: pm_request_resume failed: %d\n", __func__, ret);
1544
1545         return ret;
1546 }
1547
1548 static int __maybe_unused intel_pm_prepare(struct device *dev)
1549 {
1550         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1551         struct sdw_intel *sdw = cdns_to_intel(cdns);
1552         struct sdw_bus *bus = &cdns->bus;
1553         u32 clock_stop_quirks;
1554         int ret = 0;
1555
1556         if (bus->prop.hw_disabled || !sdw->startup_done) {
1557                 dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1558                         bus->link_id);
1559                 return 0;
1560         }
1561
1562         clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1563
1564         if (pm_runtime_suspended(dev) &&
1565             pm_runtime_suspended(dev->parent) &&
1566             ((clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) ||
1567              !clock_stop_quirks)) {
1568                 /*
1569                  * if we've enabled clock stop, and the parent is suspended, the SHIM registers
1570                  * are not accessible and the shim wake cannot be disabled.
1571                  * The only solution is to resume the entire bus to full power
1572                  */
1573
1574                 /*
1575                  * If any operation in this block fails, we keep going since we don't want
1576                  * to prevent system suspend from happening and errors should be recoverable
1577                  * on resume.
1578                  */
1579
1580                 /*
1581                  * first resume the device for this link. This will also by construction
1582                  * resume the PCI parent device.
1583                  */
1584                 ret = pm_request_resume(dev);
1585                 if (ret < 0) {
1586                         dev_err(dev, "%s: pm_request_resume failed: %d\n", __func__, ret);
1587                         return 0;
1588                 }
1589
1590                 /*
1591                  * Continue resuming the entire bus (parent + child devices) to exit
1592                  * the clock stop mode. If there are no devices connected on this link
1593                  * this is a no-op.
1594                  * The resume to full power could have been implemented with a .prepare
1595                  * step in SoundWire codec drivers. This would however require a lot
1596                  * of code to handle an Intel-specific corner case. It is simpler in
1597                  * practice to add a loop at the link level.
1598                  */
1599                 ret = device_for_each_child(bus->dev, NULL, intel_resume_child_device);
1600
1601                 if (ret < 0)
1602                         dev_err(dev, "%s: intel_resume_child_device failed: %d\n", __func__, ret);
1603         }
1604
1605         return 0;
1606 }
1607
1608 static int __maybe_unused intel_suspend(struct device *dev)
1609 {
1610         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1611         struct sdw_intel *sdw = cdns_to_intel(cdns);
1612         struct sdw_bus *bus = &cdns->bus;
1613         u32 clock_stop_quirks;
1614         int ret;
1615
1616         if (bus->prop.hw_disabled || !sdw->startup_done) {
1617                 dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1618                         bus->link_id);
1619                 return 0;
1620         }
1621
1622         if (pm_runtime_suspended(dev)) {
1623                 dev_dbg(dev, "%s: pm_runtime status: suspended\n", __func__);
1624
1625                 clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1626
1627                 if ((clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) ||
1628                     !clock_stop_quirks) {
1629
1630                         if (pm_runtime_suspended(dev->parent)) {
1631                                 /*
1632                                  * paranoia check: this should not happen with the .prepare
1633                                  * resume to full power
1634                                  */
1635                                 dev_err(dev, "%s: invalid config: parent is suspended\n", __func__);
1636                         } else {
1637                                 intel_shim_wake(sdw, false);
1638                         }
1639                 }
1640
1641                 return 0;
1642         }
1643
1644         ret = sdw_cdns_enable_interrupt(cdns, false);
1645         if (ret < 0) {
1646                 dev_err(dev, "cannot disable interrupts on suspend\n");
1647                 return ret;
1648         }
1649
1650         ret = intel_link_power_down(sdw);
1651         if (ret) {
1652                 dev_err(dev, "Link power down failed: %d\n", ret);
1653                 return ret;
1654         }
1655
1656         intel_shim_wake(sdw, false);
1657
1658         return 0;
1659 }
1660
1661 static int __maybe_unused intel_suspend_runtime(struct device *dev)
1662 {
1663         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1664         struct sdw_intel *sdw = cdns_to_intel(cdns);
1665         struct sdw_bus *bus = &cdns->bus;
1666         u32 clock_stop_quirks;
1667         int ret;
1668
1669         if (bus->prop.hw_disabled || !sdw->startup_done) {
1670                 dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1671                         bus->link_id);
1672                 return 0;
1673         }
1674
1675         clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1676
1677         if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) {
1678
1679                 ret = sdw_cdns_enable_interrupt(cdns, false);
1680                 if (ret < 0) {
1681                         dev_err(dev, "cannot disable interrupts on suspend\n");
1682                         return ret;
1683                 }
1684
1685                 ret = intel_link_power_down(sdw);
1686                 if (ret) {
1687                         dev_err(dev, "Link power down failed: %d\n", ret);
1688                         return ret;
1689                 }
1690
1691                 intel_shim_wake(sdw, false);
1692
1693         } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET ||
1694                    !clock_stop_quirks) {
1695                 bool wake_enable = true;
1696
1697                 ret = sdw_cdns_clock_stop(cdns, true);
1698                 if (ret < 0) {
1699                         dev_err(dev, "cannot enable clock stop on suspend\n");
1700                         wake_enable = false;
1701                 }
1702
1703                 ret = sdw_cdns_enable_interrupt(cdns, false);
1704                 if (ret < 0) {
1705                         dev_err(dev, "cannot disable interrupts on suspend\n");
1706                         return ret;
1707                 }
1708
1709                 ret = intel_link_power_down(sdw);
1710                 if (ret) {
1711                         dev_err(dev, "Link power down failed: %d\n", ret);
1712                         return ret;
1713                 }
1714
1715                 intel_shim_wake(sdw, wake_enable);
1716         } else {
1717                 dev_err(dev, "%s clock_stop_quirks %x unsupported\n",
1718                         __func__, clock_stop_quirks);
1719                 ret = -EINVAL;
1720         }
1721
1722         return ret;
1723 }
1724
1725 static int __maybe_unused intel_resume(struct device *dev)
1726 {
1727         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1728         struct sdw_intel *sdw = cdns_to_intel(cdns);
1729         struct sdw_bus *bus = &cdns->bus;
1730         int link_flags;
1731         bool multi_link;
1732         int ret;
1733
1734         if (bus->prop.hw_disabled || !sdw->startup_done) {
1735                 dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1736                         bus->link_id);
1737                 return 0;
1738         }
1739
1740         link_flags = md_flags >> (bus->link_id * 8);
1741         multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);
1742
1743         if (pm_runtime_suspended(dev)) {
1744                 dev_dbg(dev, "%s: pm_runtime status was suspended, forcing active\n", __func__);
1745
1746                 /* follow required sequence from runtime_pm.rst */
1747                 pm_runtime_disable(dev);
1748                 pm_runtime_set_active(dev);
1749                 pm_runtime_mark_last_busy(dev);
1750                 pm_runtime_enable(dev);
1751
1752                 link_flags = md_flags >> (bus->link_id * 8);
1753
1754                 if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE))
1755                         pm_runtime_idle(dev);
1756         }
1757
1758         ret = intel_init(sdw);
1759         if (ret) {
1760                 dev_err(dev, "%s failed: %d\n", __func__, ret);
1761                 return ret;
1762         }
1763
1764         /*
1765          * make sure all Slaves are tagged as UNATTACHED and provide
1766          * reason for reinitialization
1767          */
1768         sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
1769
1770         ret = sdw_cdns_enable_interrupt(cdns, true);
1771         if (ret < 0) {
1772                 dev_err(dev, "cannot enable interrupts during resume\n");
1773                 return ret;
1774         }
1775
1776         /*
1777          * follow recommended programming flows to avoid timeouts when
1778          * gsync is enabled
1779          */
1780         if (multi_link)
1781                 intel_shim_sync_arm(sdw);
1782
1783         ret = sdw_cdns_init(&sdw->cdns);
1784         if (ret < 0) {
1785                 dev_err(dev, "unable to initialize Cadence IP during resume\n");
1786                 return ret;
1787         }
1788
1789         ret = sdw_cdns_exit_reset(cdns);
1790         if (ret < 0) {
1791                 dev_err(dev, "unable to exit bus reset sequence during resume\n");
1792                 return ret;
1793         }
1794
1795         if (multi_link) {
1796                 ret = intel_shim_sync_go(sdw);
1797                 if (ret < 0) {
1798                         dev_err(dev, "sync go failed during resume\n");
1799                         return ret;
1800                 }
1801         }
1802         sdw_cdns_check_self_clearing_bits(cdns, __func__,
1803                                           true, INTEL_MASTER_RESET_ITERATIONS);
1804
1805         /*
1806          * after system resume, the pm_runtime suspend() may kick in
1807          * during the enumeration, before any children device force the
1808          * master device to remain active.  Using pm_runtime_get()
1809          * routines is not really possible, since it'd prevent the
1810          * master from suspending.
1811          * A reasonable compromise is to update the pm_runtime
1812          * counters and delay the pm_runtime suspend by several
1813          * seconds, by when all enumeration should be complete.
1814          */
1815         pm_runtime_mark_last_busy(dev);
1816
1817         return ret;
1818 }
1819
1820 static int __maybe_unused intel_resume_runtime(struct device *dev)
1821 {
1822         struct sdw_cdns *cdns = dev_get_drvdata(dev);
1823         struct sdw_intel *sdw = cdns_to_intel(cdns);
1824         struct sdw_bus *bus = &cdns->bus;
1825         u32 clock_stop_quirks;
1826         bool clock_stop0;
1827         int link_flags;
1828         bool multi_link;
1829         int status;
1830         int ret;
1831
1832         if (bus->prop.hw_disabled || !sdw->startup_done) {
1833                 dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1834                         bus->link_id);
1835                 return 0;
1836         }
1837
1838         link_flags = md_flags >> (bus->link_id * 8);
1839         multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);
1840
1841         clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1842
1843         if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) {
1844                 ret = intel_init(sdw);
1845                 if (ret) {
1846                         dev_err(dev, "%s failed: %d\n", __func__, ret);
1847                         return ret;
1848                 }
1849
1850                 /*
1851                  * make sure all Slaves are tagged as UNATTACHED and provide
1852                  * reason for reinitialization
1853                  */
1854                 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
1855
1856                 ret = sdw_cdns_enable_interrupt(cdns, true);
1857                 if (ret < 0) {
1858                         dev_err(dev, "cannot enable interrupts during resume\n");
1859                         return ret;
1860                 }
1861
1862                 /*
1863                  * follow recommended programming flows to avoid
1864                  * timeouts when gsync is enabled
1865                  */
1866                 if (multi_link)
1867                         intel_shim_sync_arm(sdw);
1868
1869                 ret = sdw_cdns_init(&sdw->cdns);
1870                 if (ret < 0) {
1871                         dev_err(dev, "unable to initialize Cadence IP during resume\n");
1872                         return ret;
1873                 }
1874
1875                 ret = sdw_cdns_exit_reset(cdns);
1876                 if (ret < 0) {
1877                         dev_err(dev, "unable to exit bus reset sequence during resume\n");
1878                         return ret;
1879                 }
1880
1881                 if (multi_link) {
1882                         ret = intel_shim_sync_go(sdw);
1883                         if (ret < 0) {
1884                                 dev_err(dev, "sync go failed during resume\n");
1885                                 return ret;
1886                         }
1887                 }
1888                 sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime TEARDOWN",
1889                                                   true, INTEL_MASTER_RESET_ITERATIONS);
1890
1891         } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) {
1892                 ret = intel_init(sdw);
1893                 if (ret) {
1894                         dev_err(dev, "%s failed: %d\n", __func__, ret);
1895                         return ret;
1896                 }
1897
1898                 /*
1899                  * An exception condition occurs for the CLK_STOP_BUS_RESET
1900                  * case if one or more masters remain active. In this condition,
1901                  * all the masters are powered on for they are in the same power
1902                  * domain. Master can preserve its context for clock stop0, so
1903                  * there is no need to clear slave status and reset bus.
1904                  */
1905                 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);
1906
1907                 if (!clock_stop0) {
1908
1909                         /*
1910                          * make sure all Slaves are tagged as UNATTACHED and
1911                          * provide reason for reinitialization
1912                          */
1913
1914                         status = SDW_UNATTACH_REQUEST_MASTER_RESET;
1915                         sdw_clear_slave_status(bus, status);
1916
1917                         ret = sdw_cdns_enable_interrupt(cdns, true);
1918                         if (ret < 0) {
1919                                 dev_err(dev, "cannot enable interrupts during resume\n");
1920                                 return ret;
1921                         }
1922
1923                         /*
1924                          * follow recommended programming flows to avoid
1925                          * timeouts when gsync is enabled
1926                          */
1927                         if (multi_link)
1928                                 intel_shim_sync_arm(sdw);
1929
1930                         /*
1931                          * Re-initialize the IP since it was powered-off
1932                          */
1933                         sdw_cdns_init(&sdw->cdns);
1934
1935                 } else {
1936                         ret = sdw_cdns_enable_interrupt(cdns, true);
1937                         if (ret < 0) {
1938                                 dev_err(dev, "cannot enable interrupts during resume\n");
1939                                 return ret;
1940                         }
1941                 }
1942
1943                 ret = sdw_cdns_clock_restart(cdns, !clock_stop0);
1944                 if (ret < 0) {
1945                         dev_err(dev, "unable to restart clock during resume\n");
1946                         return ret;
1947                 }
1948
1949                 if (!clock_stop0) {
1950                         ret = sdw_cdns_exit_reset(cdns);
1951                         if (ret < 0) {
1952                                 dev_err(dev, "unable to exit bus reset sequence during resume\n");
1953                                 return ret;
1954                         }
1955
1956                         if (multi_link) {
1957                                 ret = intel_shim_sync_go(sdw);
1958                                 if (ret < 0) {
1959                                         dev_err(sdw->cdns.dev, "sync go failed during resume\n");
1960                                         return ret;
1961                                 }
1962                         }
1963                 }
1964                 sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime BUS_RESET",
1965                                                   true, INTEL_MASTER_RESET_ITERATIONS);
1966
1967         } else if (!clock_stop_quirks) {
1968
1969                 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);
1970                 if (!clock_stop0)
1971                         dev_err(dev, "%s invalid configuration, clock was not stopped", __func__);
1972
1973                 ret = intel_init(sdw);
1974                 if (ret) {
1975                         dev_err(dev, "%s failed: %d\n", __func__, ret);
1976                         return ret;
1977                 }
1978
1979                 ret = sdw_cdns_enable_interrupt(cdns, true);
1980                 if (ret < 0) {
1981                         dev_err(dev, "cannot enable interrupts during resume\n");
1982                         return ret;
1983                 }
1984
1985                 ret = sdw_cdns_clock_restart(cdns, false);
1986                 if (ret < 0) {
1987                         dev_err(dev, "unable to resume master during resume\n");
1988                         return ret;
1989                 }
1990
1991                 sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime no_quirks",
1992                                                   true, INTEL_MASTER_RESET_ITERATIONS);
1993         } else {
1994                 dev_err(dev, "%s clock_stop_quirks %x unsupported\n",
1995                         __func__, clock_stop_quirks);
1996                 ret = -EINVAL;
1997         }
1998
1999         return ret;
2000 }
2001
2002 static const struct dev_pm_ops intel_pm = {
2003         .prepare = intel_pm_prepare,
2004         SET_SYSTEM_SLEEP_PM_OPS(intel_suspend, intel_resume)
2005         SET_RUNTIME_PM_OPS(intel_suspend_runtime, intel_resume_runtime, NULL)
2006 };
2007
2008 static const struct auxiliary_device_id intel_link_id_table[] = {
2009         { .name = "soundwire_intel.link" },
2010         {},
2011 };
2012 MODULE_DEVICE_TABLE(auxiliary, intel_link_id_table);
2013
2014 static struct auxiliary_driver sdw_intel_drv = {
2015         .probe = intel_link_probe,
2016         .remove = intel_link_remove,
2017         .driver = {
2018                 /* auxiliary_driver_register() sets .name to be the modname */
2019                 .pm = &intel_pm,
2020         },
2021         .id_table = intel_link_id_table
2022 };
2023 module_auxiliary_driver(sdw_intel_drv);
2024
2025 MODULE_LICENSE("Dual BSD/GPL");
2026 MODULE_DESCRIPTION("Intel Soundwire Link Driver");