1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Samsung Electronics
4 * R. Chandrasekar <rcsekar@samsung.com>
7 #include <asm/arch/clk.h>
8 #include <asm/arch/cpu.h>
16 #include <asm/arch/sound.h>
18 #include "wm8994_registers.h"
20 /* defines for wm8994 system clock selection */
21 #define SEL_MCLK1 0x00
22 #define SEL_MCLK2 0x08
26 /* fll config to configure fll */
27 struct wm8994_fll_config {
29 int in; /* Input frequency in Hz */
30 int out; /* output frequency in Hz */
33 /* codec private data */
35 enum wm8994_type type; /* codec type of wolfson */
36 int revision; /* Revision */
37 int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */
38 int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */
39 int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */
40 struct wm8994_fll_config fll[2]; /* fll config to configure fll */
43 /* wm 8994 supported sampling rate values */
44 static unsigned int src_rate[] = {
45 8000, 11025, 12000, 16000, 22050, 24000,
46 32000, 44100, 48000, 88200, 96000
49 /* op clock divisions */
50 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
52 /* lr clock frame size ratio */
53 static int fs_ratios[] = {
54 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
57 /* bit clock divisors */
58 static int bclk_divs[] = {
59 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
60 640, 880, 960, 1280, 1760, 1920
63 static struct wm8994_priv g_wm8994_info;
64 static unsigned char g_wm8994_i2c_dev_addr;
65 static struct sound_codec_info g_codec_info;
68 * Initialise I2C for wm 8994
70 * @param bus no i2c bus number in which wm8994 is connected
72 static void wm8994_i2c_init(int bus_no)
74 i2c_set_bus_num(bus_no);
78 * Writes value to a device register through i2c
80 * @param priv Private data for driver
81 * @param reg reg number to be write
82 * @param data data to be writen to the above registor
84 * @return int value 1 for change, 0 for no change or negative error code.
86 static int wm8994_i2c_write(struct wm8994_priv *priv, unsigned int reg,
91 val[0] = (unsigned char)((data >> 8) & 0xff);
92 val[1] = (unsigned char)(data & 0xff);
93 debug("Write Addr : 0x%04X, Data : 0x%04X\n", reg, data);
95 return i2c_write(g_wm8994_i2c_dev_addr, reg, 2, val, 2);
99 * Read a value from a device register through i2c
101 * @param priv Private data for driver
102 * @param reg reg number to be read
103 * @param data address of read data to be stored
105 * @return int value 0 for success, -1 in case of error.
107 static unsigned int wm8994_i2c_read(struct wm8994_priv *priv, unsigned int reg,
108 unsigned short *data)
110 unsigned char val[2];
113 ret = i2c_read(g_wm8994_i2c_dev_addr, reg, 2, val, 2);
115 debug("%s: Error while reading register %#04x\n",
128 * update device register bits through i2c
130 * @param priv Private data for driver
131 * @param reg codec register
132 * @param mask register mask
133 * @param value new value
135 * @return int value 1 if change in the register value,
136 * 0 for no change or negative error code.
138 static int wm8994_bic_or(struct wm8994_priv *priv, unsigned int reg,
139 unsigned short mask, unsigned short value)
141 int change , ret = 0;
142 unsigned short old, new;
144 if (wm8994_i2c_read(priv, reg, &old) != 0)
146 new = (old & ~mask) | (value & mask);
147 change = (old != new) ? 1 : 0;
149 ret = wm8994_i2c_write(priv, reg, new);
157 * Sets i2s set format
159 * @param priv wm8994 information
160 * @param aif_id Interface ID
161 * @param fmt i2S format
163 * @return -1 for error and 0 Success.
165 static int wm8994_set_fmt(struct wm8994_priv *priv, int aif_id, uint fmt)
176 ms_reg = WM8994_AIF1_MASTER_SLAVE;
177 aif_reg = WM8994_AIF1_CONTROL_1;
178 aif_clk = WM8994_AIF1_CLOCKING_1;
181 ms_reg = WM8994_AIF2_MASTER_SLAVE;
182 aif_reg = WM8994_AIF2_CONTROL_1;
183 aif_clk = WM8994_AIF2_CLOCKING_1;
186 debug("%s: Invalid audio interface selection\n", __func__);
190 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
191 case SND_SOC_DAIFMT_CBS_CFS:
193 case SND_SOC_DAIFMT_CBM_CFM:
194 ms = WM8994_AIF1_MSTR;
197 debug("%s: Invalid i2s master selection\n", __func__);
201 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
202 case SND_SOC_DAIFMT_DSP_B:
203 aif |= WM8994_AIF1_LRCLK_INV;
204 case SND_SOC_DAIFMT_DSP_A:
207 case SND_SOC_DAIFMT_I2S:
210 case SND_SOC_DAIFMT_RIGHT_J:
212 case SND_SOC_DAIFMT_LEFT_J:
216 debug("%s: Invalid i2s format selection\n", __func__);
220 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
221 case SND_SOC_DAIFMT_DSP_A:
222 case SND_SOC_DAIFMT_DSP_B:
223 /* frame inversion not valid for DSP modes */
224 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
225 case SND_SOC_DAIFMT_NB_NF:
227 case SND_SOC_DAIFMT_IB_NF:
228 aif |= WM8994_AIF1_BCLK_INV;
231 debug("%s: Invalid i2s frame inverse selection\n",
237 case SND_SOC_DAIFMT_I2S:
238 case SND_SOC_DAIFMT_RIGHT_J:
239 case SND_SOC_DAIFMT_LEFT_J:
240 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
241 case SND_SOC_DAIFMT_NB_NF:
243 case SND_SOC_DAIFMT_IB_IF:
244 aif |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
246 case SND_SOC_DAIFMT_IB_NF:
247 aif |= WM8994_AIF1_BCLK_INV;
249 case SND_SOC_DAIFMT_NB_IF:
250 aif |= WM8994_AIF1_LRCLK_INV;
253 debug("%s: Invalid i2s clock polarity selection\n",
259 debug("%s: Invalid i2s format selection\n", __func__);
263 error = wm8994_bic_or(priv, aif_reg, WM8994_AIF1_BCLK_INV |
264 WM8994_AIF1_LRCLK_INV_MASK |
265 WM8994_AIF1_FMT_MASK, aif);
267 error |= wm8994_bic_or(priv, ms_reg, WM8994_AIF1_MSTR_MASK, ms);
268 error |= wm8994_bic_or(priv, aif_clk, WM8994_AIF1CLK_ENA_MASK,
271 debug("%s: codec register access error\n", __func__);
279 * Sets hw params FOR WM8994
281 * @param priv wm8994 information pointer
282 * @param aif_id Audio interface ID
283 * @param sampling_rate Sampling rate
284 * @param bits_per_sample Bits per sample
285 * @param Channels Channels in the given audio input
287 * @return -1 for error and 0 Success.
289 static int wm8994_hw_params(struct wm8994_priv *priv, int aif_id,
290 uint sampling_rate, uint bits_per_sample,
302 int i, cur_val, best_val, bclk_rate, best;
303 unsigned short reg_data;
308 aif1_reg = WM8994_AIF1_CONTROL_1;
309 aif2_reg = WM8994_AIF1_CONTROL_2;
310 bclk_reg = WM8994_AIF1_BCLK;
311 rate_reg = WM8994_AIF1_RATE;
314 aif1_reg = WM8994_AIF2_CONTROL_1;
315 aif2_reg = WM8994_AIF2_CONTROL_2;
316 bclk_reg = WM8994_AIF2_BCLK;
317 rate_reg = WM8994_AIF2_RATE;
323 bclk_rate = sampling_rate * 32;
324 switch (bits_per_sample) {
344 /* Try to find an appropriate sample rate; look for an exact match. */
345 for (i = 0; i < ARRAY_SIZE(src_rate); i++)
346 if (src_rate[i] == sampling_rate)
349 if (i == ARRAY_SIZE(src_rate)) {
350 debug("%s: Could not get the best matching samplingrate\n",
355 rate_val |= i << WM8994_AIF1_SR_SHIFT;
357 /* AIFCLK/fs ratio; look for a close match in either direction */
359 best_val = abs((fs_ratios[0] * sampling_rate) - priv->aifclk[id]);
361 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
362 cur_val = abs(fs_ratios[i] * sampling_rate - priv->aifclk[id]);
363 if (cur_val >= best_val)
372 * We may not get quite the right frequency if using
373 * approximate clocks so look for the closest match that is
374 * higher than the target (we need to ensure that there enough
375 * BCLKs to clock out the samples).
378 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
379 cur_val = (priv->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
380 if (cur_val < 0) /* BCLK table is sorted */
385 if (i == ARRAY_SIZE(bclk_divs)) {
386 debug("%s: Could not get the best matching bclk division\n",
391 bclk_rate = priv->aifclk[id] * 10 / bclk_divs[best];
392 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
394 if (wm8994_i2c_read(priv, aif1_reg, ®_data) != 0) {
395 debug("%s: AIF1 register read Failed\n", __func__);
399 if ((channels == 1) && ((reg_data & 0x18) == 0x18))
400 aif2 |= WM8994_AIF1_MONO;
402 if (priv->aifclk[id] == 0) {
403 debug("%s:Audio interface clock not set\n", __func__);
407 ret = wm8994_bic_or(priv, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
408 ret |= wm8994_bic_or(priv, aif2_reg, WM8994_AIF1_MONO, aif2);
409 ret |= wm8994_bic_or(priv, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK,
411 ret |= wm8994_bic_or(priv, rate_reg, WM8994_AIF1_SR_MASK |
412 WM8994_AIF1CLK_RATE_MASK, rate_val);
414 debug("rate vale = %x , bclk val= %x\n", rate_val, bclk);
417 debug("%s: codec register access error\n", __func__);
425 * Configures Audio interface Clock
427 * @param priv wm8994 information pointer
428 * @param aif Audio Interface ID
430 * @return -1 for error and 0 Success.
432 static int configure_aif_clock(struct wm8994_priv *priv, int aif)
439 /* AIF(1/0) register adress offset calculated */
445 switch (priv->sysclk[aif - 1]) {
446 case WM8994_SYSCLK_MCLK1:
448 rate = priv->mclk[0];
451 case WM8994_SYSCLK_MCLK2:
453 rate = priv->mclk[1];
456 case WM8994_SYSCLK_FLL1:
458 rate = priv->fll[0].out;
461 case WM8994_SYSCLK_FLL2:
463 rate = priv->fll[1].out;
467 debug("%s: Invalid input clock selection [%d]\n",
468 __func__, priv->sysclk[aif - 1]);
472 /* if input clock frequenct is more than 135Mhz then divide */
473 if (rate >= WM8994_MAX_INPUT_CLK_FREQ) {
475 reg1 |= WM8994_AIF1CLK_DIV;
478 priv->aifclk[aif - 1] = rate;
480 ret = wm8994_bic_or(priv, WM8994_AIF1_CLOCKING_1 + offset,
481 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
484 if (aif == WM8994_AIF1)
485 ret |= wm8994_bic_or(priv, WM8994_CLOCKING_1,
486 WM8994_AIF1DSPCLK_ENA_MASK | WM8994_SYSDSPCLK_ENA_MASK,
487 WM8994_AIF1DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
488 else if (aif == WM8994_AIF2)
489 ret |= wm8994_bic_or(priv, WM8994_CLOCKING_1,
490 WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK |
491 WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC |
492 WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
495 debug("%s: codec register access error\n", __func__);
503 * Configures Audio interface for the given frequency
505 * @param priv wm8994 information
506 * @param aif_id Audio Interface
507 * @param clk_id Input Clock ID
508 * @param freq Sampling frequency in Hz
510 * @return -1 for error and 0 success.
512 static int wm8994_set_sysclk(struct wm8994_priv *priv, int aif_id, int clk_id,
518 priv->sysclk[aif_id - 1] = clk_id;
521 case WM8994_SYSCLK_MCLK1:
522 priv->mclk[0] = freq;
524 ret = wm8994_bic_or(priv, WM8994_AIF1_CLOCKING_2,
525 WM8994_AIF2DAC_DIV_MASK, 0);
529 case WM8994_SYSCLK_MCLK2:
530 /* TODO: Set GPIO AF */
531 priv->mclk[1] = freq;
534 case WM8994_SYSCLK_FLL1:
535 case WM8994_SYSCLK_FLL2:
538 case WM8994_SYSCLK_OPCLK:
540 * Special case - a division (times 10) is given and
541 * no effect on main clocking.
544 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
545 if (opclk_divs[i] == freq)
547 if (i == ARRAY_SIZE(opclk_divs)) {
548 debug("%s frequency divisor not found\n",
552 ret = wm8994_bic_or(priv, WM8994_CLOCKING_2,
553 WM8994_OPCLK_DIV_MASK, i);
554 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_2,
558 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_2,
559 WM8994_OPCLK_ENA, 0);
563 debug("%s Invalid input clock selection [%d]\n",
568 ret |= configure_aif_clock(priv, aif_id);
571 debug("%s: codec register access error\n", __func__);
579 * Initializes Volume for AIF2 to HP path
581 * @param priv wm8994 information
582 * @returns -1 for error and 0 Success.
585 static int wm8994_init_volume_aif2_dac1(struct wm8994_priv *priv)
590 ret = wm8994_bic_or(priv, WM8994_AIF2_DAC_FILTERS_1,
591 WM8994_AIF2DAC_MUTE_MASK, 0);
594 ret |= wm8994_bic_or(priv, WM8994_AIF2_DAC_LEFT_VOLUME,
595 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK,
596 WM8994_AIF2DAC_VU | 0xff);
598 ret |= wm8994_bic_or(priv, WM8994_AIF2_DAC_RIGHT_VOLUME,
599 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK,
600 WM8994_AIF2DAC_VU | 0xff);
603 ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_VOLUME,
604 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
605 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
607 ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_VOLUME,
608 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
609 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
610 /* Head Phone Volume */
611 ret |= wm8994_i2c_write(priv, WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
612 ret |= wm8994_i2c_write(priv, WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
615 debug("%s: codec register access error\n", __func__);
623 * Initializes Volume for AIF1 to HP path
625 * @param priv wm8994 information
626 * @returns -1 for error and 0 Success.
629 static int wm8994_init_volume_aif1_dac1(struct wm8994_priv *priv)
634 ret |= wm8994_i2c_write(priv, WM8994_AIF1_DAC_FILTERS_1, 0x0000);
636 ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_VOLUME,
637 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
638 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
640 ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_VOLUME,
641 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
642 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
643 /* Head Phone Volume */
644 ret |= wm8994_i2c_write(priv, WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
645 ret |= wm8994_i2c_write(priv, WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
648 debug("%s: codec register access error\n", __func__);
656 * Intialise wm8994 codec device
658 * @param priv wm8994 information
660 * @returns -1 for error and 0 Success.
662 static int wm8994_device_init(struct wm8994_priv *priv,
663 enum en_audio_interface aif_id)
666 unsigned short reg_data;
669 wm8994_i2c_write(priv, WM8994_SOFTWARE_RESET, WM8994_SW_RESET);
671 ret = wm8994_i2c_read(priv, WM8994_SOFTWARE_RESET, ®_data);
673 debug("Failed to read ID register\n");
677 if (reg_data == WM8994_ID) {
679 debug("Device registered as type %d\n", priv->type);
682 debug("Device is not a WM8994, ID is %x\n", ret);
687 ret = wm8994_i2c_read(priv, WM8994_CHIP_REVISION, ®_data);
689 debug("Failed to read revision register: %d\n", ret);
692 priv->revision = reg_data;
693 debug("%s revision %c\n", devname, 'A' + priv->revision);
696 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
697 WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3);
699 /* Charge Pump Enable */
700 ret |= wm8994_bic_or(priv, WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK,
703 /* Head Phone Power Enable */
704 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
705 WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA);
707 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
708 WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA);
710 if (aif_id == WM8994_AIF1) {
711 ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_2,
712 WM8994_TSHUT_ENA | WM8994_MIXINL_ENA |
713 WM8994_MIXINR_ENA | WM8994_IN2L_ENA |
716 ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_4,
717 WM8994_ADCL_ENA | WM8994_ADCR_ENA |
718 WM8994_AIF1ADC1R_ENA |
719 WM8994_AIF1ADC1L_ENA);
721 /* Power enable for AIF1 and DAC1 */
722 ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_5,
723 WM8994_AIF1DACL_ENA |
724 WM8994_AIF1DACR_ENA |
725 WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
726 } else if (aif_id == WM8994_AIF2) {
727 /* Power enable for AIF2 and DAC1 */
728 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_5,
729 WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
730 WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
731 WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA |
732 WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
734 /* Head Phone Initialisation */
735 ret |= wm8994_bic_or(priv, WM8994_ANALOGUE_HP_1,
736 WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK,
737 WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY);
739 ret |= wm8994_bic_or(priv, WM8994_DC_SERVO_1,
740 WM8994_DCS_ENA_CHAN_0_MASK |
741 WM8994_DCS_ENA_CHAN_1_MASK , WM8994_DCS_ENA_CHAN_0 |
742 WM8994_DCS_ENA_CHAN_1);
744 ret |= wm8994_bic_or(priv, WM8994_ANALOGUE_HP_1,
745 WM8994_HPOUT1L_DLY_MASK |
746 WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1L_OUTP_MASK |
747 WM8994_HPOUT1R_OUTP_MASK |
748 WM8994_HPOUT1L_RMV_SHORT_MASK |
749 WM8994_HPOUT1R_RMV_SHORT_MASK, WM8994_HPOUT1L_DLY |
750 WM8994_HPOUT1R_DLY | WM8994_HPOUT1L_OUTP |
751 WM8994_HPOUT1R_OUTP | WM8994_HPOUT1L_RMV_SHORT |
752 WM8994_HPOUT1R_RMV_SHORT);
754 /* MIXER Config DAC1 to HP */
755 ret |= wm8994_bic_or(priv, WM8994_OUTPUT_MIXER_1,
756 WM8994_DAC1L_TO_HPOUT1L_MASK,
757 WM8994_DAC1L_TO_HPOUT1L);
759 ret |= wm8994_bic_or(priv, WM8994_OUTPUT_MIXER_2,
760 WM8994_DAC1R_TO_HPOUT1R_MASK,
761 WM8994_DAC1R_TO_HPOUT1R);
763 if (aif_id == WM8994_AIF1) {
764 /* Routing AIF1 to DAC1 */
765 ret |= wm8994_i2c_write(priv, WM8994_DAC1_LEFT_MIXER_ROUTING,
766 WM8994_AIF1DAC1L_TO_DAC1L);
768 ret |= wm8994_i2c_write(priv, WM8994_DAC1_RIGHT_MIXER_ROUTING,
769 WM8994_AIF1DAC1R_TO_DAC1R);
771 /* GPIO Settings for AIF1 */
772 ret |= wm8994_i2c_write(priv, WM8994_GPIO_1,
773 WM8994_GPIO_DIR_OUTPUT |
774 WM8994_GPIO_FUNCTION_I2S_CLK |
775 WM8994_GPIO_INPUT_DEBOUNCE);
777 ret |= wm8994_init_volume_aif1_dac1(priv);
778 } else if (aif_id == WM8994_AIF2) {
779 /* Routing AIF2 to DAC1 */
780 ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_MIXER_ROUTING,
781 WM8994_AIF2DACL_TO_DAC1L_MASK,
782 WM8994_AIF2DACL_TO_DAC1L);
784 ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_MIXER_ROUTING,
785 WM8994_AIF2DACR_TO_DAC1R_MASK,
786 WM8994_AIF2DACR_TO_DAC1R);
788 /* GPIO Settings for AIF2 */
790 ret |= wm8994_bic_or(priv, WM8994_GPIO_3, WM8994_GPIO_DIR_MASK |
791 WM8994_GPIO_FUNCTION_MASK,
792 WM8994_GPIO_DIR_OUTPUT);
795 ret |= wm8994_bic_or(priv, WM8994_GPIO_4, WM8994_GPIO_DIR_MASK |
796 WM8994_GPIO_FUNCTION_MASK,
797 WM8994_GPIO_DIR_OUTPUT);
800 ret |= wm8994_bic_or(priv, WM8994_GPIO_5, WM8994_GPIO_DIR_MASK |
801 WM8994_GPIO_FUNCTION_MASK,
802 WM8994_GPIO_DIR_OUTPUT);
804 ret |= wm8994_init_volume_aif2_dac1(priv);
810 debug("%s: Codec chip init ok\n", __func__);
813 debug("%s: Codec chip init error\n", __func__);
818 * Gets fdt values for wm8994 config parameters
820 * @param pcodec_info codec information structure
821 * @param blob FDT blob
822 * @return int value, 0 for success
824 static int get_codec_values(struct sound_codec_info *pcodec_info,
828 enum fdt_compat_id compat;
832 /* Get the node from FDT for codec */
833 node = fdtdec_next_compatible(blob, 0, COMPAT_WOLFSON_WM8994_CODEC);
835 debug("EXYNOS_SOUND: No node for codec in device tree\n");
836 debug("node = %d\n", node);
840 parent = fdt_parent_offset(blob, node);
842 debug("%s: Cannot find node parent\n", __func__);
846 compat = fdtdec_lookup(blob, parent);
848 case COMPAT_SAMSUNG_S3C2440_I2C:
849 pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent);
850 error |= pcodec_info->i2c_bus;
851 debug("i2c bus = %d\n", pcodec_info->i2c_bus);
852 pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node,
854 error |= pcodec_info->i2c_dev_addr;
855 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
858 debug("%s: Unknown compat id %d\n", __func__, compat);
863 debug("fail to get wm8994 codec node properties\n");
870 static int _wm8994_init(struct wm8994_priv *priv,
871 enum en_audio_interface aif_id, int sampling_rate,
872 int mclk_freq, int bits_per_sample,
873 unsigned int channels)
877 ret = wm8994_device_init(priv, aif_id);
879 debug("%s: wm8994 codec chip init failed\n", __func__);
883 ret = wm8994_set_sysclk(priv, aif_id, WM8994_SYSCLK_MCLK1, mclk_freq);
885 debug("%s: wm8994 codec set sys clock failed\n", __func__);
889 ret = wm8994_hw_params(priv, aif_id, sampling_rate, bits_per_sample,
893 ret = wm8994_set_fmt(priv, aif_id, SND_SOC_DAIFMT_I2S |
894 SND_SOC_DAIFMT_NB_NF |
895 SND_SOC_DAIFMT_CBS_CFS);
901 /* WM8994 Device Initialisation */
902 int wm8994_init(const void *blob, enum en_audio_interface aif_id,
903 int sampling_rate, int mclk_freq, int bits_per_sample,
904 unsigned int channels)
906 struct sound_codec_info *pcodec_info = &g_codec_info;
908 /* Get the codec Values */
909 if (get_codec_values(pcodec_info, blob) < 0) {
910 debug("FDT Codec values failed\n");
914 /* shift the device address by 1 for 7 bit addressing */
915 g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr;
916 wm8994_i2c_init(pcodec_info->i2c_bus);
918 return _wm8994_init(&g_wm8994_info, aif_id, sampling_rate, mclk_freq,
919 bits_per_sample, channels);