1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * rt5677.h -- RealTek ALC5677 ALSA SoC Audio driver
5 * Copyright 2013 Realtek Semiconductor Corp.
6 * Author: Oder Chiou <oder_chiou@realtek.com>
8 * Based on the file by the same name in Chromium OS dc
11 #ifndef __DRIVERS_SOUND_RT5677_H__
12 #define __DRIVERS_SOUND_RT5677_H__
15 * RT5677 Registers Definition
19 #define RT5677_RESET 0x00
20 #define RT5677_VENDOR_ID 0xfd
21 #define RT5677_VENDOR_ID1 0xfe
22 #define RT5677_VENDOR_ID2 0xff
24 #define RT5677_REG_CNT (RT5677_VENDOR_ID2 + 1)
25 #define RT5677_PR_REG_CNT 255
28 #define RT5677_LOUT1 0x01
30 #define RT5677_IN1 0x03
31 #define RT5677_MICBIAS 0x04
33 #define RT5677_SLIMBUS_PARAM 0x07
34 #define RT5677_SLIMBUS_RX 0x08
35 #define RT5677_SLIMBUS_CTRL 0x09
37 #define RT5677_SIDETONE_CTRL 0x13
39 #define RT5677_ANA_DAC1_2_3_SRC 0x15
40 #define RT5677_IF_DSP_DAC3_4_MIXER 0x16
41 #define RT5677_DAC4_DIG_VOL 0x17
42 #define RT5677_DAC3_DIG_VOL 0x18
43 #define RT5677_DAC1_DIG_VOL 0x19
44 #define RT5677_DAC2_DIG_VOL 0x1a
45 #define RT5677_IF_DSP_DAC2_MIXER 0x1b
46 #define RT5677_STO1_ADC_DIG_VOL 0x1c
47 #define RT5677_MONO_ADC_DIG_VOL 0x1d
48 #define RT5677_STO1_2_ADC_BST 0x1e
49 #define RT5677_STO2_ADC_DIG_VOL 0x1f
51 #define RT5677_ADC_BST_CTRL2 0x20
52 #define RT5677_STO3_4_ADC_BST 0x21
53 #define RT5677_STO3_ADC_DIG_VOL 0x22
54 #define RT5677_STO4_ADC_DIG_VOL 0x23
55 #define RT5677_STO4_ADC_MIXER 0x24
56 #define RT5677_STO3_ADC_MIXER 0x25
57 #define RT5677_STO2_ADC_MIXER 0x26
58 #define RT5677_STO1_ADC_MIXER 0x27
59 #define RT5677_MONO_ADC_MIXER 0x28
60 #define RT5677_ADC_IF_DSP_DAC1_MIXER 0x29
61 #define RT5677_STO1_DAC_MIXER 0x2a
62 #define RT5677_MONO_DAC_MIXER 0x2b
63 #define RT5677_DD1_MIXER 0x2c
64 #define RT5677_DD2_MIXER 0x2d
65 #define RT5677_IF3_DATA 0x2f
66 #define RT5677_IF4_DATA 0x30
68 #define RT5677_PDM_OUT_CTRL 0x31
69 #define RT5677_PDM_DATA_CTRL1 0x32
70 #define RT5677_PDM_DATA_CTRL2 0x33
71 #define RT5677_PDM1_DATA_CTRL2 0x34
72 #define RT5677_PDM1_DATA_CTRL3 0x35
73 #define RT5677_PDM1_DATA_CTRL4 0x36
74 #define RT5677_PDM2_DATA_CTRL2 0x37
75 #define RT5677_PDM2_DATA_CTRL3 0x38
76 #define RT5677_PDM2_DATA_CTRL4 0x39
78 #define RT5677_TDM1_CTRL1 0x3b
79 #define RT5677_TDM1_CTRL2 0x3c
80 #define RT5677_TDM1_CTRL3 0x3d
81 #define RT5677_TDM1_CTRL4 0x3e
82 #define RT5677_TDM1_CTRL5 0x3f
83 #define RT5677_TDM2_CTRL1 0x40
84 #define RT5677_TDM2_CTRL2 0x41
85 #define RT5677_TDM2_CTRL3 0x42
86 #define RT5677_TDM2_CTRL4 0x43
87 #define RT5677_TDM2_CTRL5 0x44
89 #define RT5677_I2C_MASTER_CTRL1 0x47
90 #define RT5677_I2C_MASTER_CTRL2 0x48
91 #define RT5677_I2C_MASTER_CTRL3 0x49
92 #define RT5677_I2C_MASTER_CTRL4 0x4a
93 #define RT5677_I2C_MASTER_CTRL5 0x4b
94 #define RT5677_I2C_MASTER_CTRL6 0x4c
95 #define RT5677_I2C_MASTER_CTRL7 0x4d
96 #define RT5677_I2C_MASTER_CTRL8 0x4e
98 #define RT5677_DMIC_CTRL1 0x50
99 #define RT5677_DMIC_CTRL2 0x51
100 /* Haptic Generator */
101 #define RT5677_HAP_GENE_CTRL1 0x56
102 #define RT5677_HAP_GENE_CTRL2 0x57
103 #define RT5677_HAP_GENE_CTRL3 0x58
104 #define RT5677_HAP_GENE_CTRL4 0x59
105 #define RT5677_HAP_GENE_CTRL5 0x5a
106 #define RT5677_HAP_GENE_CTRL6 0x5b
107 #define RT5677_HAP_GENE_CTRL7 0x5c
108 #define RT5677_HAP_GENE_CTRL8 0x5d
109 #define RT5677_HAP_GENE_CTRL9 0x5e
110 #define RT5677_HAP_GENE_CTRL10 0x5f
112 #define RT5677_PWR_DIG1 0x61
113 #define RT5677_PWR_DIG2 0x62
114 #define RT5677_PWR_ANLG1 0x63
115 #define RT5677_PWR_ANLG2 0x64
116 #define RT5677_PWR_DSP1 0x65
117 #define RT5677_PWR_DSP_ST 0x66
118 #define RT5677_PWR_DSP2 0x67
119 #define RT5677_ADC_DAC_HPF_CTRL1 0x68
120 /* Private Register Control */
121 #define RT5677_PRIV_INDEX 0x6a
122 #define RT5677_PRIV_DATA 0x6c
123 /* Format - ADC/DAC */
124 #define RT5677_I2S4_SDP 0x6f
125 #define RT5677_I2S1_SDP 0x70
126 #define RT5677_I2S2_SDP 0x71
127 #define RT5677_I2S3_SDP 0x72
128 #define RT5677_CLK_TREE_CTRL1 0x73
129 #define RT5677_CLK_TREE_CTRL2 0x74
130 #define RT5677_CLK_TREE_CTRL3 0x75
131 /* Function - Analog */
132 #define RT5677_PLL1_CTRL1 0x7a
133 #define RT5677_PLL1_CTRL2 0x7b
134 #define RT5677_PLL2_CTRL1 0x7c
135 #define RT5677_PLL2_CTRL2 0x7d
136 #define RT5677_GLB_CLK1 0x80
137 #define RT5677_GLB_CLK2 0x81
138 #define RT5677_ASRC_1 0x83
139 #define RT5677_ASRC_2 0x84
140 #define RT5677_ASRC_3 0x85
141 #define RT5677_ASRC_4 0x86
142 #define RT5677_ASRC_5 0x87
143 #define RT5677_ASRC_6 0x88
144 #define RT5677_ASRC_7 0x89
145 #define RT5677_ASRC_8 0x8a
146 #define RT5677_ASRC_9 0x8b
147 #define RT5677_ASRC_10 0x8c
148 #define RT5677_ASRC_11 0x8d
149 #define RT5677_ASRC_12 0x8e
150 #define RT5677_ASRC_13 0x8f
151 #define RT5677_ASRC_14 0x90
152 #define RT5677_ASRC_15 0x91
153 #define RT5677_ASRC_16 0x92
154 #define RT5677_ASRC_17 0x93
155 #define RT5677_ASRC_18 0x94
156 #define RT5677_ASRC_19 0x95
157 #define RT5677_ASRC_20 0x97
158 #define RT5677_ASRC_21 0x98
159 #define RT5677_ASRC_22 0x99
160 #define RT5677_ASRC_23 0x9a
161 #define RT5677_VAD_CTRL1 0x9c
162 #define RT5677_VAD_CTRL2 0x9d
163 #define RT5677_VAD_CTRL3 0x9e
164 #define RT5677_VAD_CTRL4 0x9f
165 #define RT5677_VAD_CTRL5 0xa0
166 /* Function - Digital */
167 #define RT5677_DSP_INB_CTRL1 0xa3
168 #define RT5677_DSP_INB_CTRL2 0xa4
169 #define RT5677_DSP_IN_OUTB_CTRL 0xa5
170 #define RT5677_DSP_OUTB0_1_DIG_VOL 0xa6
171 #define RT5677_DSP_OUTB2_3_DIG_VOL 0xa7
172 #define RT5677_DSP_OUTB4_5_DIG_VOL 0xa8
173 #define RT5677_DSP_OUTB6_7_DIG_VOL 0xa9
174 #define RT5677_ADC_EQ_CTRL1 0xae
175 #define RT5677_ADC_EQ_CTRL2 0xaf
176 #define RT5677_EQ_CTRL1 0xb0
177 #define RT5677_EQ_CTRL2 0xb1
178 #define RT5677_EQ_CTRL3 0xb2
179 #define RT5677_SOFT_VOL_ZERO_CROSS1 0xb3
180 #define RT5677_JD_CTRL1 0xb5
181 #define RT5677_JD_CTRL2 0xb6
182 #define RT5677_JD_CTRL3 0xb8
183 #define RT5677_IRQ_CTRL1 0xbd
184 #define RT5677_IRQ_CTRL2 0xbe
185 #define RT5677_GPIO_ST 0xbf
186 #define RT5677_GPIO_CTRL1 0xc0
187 #define RT5677_GPIO_CTRL2 0xc1
188 #define RT5677_GPIO_CTRL3 0xc2
189 #define RT5677_STO1_ADC_HI_FILTER1 0xc5
190 #define RT5677_STO1_ADC_HI_FILTER2 0xc6
191 #define RT5677_MONO_ADC_HI_FILTER1 0xc7
192 #define RT5677_MONO_ADC_HI_FILTER2 0xc8
193 #define RT5677_STO2_ADC_HI_FILTER1 0xc9
194 #define RT5677_STO2_ADC_HI_FILTER2 0xca
195 #define RT5677_STO3_ADC_HI_FILTER1 0xcb
196 #define RT5677_STO3_ADC_HI_FILTER2 0xcc
197 #define RT5677_STO4_ADC_HI_FILTER1 0xcd
198 #define RT5677_STO4_ADC_HI_FILTER2 0xce
199 #define RT5677_MB_DRC_CTRL1 0xd0
200 #define RT5677_DRC1_CTRL1 0xd2
201 #define RT5677_DRC1_CTRL2 0xd3
202 #define RT5677_DRC1_CTRL3 0xd4
203 #define RT5677_DRC1_CTRL4 0xd5
204 #define RT5677_DRC1_CTRL5 0xd6
205 #define RT5677_DRC1_CTRL6 0xd7
206 #define RT5677_DRC2_CTRL1 0xd8
207 #define RT5677_DRC2_CTRL2 0xd9
208 #define RT5677_DRC2_CTRL3 0xda
209 #define RT5677_DRC2_CTRL4 0xdb
210 #define RT5677_DRC2_CTRL5 0xdc
211 #define RT5677_DRC2_CTRL6 0xdd
212 #define RT5677_DRC1_HL_CTRL1 0xde
213 #define RT5677_DRC1_HL_CTRL2 0xdf
214 #define RT5677_DRC2_HL_CTRL1 0xe0
215 #define RT5677_DRC2_HL_CTRL2 0xe1
216 #define RT5677_DSP_INB1_SRC_CTRL1 0xe3
217 #define RT5677_DSP_INB1_SRC_CTRL2 0xe4
218 #define RT5677_DSP_INB1_SRC_CTRL3 0xe5
219 #define RT5677_DSP_INB1_SRC_CTRL4 0xe6
220 #define RT5677_DSP_INB2_SRC_CTRL1 0xe7
221 #define RT5677_DSP_INB2_SRC_CTRL2 0xe8
222 #define RT5677_DSP_INB2_SRC_CTRL3 0xe9
223 #define RT5677_DSP_INB2_SRC_CTRL4 0xea
224 #define RT5677_DSP_INB3_SRC_CTRL1 0xeb
225 #define RT5677_DSP_INB3_SRC_CTRL2 0xec
226 #define RT5677_DSP_INB3_SRC_CTRL3 0xed
227 #define RT5677_DSP_INB3_SRC_CTRL4 0xee
228 #define RT5677_DSP_OUTB1_SRC_CTRL1 0xef
229 #define RT5677_DSP_OUTB1_SRC_CTRL2 0xf0
230 #define RT5677_DSP_OUTB1_SRC_CTRL3 0xf1
231 #define RT5677_DSP_OUTB1_SRC_CTRL4 0xf2
232 #define RT5677_DSP_OUTB2_SRC_CTRL1 0xf3
233 #define RT5677_DSP_OUTB2_SRC_CTRL2 0xf4
234 #define RT5677_DSP_OUTB2_SRC_CTRL3 0xf5
235 #define RT5677_DSP_OUTB2_SRC_CTRL4 0xf6
237 /* Virtual DSP Mixer Control */
238 #define RT5677_DSP_OUTB_0123_MIXER_CTRL 0xf7
239 #define RT5677_DSP_OUTB_45_MIXER_CTRL 0xf8
240 #define RT5677_DSP_OUTB_67_MIXER_CTRL 0xf9
242 /* General Control */
243 #define RT5677_DIG_MISC 0xfa
244 #define RT5677_GEN_CTRL1 0xfb
245 #define RT5677_GEN_CTRL2 0xfc
247 /* DSP Mode I2C Control*/
248 #define RT5677_DSP_I2C_OP_CODE 0x00
249 #define RT5677_DSP_I2C_ADDR_LSB 0x01
250 #define RT5677_DSP_I2C_ADDR_MSB 0x02
251 #define RT5677_DSP_I2C_DATA_LSB 0x03
252 #define RT5677_DSP_I2C_DATA_MSB 0x04
254 /* Index of Codec Private Register definition */
255 #define RT5677_PR_DRC1_CTRL_1 0x01
256 #define RT5677_PR_DRC1_CTRL_2 0x02
257 #define RT5677_PR_DRC1_CTRL_3 0x03
258 #define RT5677_PR_DRC1_CTRL_4 0x04
259 #define RT5677_PR_DRC1_CTRL_5 0x05
260 #define RT5677_PR_DRC1_CTRL_6 0x06
261 #define RT5677_PR_DRC1_CTRL_7 0x07
262 #define RT5677_PR_DRC2_CTRL_1 0x08
263 #define RT5677_PR_DRC2_CTRL_2 0x09
264 #define RT5677_PR_DRC2_CTRL_3 0x0a
265 #define RT5677_PR_DRC2_CTRL_4 0x0b
266 #define RT5677_PR_DRC2_CTRL_5 0x0c
267 #define RT5677_PR_DRC2_CTRL_6 0x0d
268 #define RT5677_PR_DRC2_CTRL_7 0x0e
269 #define RT5677_BIAS_CUR1 0x10
270 #define RT5677_BIAS_CUR2 0x12
271 #define RT5677_BIAS_CUR3 0x13
272 #define RT5677_BIAS_CUR4 0x14
273 #define RT5677_BIAS_CUR5 0x15
274 #define RT5677_VREF_LOUT_CTRL 0x17
275 #define RT5677_DIG_VOL_CTRL1 0x1a
276 #define RT5677_DIG_VOL_CTRL2 0x1b
277 #define RT5677_ANA_ADC_GAIN_CTRL 0x1e
278 #define RT5677_VAD_SRAM_TEST1 0x20
279 #define RT5677_VAD_SRAM_TEST2 0x21
280 #define RT5677_VAD_SRAM_TEST3 0x22
281 #define RT5677_VAD_SRAM_TEST4 0x23
282 #define RT5677_PAD_DRV_CTRL 0x26
283 #define RT5677_DIG_IN_PIN_ST_CTRL1 0x29
284 #define RT5677_DIG_IN_PIN_ST_CTRL2 0x2a
285 #define RT5677_DIG_IN_PIN_ST_CTRL3 0x2b
286 #define RT5677_PLL1_INT 0x38
287 #define RT5677_PLL2_INT 0x39
288 #define RT5677_TEST_CTRL1 0x3a
289 #define RT5677_TEST_CTRL2 0x3b
290 #define RT5677_TEST_CTRL3 0x3c
291 #define RT5677_CHOP_DAC_ADC 0x3d
292 #define RT5677_SOFT_DEPOP_DAC_CLK_CTRL 0x3e
293 #define RT5677_CROSS_OVER_FILTER1 0x90
294 #define RT5677_CROSS_OVER_FILTER2 0x91
295 #define RT5677_CROSS_OVER_FILTER3 0x92
296 #define RT5677_CROSS_OVER_FILTER4 0x93
297 #define RT5677_CROSS_OVER_FILTER5 0x94
298 #define RT5677_CROSS_OVER_FILTER6 0x95
299 #define RT5677_CROSS_OVER_FILTER7 0x96
300 #define RT5677_CROSS_OVER_FILTER8 0x97
301 #define RT5677_CROSS_OVER_FILTER9 0x98
302 #define RT5677_CROSS_OVER_FILTER10 0x99
304 /* global definition */
305 #define RT5677_L_MUTE (0x1 << 15)
306 #define RT5677_L_MUTE_SFT 15
307 #define RT5677_VOL_L_MUTE (0x1 << 14)
308 #define RT5677_VOL_L_SFT 14
309 #define RT5677_R_MUTE (0x1 << 7)
310 #define RT5677_R_MUTE_SFT 7
311 #define RT5677_VOL_R_MUTE (0x1 << 6)
312 #define RT5677_VOL_R_SFT 6
313 #define RT5677_L_VOL_MASK (0x3f << 8)
314 #define RT5677_L_VOL_SFT 8
315 #define RT5677_R_VOL_MASK (0x3f)
316 #define RT5677_R_VOL_SFT 0
318 /* LOUT1 Control (0x01) */
319 #define RT5677_LOUT1_L_MUTE (0x1 << 15)
320 #define RT5677_LOUT1_L_MUTE_SFT (15)
321 #define RT5677_LOUT1_L_DF (0x1 << 14)
322 #define RT5677_LOUT1_L_DF_SFT (14)
323 #define RT5677_LOUT2_L_MUTE (0x1 << 13)
324 #define RT5677_LOUT2_L_MUTE_SFT (13)
325 #define RT5677_LOUT2_L_DF (0x1 << 12)
326 #define RT5677_LOUT2_L_DF_SFT (12)
327 #define RT5677_LOUT3_L_MUTE (0x1 << 11)
328 #define RT5677_LOUT3_L_MUTE_SFT (11)
329 #define RT5677_LOUT3_L_DF (0x1 << 10)
330 #define RT5677_LOUT3_L_DF_SFT (10)
331 #define RT5677_LOUT1_ENH_DRV (0x1 << 9)
332 #define RT5677_LOUT1_ENH_DRV_SFT (9)
333 #define RT5677_LOUT2_ENH_DRV (0x1 << 8)
334 #define RT5677_LOUT2_ENH_DRV_SFT (8)
335 #define RT5677_LOUT3_ENH_DRV (0x1 << 7)
336 #define RT5677_LOUT3_ENH_DRV_SFT (7)
338 /* IN1 Control (0x03) */
339 #define RT5677_BST_MASK1 (0xf << 12)
340 #define RT5677_BST_SFT1 12
341 #define RT5677_BST_MASK2 (0xf << 8)
342 #define RT5677_BST_SFT2 8
343 #define RT5677_IN_DF1 (0x1 << 7)
344 #define RT5677_IN_DF1_SFT 7
345 #define RT5677_IN_DF2 (0x1 << 6)
346 #define RT5677_IN_DF2_SFT 6
348 /* Micbias Control (0x04) */
349 #define RT5677_MICBIAS1_OUTVOLT_MASK (0x1 << 15)
350 #define RT5677_MICBIAS1_OUTVOLT_SFT (15)
351 #define RT5677_MICBIAS1_OUTVOLT_2_7V (0x0 << 15)
352 #define RT5677_MICBIAS1_OUTVOLT_2_25V (0x1 << 15)
353 #define RT5677_MICBIAS1_CTRL_VDD_MASK (0x1 << 14)
354 #define RT5677_MICBIAS1_CTRL_VDD_SFT (14)
355 #define RT5677_MICBIAS1_CTRL_VDD_1_8V (0x0 << 14)
356 #define RT5677_MICBIAS1_CTRL_VDD_3_3V (0x1 << 14)
357 #define RT5677_MICBIAS1_OVCD_MASK (0x1 << 11)
358 #define RT5677_MICBIAS1_OVCD_SHIFT (11)
359 #define RT5677_MICBIAS1_OVCD_DIS (0x0 << 11)
360 #define RT5677_MICBIAS1_OVCD_EN (0x1 << 11)
361 #define RT5677_MICBIAS1_OVTH_MASK (0x3 << 9)
362 #define RT5677_MICBIAS1_OVTH_SFT 9
363 #define RT5677_MICBIAS1_OVTH_640UA (0x0 << 9)
364 #define RT5677_MICBIAS1_OVTH_1280UA (0x1 << 9)
365 #define RT5677_MICBIAS1_OVTH_1920UA (0x2 << 9)
367 /* SLIMbus Parameter (0x07) */
369 /* SLIMbus Rx (0x08) */
370 #define RT5677_SLB_ADC4_MASK (0x3 << 6)
371 #define RT5677_SLB_ADC4_SFT 6
372 #define RT5677_SLB_ADC3_MASK (0x3 << 4)
373 #define RT5677_SLB_ADC3_SFT 4
374 #define RT5677_SLB_ADC2_MASK (0x3 << 2)
375 #define RT5677_SLB_ADC2_SFT 2
376 #define RT5677_SLB_ADC1_MASK (0x3 << 0)
377 #define RT5677_SLB_ADC1_SFT 0
379 /* SLIMBus control (0x09) */
381 /* Sidetone Control (0x13) */
382 #define RT5677_ST_HPF_SEL_MASK (0x7 << 13)
383 #define RT5677_ST_HPF_SEL_SFT 13
384 #define RT5677_ST_HPF_PATH (0x1 << 12)
385 #define RT5677_ST_HPF_PATH_SFT 12
386 #define RT5677_ST_SEL_MASK (0x7 << 9)
387 #define RT5677_ST_SEL_SFT 9
388 #define RT5677_ST_EN (0x1 << 6)
389 #define RT5677_ST_EN_SFT 6
391 /* Analog DAC1/2/3 Source Control (0x15) */
392 #define RT5677_ANA_DAC3_SRC_SEL_MASK (0x3 << 4)
393 #define RT5677_ANA_DAC3_SRC_SEL_SFT 4
394 #define RT5677_ANA_DAC1_2_SRC_SEL_MASK (0x3 << 0)
395 #define RT5677_ANA_DAC1_2_SRC_SEL_SFT 0
397 /* IF/DSP to DAC3/4 Mixer Control (0x16) */
398 #define RT5677_M_DAC4_L_VOL (0x1 << 15)
399 #define RT5677_M_DAC4_L_VOL_SFT 15
400 #define RT5677_SEL_DAC4_L_SRC_MASK (0x7 << 12)
401 #define RT5677_SEL_DAC4_L_SRC_SFT 12
402 #define RT5677_M_DAC4_R_VOL (0x1 << 11)
403 #define RT5677_M_DAC4_R_VOL_SFT 11
404 #define RT5677_SEL_DAC4_R_SRC_MASK (0x7 << 8)
405 #define RT5677_SEL_DAC4_R_SRC_SFT 8
406 #define RT5677_M_DAC3_L_VOL (0x1 << 7)
407 #define RT5677_M_DAC3_L_VOL_SFT 7
408 #define RT5677_SEL_DAC3_L_SRC_MASK (0x7 << 4)
409 #define RT5677_SEL_DAC3_L_SRC_SFT 4
410 #define RT5677_M_DAC3_R_VOL (0x1 << 3)
411 #define RT5677_M_DAC3_R_VOL_SFT 3
412 #define RT5677_SEL_DAC3_R_SRC_MASK (0x7 << 0)
413 #define RT5677_SEL_DAC3_R_SRC_SFT 0
415 /* DAC4 Digital Volume (0x17) */
416 #define RT5677_DAC4_L_VOL_MASK (0xff << 8)
417 #define RT5677_DAC4_L_VOL_SFT 8
418 #define RT5677_DAC4_R_VOL_MASK (0xff)
419 #define RT5677_DAC4_R_VOL_SFT 0
421 /* DAC3 Digital Volume (0x18) */
422 #define RT5677_DAC3_L_VOL_MASK (0xff << 8)
423 #define RT5677_DAC3_L_VOL_SFT 8
424 #define RT5677_DAC3_R_VOL_MASK (0xff)
425 #define RT5677_DAC3_R_VOL_SFT 0
427 /* DAC3 Digital Volume (0x19) */
428 #define RT5677_DAC1_L_VOL_MASK (0xff << 8)
429 #define RT5677_DAC1_L_VOL_SFT 8
430 #define RT5677_DAC1_R_VOL_MASK (0xff)
431 #define RT5677_DAC1_R_VOL_SFT 0
433 /* DAC2 Digital Volume (0x1a) */
434 #define RT5677_DAC2_L_VOL_MASK (0xff << 8)
435 #define RT5677_DAC2_L_VOL_SFT 8
436 #define RT5677_DAC2_R_VOL_MASK (0xff)
437 #define RT5677_DAC2_R_VOL_SFT 0
439 /* IF/DSP to DAC2 Mixer Control (0x1b) */
440 #define RT5677_M_DAC2_L_VOL (0x1 << 7)
441 #define RT5677_M_DAC2_L_VOL_SFT 7
442 #define RT5677_SEL_DAC2_L_SRC_MASK (0x7 << 4)
443 #define RT5677_SEL_DAC2_L_SRC_SFT 4
444 #define RT5677_M_DAC2_R_VOL (0x1 << 3)
445 #define RT5677_M_DAC2_R_VOL_SFT 3
446 #define RT5677_SEL_DAC2_R_SRC_MASK (0x7 << 0)
447 #define RT5677_SEL_DAC2_R_SRC_SFT 0
449 /* Stereo1 ADC Digital Volume Control (0x1c) */
450 #define RT5677_STO1_ADC_L_VOL_MASK (0x7f << 8)
451 #define RT5677_STO1_ADC_L_VOL_SFT 8
452 #define RT5677_STO1_ADC_R_VOL_MASK (0x7f)
453 #define RT5677_STO1_ADC_R_VOL_SFT 0
455 /* Mono ADC Digital Volume Control (0x1d) */
456 #define RT5677_MONO_ADC_L_VOL_MASK (0x7f << 8)
457 #define RT5677_MONO_ADC_L_VOL_SFT 8
458 #define RT5677_MONO_ADC_R_VOL_MASK (0x7f)
459 #define RT5677_MONO_ADC_R_VOL_SFT 0
461 /* Stereo 1/2 ADC Boost Gain Control (0x1e) */
462 #define RT5677_STO1_ADC_L_BST_MASK (0x3 << 14)
463 #define RT5677_STO1_ADC_L_BST_SFT 14
464 #define RT5677_STO1_ADC_R_BST_MASK (0x3 << 12)
465 #define RT5677_STO1_ADC_R_BST_SFT 12
466 #define RT5677_STO1_ADC_COMP_MASK (0x3 << 10)
467 #define RT5677_STO1_ADC_COMP_SFT 10
468 #define RT5677_STO2_ADC_L_BST_MASK (0x3 << 8)
469 #define RT5677_STO2_ADC_L_BST_SFT 8
470 #define RT5677_STO2_ADC_R_BST_MASK (0x3 << 6)
471 #define RT5677_STO2_ADC_R_BST_SFT 6
472 #define RT5677_STO2_ADC_COMP_MASK (0x3 << 4)
473 #define RT5677_STO2_ADC_COMP_SFT 4
475 /* Stereo2 ADC Digital Volume Control (0x1f) */
476 #define RT5677_STO2_ADC_L_VOL_MASK (0x7f << 8)
477 #define RT5677_STO2_ADC_L_VOL_SFT 8
478 #define RT5677_STO2_ADC_R_VOL_MASK (0x7f)
479 #define RT5677_STO2_ADC_R_VOL_SFT 0
481 /* ADC Boost Gain Control 2 (0x20) */
482 #define RT5677_MONO_ADC_L_BST_MASK (0x3 << 14)
483 #define RT5677_MONO_ADC_L_BST_SFT 14
484 #define RT5677_MONO_ADC_R_BST_MASK (0x3 << 12)
485 #define RT5677_MONO_ADC_R_BST_SFT 12
486 #define RT5677_MONO_ADC_COMP_MASK (0x3 << 10)
487 #define RT5677_MONO_ADC_COMP_SFT 10
489 /* Stereo 3/4 ADC Boost Gain Control (0x21) */
490 #define RT5677_STO3_ADC_L_BST_MASK (0x3 << 14)
491 #define RT5677_STO3_ADC_L_BST_SFT 14
492 #define RT5677_STO3_ADC_R_BST_MASK (0x3 << 12)
493 #define RT5677_STO3_ADC_R_BST_SFT 12
494 #define RT5677_STO3_ADC_COMP_MASK (0x3 << 10)
495 #define RT5677_STO3_ADC_COMP_SFT 10
496 #define RT5677_STO4_ADC_L_BST_MASK (0x3 << 8)
497 #define RT5677_STO4_ADC_L_BST_SFT 8
498 #define RT5677_STO4_ADC_R_BST_MASK (0x3 << 6)
499 #define RT5677_STO4_ADC_R_BST_SFT 6
500 #define RT5677_STO4_ADC_COMP_MASK (0x3 << 4)
501 #define RT5677_STO4_ADC_COMP_SFT 4
503 /* Stereo3 ADC Digital Volume Control (0x22) */
504 #define RT5677_STO3_ADC_L_VOL_MASK (0x7f << 8)
505 #define RT5677_STO3_ADC_L_VOL_SFT 8
506 #define RT5677_STO3_ADC_R_VOL_MASK (0x7f)
507 #define RT5677_STO3_ADC_R_VOL_SFT 0
509 /* Stereo4 ADC Digital Volume Control (0x23) */
510 #define RT5677_STO4_ADC_L_VOL_MASK (0x7f << 8)
511 #define RT5677_STO4_ADC_L_VOL_SFT 8
512 #define RT5677_STO4_ADC_R_VOL_MASK (0x7f)
513 #define RT5677_STO4_ADC_R_VOL_SFT 0
515 /* Stereo4 ADC Mixer control (0x24) */
516 #define RT5677_M_STO4_ADC_L2 (0x1 << 15)
517 #define RT5677_M_STO4_ADC_L2_SFT 15
518 #define RT5677_M_STO4_ADC_L1 (0x1 << 14)
519 #define RT5677_M_STO4_ADC_L1_SFT 14
520 #define RT5677_SEL_STO4_ADC1_MASK (0x3 << 12)
521 #define RT5677_SEL_STO4_ADC1_SFT 12
522 #define RT5677_SEL_STO4_ADC2_MASK (0x3 << 10)
523 #define RT5677_SEL_STO4_ADC2_SFT 10
524 #define RT5677_SEL_STO4_DMIC_MASK (0x3 << 8)
525 #define RT5677_SEL_STO4_DMIC_SFT 8
526 #define RT5677_M_STO4_ADC_R1 (0x1 << 7)
527 #define RT5677_M_STO4_ADC_R1_SFT 7
528 #define RT5677_M_STO4_ADC_R2 (0x1 << 6)
529 #define RT5677_M_STO4_ADC_R2_SFT 6
531 /* Stereo3 ADC Mixer control (0x25) */
532 #define RT5677_M_STO3_ADC_L2 (0x1 << 15)
533 #define RT5677_M_STO3_ADC_L2_SFT 15
534 #define RT5677_M_STO3_ADC_L1 (0x1 << 14)
535 #define RT5677_M_STO3_ADC_L1_SFT 14
536 #define RT5677_SEL_STO3_ADC1_MASK (0x3 << 12)
537 #define RT5677_SEL_STO3_ADC1_SFT 12
538 #define RT5677_SEL_STO3_ADC2_MASK (0x3 << 10)
539 #define RT5677_SEL_STO3_ADC2_SFT 10
540 #define RT5677_SEL_STO3_DMIC_MASK (0x3 << 8)
541 #define RT5677_SEL_STO3_DMIC_SFT 8
542 #define RT5677_M_STO3_ADC_R1 (0x1 << 7)
543 #define RT5677_M_STO3_ADC_R1_SFT 7
544 #define RT5677_M_STO3_ADC_R2 (0x1 << 6)
545 #define RT5677_M_STO3_ADC_R2_SFT 6
547 /* Stereo2 ADC Mixer Control (0x26) */
548 #define RT5677_M_STO2_ADC_L2 (0x1 << 15)
549 #define RT5677_M_STO2_ADC_L2_SFT 15
550 #define RT5677_M_STO2_ADC_L1 (0x1 << 14)
551 #define RT5677_M_STO2_ADC_L1_SFT 14
552 #define RT5677_SEL_STO2_ADC1_MASK (0x3 << 12)
553 #define RT5677_SEL_STO2_ADC1_SFT 12
554 #define RT5677_SEL_STO2_ADC2_MASK (0x3 << 10)
555 #define RT5677_SEL_STO2_ADC2_SFT 10
556 #define RT5677_SEL_STO2_DMIC_MASK (0x3 << 8)
557 #define RT5677_SEL_STO2_DMIC_SFT 8
558 #define RT5677_M_STO2_ADC_R1 (0x1 << 7)
559 #define RT5677_M_STO2_ADC_R1_SFT 7
560 #define RT5677_M_STO2_ADC_R2 (0x1 << 6)
561 #define RT5677_M_STO2_ADC_R2_SFT 6
562 #define RT5677_SEL_STO2_LR_MIX_MASK (0x1 << 0)
563 #define RT5677_SEL_STO2_LR_MIX_SFT 0
564 #define RT5677_SEL_STO2_LR_MIX_L (0x0 << 0)
565 #define RT5677_SEL_STO2_LR_MIX_LR (0x1 << 0)
567 /* Stereo1 ADC Mixer control (0x27) */
568 #define RT5677_M_STO1_ADC_L2 (0x1 << 15)
569 #define RT5677_M_STO1_ADC_L2_SFT 15
570 #define RT5677_M_STO1_ADC_L1 (0x1 << 14)
571 #define RT5677_M_STO1_ADC_L1_SFT 14
572 #define RT5677_SEL_STO1_ADC1_MASK (0x3 << 12)
573 #define RT5677_SEL_STO1_ADC1_SFT 12
574 #define RT5677_SEL_STO1_ADC2_MASK (0x3 << 10)
575 #define RT5677_SEL_STO1_ADC2_SFT 10
576 #define RT5677_SEL_STO1_DMIC_MASK (0x3 << 8)
577 #define RT5677_SEL_STO1_DMIC_SFT 8
578 #define RT5677_M_STO1_ADC_R1 (0x1 << 7)
579 #define RT5677_M_STO1_ADC_R1_SFT 7
580 #define RT5677_M_STO1_ADC_R2 (0x1 << 6)
581 #define RT5677_M_STO1_ADC_R2_SFT 6
583 /* Mono ADC Mixer control (0x28) */
584 #define RT5677_M_MONO_ADC_L2 (0x1 << 15)
585 #define RT5677_M_MONO_ADC_L2_SFT 15
586 #define RT5677_M_MONO_ADC_L1 (0x1 << 14)
587 #define RT5677_M_MONO_ADC_L1_SFT 14
588 #define RT5677_SEL_MONO_ADC_L1_MASK (0x3 << 12)
589 #define RT5677_SEL_MONO_ADC_L1_SFT 12
590 #define RT5677_SEL_MONO_ADC_L2_MASK (0x3 << 10)
591 #define RT5677_SEL_MONO_ADC_L2_SFT 10
592 #define RT5677_SEL_MONO_DMIC_L_MASK (0x3 << 8)
593 #define RT5677_SEL_MONO_DMIC_L_SFT 8
594 #define RT5677_M_MONO_ADC_R1 (0x1 << 7)
595 #define RT5677_M_MONO_ADC_R1_SFT 7
596 #define RT5677_M_MONO_ADC_R2 (0x1 << 6)
597 #define RT5677_M_MONO_ADC_R2_SFT 6
598 #define RT5677_SEL_MONO_ADC_R1_MASK (0x3 << 4)
599 #define RT5677_SEL_MONO_ADC_R1_SFT 4
600 #define RT5677_SEL_MONO_ADC_R2_MASK (0x3 << 2)
601 #define RT5677_SEL_MONO_ADC_R2_SFT 2
602 #define RT5677_SEL_MONO_DMIC_R_MASK (0x3 << 0)
603 #define RT5677_SEL_MONO_DMIC_R_SFT 0
605 /* ADC/IF/DSP to DAC1 Mixer control (0x29) */
606 #define RT5677_M_ADDA_MIXER1_L (0x1 << 15)
607 #define RT5677_M_ADDA_MIXER1_L_SFT 15
608 #define RT5677_M_DAC1_L (0x1 << 14)
609 #define RT5677_M_DAC1_L_SFT 14
610 #define RT5677_DAC1_L_SEL_MASK (0x7 << 8)
611 #define RT5677_DAC1_L_SEL_SFT 8
612 #define RT5677_M_ADDA_MIXER1_R (0x1 << 7)
613 #define RT5677_M_ADDA_MIXER1_R_SFT 7
614 #define RT5677_M_DAC1_R (0x1 << 6)
615 #define RT5677_M_DAC1_R_SFT 6
616 #define RT5677_ADDA1_SEL_MASK (0x3 << 0)
617 #define RT5677_ADDA1_SEL_SFT 0
619 /* Stereo1 DAC Mixer L/R Control (0x2a) */
620 #define RT5677_M_ST_DAC1_L (0x1 << 15)
621 #define RT5677_M_ST_DAC1_L_SFT 15
622 #define RT5677_M_DAC1_L_STO_L (0x1 << 13)
623 #define RT5677_M_DAC1_L_STO_L_SFT 13
624 #define RT5677_DAC1_L_STO_L_VOL_MASK (0x1 << 12)
625 #define RT5677_DAC1_L_STO_L_VOL_SFT 12
626 #define RT5677_M_DAC2_L_STO_L (0x1 << 11)
627 #define RT5677_M_DAC2_L_STO_L_SFT 11
628 #define RT5677_DAC2_L_STO_L_VOL_MASK (0x1 << 10)
629 #define RT5677_DAC2_L_STO_L_VOL_SFT 10
630 #define RT5677_M_DAC1_R_STO_L (0x1 << 9)
631 #define RT5677_M_DAC1_R_STO_L_SFT 9
632 #define RT5677_DAC1_R_STO_L_VOL_MASK (0x1 << 8)
633 #define RT5677_DAC1_R_STO_L_VOL_SFT 8
634 #define RT5677_M_ST_DAC1_R (0x1 << 7)
635 #define RT5677_M_ST_DAC1_R_SFT 7
636 #define RT5677_M_DAC1_R_STO_R (0x1 << 5)
637 #define RT5677_M_DAC1_R_STO_R_SFT 5
638 #define RT5677_DAC1_R_STO_R_VOL_MASK (0x1 << 4)
639 #define RT5677_DAC1_R_STO_R_VOL_SFT 4
640 #define RT5677_M_DAC2_R_STO_R (0x1 << 3)
641 #define RT5677_M_DAC2_R_STO_R_SFT 3
642 #define RT5677_DAC2_R_STO_R_VOL_MASK (0x1 << 2)
643 #define RT5677_DAC2_R_STO_R_VOL_SFT 2
644 #define RT5677_M_DAC1_L_STO_R (0x1 << 1)
645 #define RT5677_M_DAC1_L_STO_R_SFT 1
646 #define RT5677_DAC1_L_STO_R_VOL_MASK (0x1 << 0)
647 #define RT5677_DAC1_L_STO_R_VOL_SFT 0
649 /* Mono DAC Mixer L/R Control (0x2b) */
650 #define RT5677_M_ST_DAC2_L (0x1 << 15)
651 #define RT5677_M_ST_DAC2_L_SFT 15
652 #define RT5677_M_DAC2_L_MONO_L (0x1 << 13)
653 #define RT5677_M_DAC2_L_MONO_L_SFT 13
654 #define RT5677_DAC2_L_MONO_L_VOL_MASK (0x1 << 12)
655 #define RT5677_DAC2_L_MONO_L_VOL_SFT 12
656 #define RT5677_M_DAC2_R_MONO_L (0x1 << 11)
657 #define RT5677_M_DAC2_R_MONO_L_SFT 11
658 #define RT5677_DAC2_R_MONO_L_VOL_MASK (0x1 << 10)
659 #define RT5677_DAC2_R_MONO_L_VOL_SFT 10
660 #define RT5677_M_DAC1_L_MONO_L (0x1 << 9)
661 #define RT5677_M_DAC1_L_MONO_L_SFT 9
662 #define RT5677_DAC1_L_MONO_L_VOL_MASK (0x1 << 8)
663 #define RT5677_DAC1_L_MONO_L_VOL_SFT 8
664 #define RT5677_M_ST_DAC2_R (0x1 << 7)
665 #define RT5677_M_ST_DAC2_R_SFT 7
666 #define RT5677_M_DAC2_R_MONO_R (0x1 << 5)
667 #define RT5677_M_DAC2_R_MONO_R_SFT 5
668 #define RT5677_DAC2_R_MONO_R_VOL_MASK (0x1 << 4)
669 #define RT5677_DAC2_R_MONO_R_VOL_SFT 4
670 #define RT5677_M_DAC1_R_MONO_R (0x1 << 3)
671 #define RT5677_M_DAC1_R_MONO_R_SFT 3
672 #define RT5677_DAC1_R_MONO_R_VOL_MASK (0x1 << 2)
673 #define RT5677_DAC1_R_MONO_R_VOL_SFT 2
674 #define RT5677_M_DAC2_L_MONO_R (0x1 << 1)
675 #define RT5677_M_DAC2_L_MONO_R_SFT 1
676 #define RT5677_DAC2_L_MONO_R_VOL_MASK (0x1 << 0)
677 #define RT5677_DAC2_L_MONO_R_VOL_SFT 0
679 /* DD Mixer 1 Control (0x2c) */
680 #define RT5677_M_STO_L_DD1_L (0x1 << 15)
681 #define RT5677_M_STO_L_DD1_L_SFT 15
682 #define RT5677_STO_L_DD1_L_VOL_MASK (0x1 << 14)
683 #define RT5677_STO_L_DD1_L_VOL_SFT 14
684 #define RT5677_M_MONO_L_DD1_L (0x1 << 13)
685 #define RT5677_M_MONO_L_DD1_L_SFT 13
686 #define RT5677_MONO_L_DD1_L_VOL_MASK (0x1 << 12)
687 #define RT5677_MONO_L_DD1_L_VOL_SFT 12
688 #define RT5677_M_DAC3_L_DD1_L (0x1 << 11)
689 #define RT5677_M_DAC3_L_DD1_L_SFT 11
690 #define RT5677_DAC3_L_DD1_L_VOL_MASK (0x1 << 10)
691 #define RT5677_DAC3_L_DD1_L_VOL_SFT 10
692 #define RT5677_M_DAC3_R_DD1_L (0x1 << 9)
693 #define RT5677_M_DAC3_R_DD1_L_SFT 9
694 #define RT5677_DAC3_R_DD1_L_VOL_MASK (0x1 << 8)
695 #define RT5677_DAC3_R_DD1_L_VOL_SFT 8
696 #define RT5677_M_STO_R_DD1_R (0x1 << 7)
697 #define RT5677_M_STO_R_DD1_R_SFT 7
698 #define RT5677_STO_R_DD1_R_VOL_MASK (0x1 << 6)
699 #define RT5677_STO_R_DD1_R_VOL_SFT 6
700 #define RT5677_M_MONO_R_DD1_R (0x1 << 5)
701 #define RT5677_M_MONO_R_DD1_R_SFT 5
702 #define RT5677_MONO_R_DD1_R_VOL_MASK (0x1 << 4)
703 #define RT5677_MONO_R_DD1_R_VOL_SFT 4
704 #define RT5677_M_DAC3_R_DD1_R (0x1 << 3)
705 #define RT5677_M_DAC3_R_DD1_R_SFT 3
706 #define RT5677_DAC3_R_DD1_R_VOL_MASK (0x1 << 2)
707 #define RT5677_DAC3_R_DD1_R_VOL_SFT 2
708 #define RT5677_M_DAC3_L_DD1_R (0x1 << 1)
709 #define RT5677_M_DAC3_L_DD1_R_SFT 1
710 #define RT5677_DAC3_L_DD1_R_VOL_MASK (0x1 << 0)
711 #define RT5677_DAC3_L_DD1_R_VOL_SFT 0
713 /* DD Mixer 2 Control (0x2d) */
714 #define RT5677_M_STO_L_DD2_L (0x1 << 15)
715 #define RT5677_M_STO_L_DD2_L_SFT 15
716 #define RT5677_STO_L_DD2_L_VOL_MASK (0x1 << 14)
717 #define RT5677_STO_L_DD2_L_VOL_SFT 14
718 #define RT5677_M_MONO_L_DD2_L (0x1 << 13)
719 #define RT5677_M_MONO_L_DD2_L_SFT 13
720 #define RT5677_MONO_L_DD2_L_VOL_MASK (0x1 << 12)
721 #define RT5677_MONO_L_DD2_L_VOL_SFT 12
722 #define RT5677_M_DAC4_L_DD2_L (0x1 << 11)
723 #define RT5677_M_DAC4_L_DD2_L_SFT 11
724 #define RT5677_DAC4_L_DD2_L_VOL_MASK (0x1 << 10)
725 #define RT5677_DAC4_L_DD2_L_VOL_SFT 10
726 #define RT5677_M_DAC4_R_DD2_L (0x1 << 9)
727 #define RT5677_M_DAC4_R_DD2_L_SFT 9
728 #define RT5677_DAC4_R_DD2_L_VOL_MASK (0x1 << 8)
729 #define RT5677_DAC4_R_DD2_L_VOL_SFT 8
730 #define RT5677_M_STO_R_DD2_R (0x1 << 7)
731 #define RT5677_M_STO_R_DD2_R_SFT 7
732 #define RT5677_STO_R_DD2_R_VOL_MASK (0x1 << 6)
733 #define RT5677_STO_R_DD2_R_VOL_SFT 6
734 #define RT5677_M_MONO_R_DD2_R (0x1 << 5)
735 #define RT5677_M_MONO_R_DD2_R_SFT 5
736 #define RT5677_MONO_R_DD2_R_VOL_MASK (0x1 << 4)
737 #define RT5677_MONO_R_DD2_R_VOL_SFT 4
738 #define RT5677_M_DAC4_R_DD2_R (0x1 << 3)
739 #define RT5677_M_DAC4_R_DD2_R_SFT 3
740 #define RT5677_DAC4_R_DD2_R_VOL_MASK (0x1 << 2)
741 #define RT5677_DAC4_R_DD2_R_VOL_SFT 2
742 #define RT5677_M_DAC4_L_DD2_R (0x1 << 1)
743 #define RT5677_M_DAC4_L_DD2_R_SFT 1
744 #define RT5677_DAC4_L_DD2_R_VOL_MASK (0x1 << 0)
745 #define RT5677_DAC4_L_DD2_R_VOL_SFT 0
747 /* IF3 data control (0x2f) */
748 #define RT5677_IF3_DAC_SEL_MASK (0x3 << 6)
749 #define RT5677_IF3_DAC_SEL_SFT 6
750 #define RT5677_IF3_ADC_SEL_MASK (0x3 << 4)
751 #define RT5677_IF3_ADC_SEL_SFT 4
752 #define RT5677_IF3_ADC_IN_MASK (0xf << 0)
753 #define RT5677_IF3_ADC_IN_SFT 0
755 /* IF4 data control (0x30) */
756 #define RT5677_IF4_ADC_IN_MASK (0xf << 4)
757 #define RT5677_IF4_ADC_IN_SFT 4
758 #define RT5677_IF4_DAC_SEL_MASK (0x3 << 2)
759 #define RT5677_IF4_DAC_SEL_SFT 2
760 #define RT5677_IF4_ADC_SEL_MASK (0x3 << 0)
761 #define RT5677_IF4_ADC_SEL_SFT 0
763 /* PDM Output Control (0x31) */
764 #define RT5677_M_PDM1_L (0x1 << 15)
765 #define RT5677_M_PDM1_L_SFT 15
766 #define RT5677_SEL_PDM1_L_MASK (0x3 << 12)
767 #define RT5677_SEL_PDM1_L_SFT 12
768 #define RT5677_M_PDM1_R (0x1 << 11)
769 #define RT5677_M_PDM1_R_SFT 11
770 #define RT5677_SEL_PDM1_R_MASK (0x3 << 8)
771 #define RT5677_SEL_PDM1_R_SFT 8
772 #define RT5677_M_PDM2_L (0x1 << 7)
773 #define RT5677_M_PDM2_L_SFT 7
774 #define RT5677_SEL_PDM2_L_MASK (0x3 << 4)
775 #define RT5677_SEL_PDM2_L_SFT 4
776 #define RT5677_M_PDM2_R (0x1 << 3)
777 #define RT5677_M_PDM2_R_SFT 3
778 #define RT5677_SEL_PDM2_R_MASK (0x3 << 0)
779 #define RT5677_SEL_PDM2_R_SFT 0
781 /* PDM I2C / Data Control 1 (0x32) */
782 #define RT5677_PDM2_PW_DOWN (0x1 << 7)
783 #define RT5677_PDM1_PW_DOWN (0x1 << 6)
784 #define RT5677_PDM2_BUSY (0x1 << 5)
785 #define RT5677_PDM1_BUSY (0x1 << 4)
786 #define RT5677_PDM_PATTERN (0x1 << 3)
787 #define RT5677_PDM_GAIN (0x1 << 2)
788 #define RT5677_PDM_DIV_MASK (0x3 << 0)
790 /* PDM I2C / Data Control 2 (0x33) */
791 #define RT5677_PDM1_I2C_ID (0xf << 12)
792 #define RT5677_PDM1_EXE (0x1 << 11)
793 #define RT5677_PDM1_I2C_CMD (0x1 << 10)
794 #define RT5677_PDM1_I2C_EXE (0x1 << 9)
795 #define RT5677_PDM1_I2C_BUSY (0x1 << 8)
796 #define RT5677_PDM2_I2C_ID (0xf << 4)
797 #define RT5677_PDM2_EXE (0x1 << 3)
798 #define RT5677_PDM2_I2C_CMD (0x1 << 2)
799 #define RT5677_PDM2_I2C_EXE (0x1 << 1)
800 #define RT5677_PDM2_I2C_BUSY (0x1 << 0)
802 /* MX3C TDM1 control 1 (0x3c) */
803 #define RT5677_IF1_ADC4_MASK (0x3 << 10)
804 #define RT5677_IF1_ADC4_SFT 10
805 #define RT5677_IF1_ADC3_MASK (0x3 << 8)
806 #define RT5677_IF1_ADC3_SFT 8
807 #define RT5677_IF1_ADC2_MASK (0x3 << 6)
808 #define RT5677_IF1_ADC2_SFT 6
809 #define RT5677_IF1_ADC1_MASK (0x3 << 4)
810 #define RT5677_IF1_ADC1_SFT 4
812 /* MX41 TDM2 control 1 (0x41) */
813 #define RT5677_IF2_ADC4_MASK (0x3 << 10)
814 #define RT5677_IF2_ADC4_SFT 10
815 #define RT5677_IF2_ADC3_MASK (0x3 << 8)
816 #define RT5677_IF2_ADC3_SFT 8
817 #define RT5677_IF2_ADC2_MASK (0x3 << 6)
818 #define RT5677_IF2_ADC2_SFT 6
819 #define RT5677_IF2_ADC1_MASK (0x3 << 4)
820 #define RT5677_IF2_ADC1_SFT 4
822 /* Digital Microphone Control 1 (0x50) */
823 #define RT5677_DMIC_1_EN_MASK (0x1 << 15)
824 #define RT5677_DMIC_1_EN_SFT 15
825 #define RT5677_DMIC_1_DIS (0x0 << 15)
826 #define RT5677_DMIC_1_EN (0x1 << 15)
827 #define RT5677_DMIC_2_EN_MASK (0x1 << 14)
828 #define RT5677_DMIC_2_EN_SFT 14
829 #define RT5677_DMIC_2_DIS (0x0 << 14)
830 #define RT5677_DMIC_2_EN (0x1 << 14)
831 #define RT5677_DMIC_L_STO1_LH_MASK (0x1 << 13)
832 #define RT5677_DMIC_L_STO1_LH_SFT 13
833 #define RT5677_DMIC_L_STO1_LH_FALLING (0x0 << 13)
834 #define RT5677_DMIC_L_STO1_LH_RISING (0x1 << 13)
835 #define RT5677_DMIC_R_STO1_LH_MASK (0x1 << 12)
836 #define RT5677_DMIC_R_STO1_LH_SFT 12
837 #define RT5677_DMIC_R_STO1_LH_FALLING (0x0 << 12)
838 #define RT5677_DMIC_R_STO1_LH_RISING (0x1 << 12)
839 #define RT5677_DMIC_L_STO3_LH_MASK (0x1 << 11)
840 #define RT5677_DMIC_L_STO3_LH_SFT 11
841 #define RT5677_DMIC_L_STO3_LH_FALLING (0x0 << 11)
842 #define RT5677_DMIC_L_STO3_LH_RISING (0x1 << 11)
843 #define RT5677_DMIC_R_STO3_LH_MASK (0x1 << 10)
844 #define RT5677_DMIC_R_STO3_LH_SFT 10
845 #define RT5677_DMIC_R_STO3_LH_FALLING (0x0 << 10)
846 #define RT5677_DMIC_R_STO3_LH_RISING (0x1 << 10)
847 #define RT5677_DMIC_L_STO2_LH_MASK (0x1 << 9)
848 #define RT5677_DMIC_L_STO2_LH_SFT 9
849 #define RT5677_DMIC_L_STO2_LH_FALLING (0x0 << 9)
850 #define RT5677_DMIC_L_STO2_LH_RISING (0x1 << 9)
851 #define RT5677_DMIC_R_STO2_LH_MASK (0x1 << 8)
852 #define RT5677_DMIC_R_STO2_LH_SFT 8
853 #define RT5677_DMIC_R_STO2_LH_FALLING (0x0 << 8)
854 #define RT5677_DMIC_R_STO2_LH_RISING (0x1 << 8)
855 #define RT5677_DMIC_CLK_MASK (0x7 << 5)
856 #define RT5677_DMIC_CLK_SFT 5
857 #define RT5677_DMIC_3_EN_MASK (0x1 << 4)
858 #define RT5677_DMIC_3_EN_SFT 4
859 #define RT5677_DMIC_3_DIS (0x0 << 4)
860 #define RT5677_DMIC_3_EN (0x1 << 4)
861 #define RT5677_DMIC_R_MONO_LH_MASK (0x1 << 2)
862 #define RT5677_DMIC_R_MONO_LH_SFT 2
863 #define RT5677_DMIC_R_MONO_LH_FALLING (0x0 << 2)
864 #define RT5677_DMIC_R_MONO_LH_RISING (0x1 << 2)
865 #define RT5677_DMIC_L_STO4_LH_MASK (0x1 << 1)
866 #define RT5677_DMIC_L_STO4_LH_SFT 1
867 #define RT5677_DMIC_L_STO4_LH_FALLING (0x0 << 1)
868 #define RT5677_DMIC_L_STO4_LH_RISING (0x1 << 1)
869 #define RT5677_DMIC_R_STO4_LH_MASK (0x1 << 0)
870 #define RT5677_DMIC_R_STO4_LH_SFT 0
871 #define RT5677_DMIC_R_STO4_LH_FALLING (0x0 << 0)
872 #define RT5677_DMIC_R_STO4_LH_RISING (0x1 << 0)
874 /* Digital Microphone Control 2 (0x51) */
875 #define RT5677_DMIC_4_EN_MASK (0x1 << 15)
876 #define RT5677_DMIC_4_EN_SFT 15
877 #define RT5677_DMIC_4_DIS (0x0 << 15)
878 #define RT5677_DMIC_4_EN (0x1 << 15)
879 #define RT5677_DMIC_4L_LH_MASK (0x1 << 7)
880 #define RT5677_DMIC_4L_LH_SFT 7
881 #define RT5677_DMIC_4L_LH_FALLING (0x0 << 7)
882 #define RT5677_DMIC_4L_LH_RISING (0x1 << 7)
883 #define RT5677_DMIC_4R_LH_MASK (0x1 << 6)
884 #define RT5677_DMIC_4R_LH_SFT 6
885 #define RT5677_DMIC_4R_LH_FALLING (0x0 << 6)
886 #define RT5677_DMIC_4R_LH_RISING (0x1 << 6)
887 #define RT5677_DMIC_3L_LH_MASK (0x1 << 5)
888 #define RT5677_DMIC_3L_LH_SFT 5
889 #define RT5677_DMIC_3L_LH_FALLING (0x0 << 5)
890 #define RT5677_DMIC_3L_LH_RISING (0x1 << 5)
891 #define RT5677_DMIC_3R_LH_MASK (0x1 << 4)
892 #define RT5677_DMIC_3R_LH_SFT 4
893 #define RT5677_DMIC_3R_LH_FALLING (0x0 << 4)
894 #define RT5677_DMIC_3R_LH_RISING (0x1 << 4)
895 #define RT5677_DMIC_2L_LH_MASK (0x1 << 3)
896 #define RT5677_DMIC_2L_LH_SFT 3
897 #define RT5677_DMIC_2L_LH_FALLING (0x0 << 3)
898 #define RT5677_DMIC_2L_LH_RISING (0x1 << 3)
899 #define RT5677_DMIC_2R_LH_MASK (0x1 << 2)
900 #define RT5677_DMIC_2R_LH_SFT 2
901 #define RT5677_DMIC_2R_LH_FALLING (0x0 << 2)
902 #define RT5677_DMIC_2R_LH_RISING (0x1 << 2)
903 #define RT5677_DMIC_1L_LH_MASK (0x1 << 1)
904 #define RT5677_DMIC_1L_LH_SFT 1
905 #define RT5677_DMIC_1L_LH_FALLING (0x0 << 1)
906 #define RT5677_DMIC_1L_LH_RISING (0x1 << 1)
907 #define RT5677_DMIC_1R_LH_MASK (0x1 << 0)
908 #define RT5677_DMIC_1R_LH_SFT 0
909 #define RT5677_DMIC_1R_LH_FALLING (0x0 << 0)
910 #define RT5677_DMIC_1R_LH_RISING (0x1 << 0)
912 /* Power Management for Digital 1 (0x61) */
913 #define RT5677_PWR_I2S1 (0x1 << 15)
914 #define RT5677_PWR_I2S1_BIT 15
915 #define RT5677_PWR_I2S2 (0x1 << 14)
916 #define RT5677_PWR_I2S2_BIT 14
917 #define RT5677_PWR_I2S3 (0x1 << 13)
918 #define RT5677_PWR_I2S3_BIT 13
919 #define RT5677_PWR_DAC1 (0x1 << 12)
920 #define RT5677_PWR_DAC1_BIT 12
921 #define RT5677_PWR_DAC2 (0x1 << 11)
922 #define RT5677_PWR_DAC2_BIT 11
923 #define RT5677_PWR_I2S4 (0x1 << 10)
924 #define RT5677_PWR_I2S4_BIT 10
925 #define RT5677_PWR_SLB (0x1 << 9)
926 #define RT5677_PWR_SLB_BIT 9
927 #define RT5677_PWR_DAC3 (0x1 << 7)
928 #define RT5677_PWR_DAC3_BIT 7
929 #define RT5677_PWR_ADCFED2 (0x1 << 4)
930 #define RT5677_PWR_ADCFED2_BIT 4
931 #define RT5677_PWR_ADCFED1 (0x1 << 3)
932 #define RT5677_PWR_ADCFED1_BIT 3
933 #define RT5677_PWR_ADC_L (0x1 << 2)
934 #define RT5677_PWR_ADC_L_BIT 2
935 #define RT5677_PWR_ADC_R (0x1 << 1)
936 #define RT5677_PWR_ADC_R_BIT 1
937 #define RT5677_PWR_I2C_MASTER (0x1 << 0)
938 #define RT5677_PWR_I2C_MASTER_BIT 0
940 /* Power Management for Digital 2 (0x62) */
941 #define RT5677_PWR_ADC_S1F (0x1 << 15)
942 #define RT5677_PWR_ADC_S1F_BIT 15
943 #define RT5677_PWR_ADC_MF_L (0x1 << 14)
944 #define RT5677_PWR_ADC_MF_L_BIT 14
945 #define RT5677_PWR_ADC_MF_R (0x1 << 13)
946 #define RT5677_PWR_ADC_MF_R_BIT 13
947 #define RT5677_PWR_DAC_S1F (0x1 << 12)
948 #define RT5677_PWR_DAC_S1F_BIT 12
949 #define RT5677_PWR_DAC_M2F_L (0x1 << 11)
950 #define RT5677_PWR_DAC_M2F_L_BIT 11
951 #define RT5677_PWR_DAC_M2F_R (0x1 << 10)
952 #define RT5677_PWR_DAC_M2F_R_BIT 10
953 #define RT5677_PWR_DAC_M3F_L (0x1 << 9)
954 #define RT5677_PWR_DAC_M3F_L_BIT 9
955 #define RT5677_PWR_DAC_M3F_R (0x1 << 8)
956 #define RT5677_PWR_DAC_M3F_R_BIT 8
957 #define RT5677_PWR_DAC_M4F_L (0x1 << 7)
958 #define RT5677_PWR_DAC_M4F_L_BIT 7
959 #define RT5677_PWR_DAC_M4F_R (0x1 << 6)
960 #define RT5677_PWR_DAC_M4F_R_BIT 6
961 #define RT5677_PWR_ADC_S2F (0x1 << 5)
962 #define RT5677_PWR_ADC_S2F_BIT 5
963 #define RT5677_PWR_ADC_S3F (0x1 << 4)
964 #define RT5677_PWR_ADC_S3F_BIT 4
965 #define RT5677_PWR_ADC_S4F (0x1 << 3)
966 #define RT5677_PWR_ADC_S4F_BIT 3
967 #define RT5677_PWR_PDM1 (0x1 << 2)
968 #define RT5677_PWR_PDM1_BIT 2
969 #define RT5677_PWR_PDM2 (0x1 << 1)
970 #define RT5677_PWR_PDM2_BIT 1
972 /* Power Management for Analog 1 (0x63) */
973 #define RT5677_PWR_VREF1 (0x1 << 15)
974 #define RT5677_PWR_VREF1_BIT 15
975 #define RT5677_PWR_FV1 (0x1 << 14)
976 #define RT5677_PWR_FV1_BIT 14
977 #define RT5677_PWR_MB (0x1 << 13)
978 #define RT5677_PWR_MB_BIT 13
979 #define RT5677_PWR_LO1 (0x1 << 12)
980 #define RT5677_PWR_LO1_BIT 12
981 #define RT5677_PWR_BG (0x1 << 11)
982 #define RT5677_PWR_BG_BIT 11
983 #define RT5677_PWR_LO2 (0x1 << 10)
984 #define RT5677_PWR_LO2_BIT 10
985 #define RT5677_PWR_LO3 (0x1 << 9)
986 #define RT5677_PWR_LO3_BIT 9
987 #define RT5677_PWR_VREF2 (0x1 << 8)
988 #define RT5677_PWR_VREF2_BIT 8
989 #define RT5677_PWR_FV2 (0x1 << 7)
990 #define RT5677_PWR_FV2_BIT 7
991 #define RT5677_LDO2_SEL_MASK (0x7 << 4)
992 #define RT5677_LDO2_SEL_SFT 4
993 #define RT5677_LDO1_SEL_MASK (0x7 << 0)
994 #define RT5677_LDO1_SEL_SFT 0
996 /* Power Management for Analog 2 (0x64) */
997 #define RT5677_PWR_BST1 (0x1 << 15)
998 #define RT5677_PWR_BST1_BIT 15
999 #define RT5677_PWR_BST2 (0x1 << 14)
1000 #define RT5677_PWR_BST2_BIT 14
1001 #define RT5677_PWR_CLK_MB1 (0x1 << 13)
1002 #define RT5677_PWR_CLK_MB1_BIT 13
1003 #define RT5677_PWR_SLIM (0x1 << 12)
1004 #define RT5677_PWR_SLIM_BIT 12
1005 #define RT5677_PWR_MB1 (0x1 << 11)
1006 #define RT5677_PWR_MB1_BIT 11
1007 #define RT5677_PWR_PP_MB1 (0x1 << 10)
1008 #define RT5677_PWR_PP_MB1_BIT 10
1009 #define RT5677_PWR_PLL1 (0x1 << 9)
1010 #define RT5677_PWR_PLL1_BIT 9
1011 #define RT5677_PWR_PLL2 (0x1 << 8)
1012 #define RT5677_PWR_PLL2_BIT 8
1013 #define RT5677_PWR_CORE (0x1 << 7)
1014 #define RT5677_PWR_CORE_BIT 7
1015 #define RT5677_PWR_CLK_MB (0x1 << 6)
1016 #define RT5677_PWR_CLK_MB_BIT 6
1017 #define RT5677_PWR_BST1_P (0x1 << 5)
1018 #define RT5677_PWR_BST1_P_BIT 5
1019 #define RT5677_PWR_BST2_P (0x1 << 4)
1020 #define RT5677_PWR_BST2_P_BIT 4
1021 #define RT5677_PWR_IPTV (0x1 << 3)
1022 #define RT5677_PWR_IPTV_BIT 3
1023 #define RT5677_PWR_25M_CLK (0x1 << 1)
1024 #define RT5677_PWR_25M_CLK_BIT 1
1025 #define RT5677_PWR_LDO1 (0x1 << 0)
1026 #define RT5677_PWR_LDO1_BIT 0
1028 /* Power Management for DSP (0x65) */
1029 #define RT5677_PWR_SR7 (0x1 << 10)
1030 #define RT5677_PWR_SR7_BIT 10
1031 #define RT5677_PWR_SR6 (0x1 << 9)
1032 #define RT5677_PWR_SR6_BIT 9
1033 #define RT5677_PWR_SR5 (0x1 << 8)
1034 #define RT5677_PWR_SR5_BIT 8
1035 #define RT5677_PWR_SR4 (0x1 << 7)
1036 #define RT5677_PWR_SR4_BIT 7
1037 #define RT5677_PWR_SR3 (0x1 << 6)
1038 #define RT5677_PWR_SR3_BIT 6
1039 #define RT5677_PWR_SR2 (0x1 << 5)
1040 #define RT5677_PWR_SR2_BIT 5
1041 #define RT5677_PWR_SR1 (0x1 << 4)
1042 #define RT5677_PWR_SR1_BIT 4
1043 #define RT5677_PWR_SR0 (0x1 << 3)
1044 #define RT5677_PWR_SR0_BIT 3
1045 #define RT5677_PWR_MLT (0x1 << 2)
1046 #define RT5677_PWR_MLT_BIT 2
1047 #define RT5677_PWR_DSP (0x1 << 1)
1048 #define RT5677_PWR_DSP_BIT 1
1049 #define RT5677_PWR_DSP_CPU (0x1 << 0)
1050 #define RT5677_PWR_DSP_CPU_BIT 0
1052 /* Power Status for DSP (0x66) */
1053 #define RT5677_PWR_SR7_RDY (0x1 << 9)
1054 #define RT5677_PWR_SR7_RDY_BIT 9
1055 #define RT5677_PWR_SR6_RDY (0x1 << 8)
1056 #define RT5677_PWR_SR6_RDY_BIT 8
1057 #define RT5677_PWR_SR5_RDY (0x1 << 7)
1058 #define RT5677_PWR_SR5_RDY_BIT 7
1059 #define RT5677_PWR_SR4_RDY (0x1 << 6)
1060 #define RT5677_PWR_SR4_RDY_BIT 6
1061 #define RT5677_PWR_SR3_RDY (0x1 << 5)
1062 #define RT5677_PWR_SR3_RDY_BIT 5
1063 #define RT5677_PWR_SR2_RDY (0x1 << 4)
1064 #define RT5677_PWR_SR2_RDY_BIT 4
1065 #define RT5677_PWR_SR1_RDY (0x1 << 3)
1066 #define RT5677_PWR_SR1_RDY_BIT 3
1067 #define RT5677_PWR_SR0_RDY (0x1 << 2)
1068 #define RT5677_PWR_SR0_RDY_BIT 2
1069 #define RT5677_PWR_MLT_RDY (0x1 << 1)
1070 #define RT5677_PWR_MLT_RDY_BIT 1
1071 #define RT5677_PWR_DSP_RDY (0x1 << 0)
1072 #define RT5677_PWR_DSP_RDY_BIT 0
1074 /* Power Management for DSP (0x67) */
1075 #define RT5677_PWR_SLIM_ISO (0x1 << 11)
1076 #define RT5677_PWR_SLIM_ISO_BIT 11
1077 #define RT5677_PWR_CORE_ISO (0x1 << 10)
1078 #define RT5677_PWR_CORE_ISO_BIT 10
1079 #define RT5677_PWR_DSP_ISO (0x1 << 9)
1080 #define RT5677_PWR_DSP_ISO_BIT 9
1081 #define RT5677_PWR_SR7_ISO (0x1 << 8)
1082 #define RT5677_PWR_SR7_ISO_BIT 8
1083 #define RT5677_PWR_SR6_ISO (0x1 << 7)
1084 #define RT5677_PWR_SR6_ISO_BIT 7
1085 #define RT5677_PWR_SR5_ISO (0x1 << 6)
1086 #define RT5677_PWR_SR5_ISO_BIT 6
1087 #define RT5677_PWR_SR4_ISO (0x1 << 5)
1088 #define RT5677_PWR_SR4_ISO_BIT 5
1089 #define RT5677_PWR_SR3_ISO (0x1 << 4)
1090 #define RT5677_PWR_SR3_ISO_BIT 4
1091 #define RT5677_PWR_SR2_ISO (0x1 << 3)
1092 #define RT5677_PWR_SR2_ISO_BIT 3
1093 #define RT5677_PWR_SR1_ISO (0x1 << 2)
1094 #define RT5677_PWR_SR1_ISO_BIT 2
1095 #define RT5677_PWR_SR0_ISO (0x1 << 1)
1096 #define RT5677_PWR_SR0_ISO_BIT 1
1097 #define RT5677_PWR_MLT_ISO (0x1 << 0)
1098 #define RT5677_PWR_MLT_ISO_BIT 0
1100 /* I2S1/2/3/4 Audio Serial Data Port Control (0x6f 0x70 0x71 0x72) */
1101 #define RT5677_I2S_MS_MASK (0x1 << 15)
1102 #define RT5677_I2S_MS_SFT 15
1103 #define RT5677_I2S_MS_M (0x0 << 15)
1104 #define RT5677_I2S_MS_S (0x1 << 15)
1105 #define RT5677_I2S_O_CP_MASK (0x3 << 10)
1106 #define RT5677_I2S_O_CP_SFT 10
1107 #define RT5677_I2S_O_CP_OFF (0x0 << 10)
1108 #define RT5677_I2S_O_CP_U_LAW (0x1 << 10)
1109 #define RT5677_I2S_O_CP_A_LAW (0x2 << 10)
1110 #define RT5677_I2S_I_CP_MASK (0x3 << 8)
1111 #define RT5677_I2S_I_CP_SFT 8
1112 #define RT5677_I2S_I_CP_OFF (0x0 << 8)
1113 #define RT5677_I2S_I_CP_U_LAW (0x1 << 8)
1114 #define RT5677_I2S_I_CP_A_LAW (0x2 << 8)
1115 #define RT5677_I2S_BP_MASK (0x1 << 7)
1116 #define RT5677_I2S_BP_SFT 7
1117 #define RT5677_I2S_BP_NOR (0x0 << 7)
1118 #define RT5677_I2S_BP_INV (0x1 << 7)
1119 #define RT5677_I2S_DL_MASK (0x3 << 2)
1120 #define RT5677_I2S_DL_SFT 2
1121 #define RT5677_I2S_DL_16 (0x0 << 2)
1122 #define RT5677_I2S_DL_20 (0x1 << 2)
1123 #define RT5677_I2S_DL_24 (0x2 << 2)
1124 #define RT5677_I2S_DL_8 (0x3 << 2)
1125 #define RT5677_I2S_DF_MASK (0x3 << 0)
1126 #define RT5677_I2S_DF_SFT 0
1127 #define RT5677_I2S_DF_I2S (0x0 << 0)
1128 #define RT5677_I2S_DF_LEFT (0x1 << 0)
1129 #define RT5677_I2S_DF_PCM_A (0x2 << 0)
1130 #define RT5677_I2S_DF_PCM_B (0x3 << 0)
1132 /* Clock Tree Control 1 (0x73) */
1133 #define RT5677_I2S_PD1_MASK (0x7 << 12)
1134 #define RT5677_I2S_PD1_SFT 12
1135 #define RT5677_I2S_PD1_1 (0x0 << 12)
1136 #define RT5677_I2S_PD1_2 (0x1 << 12)
1137 #define RT5677_I2S_PD1_3 (0x2 << 12)
1138 #define RT5677_I2S_PD1_4 (0x3 << 12)
1139 #define RT5677_I2S_PD1_6 (0x4 << 12)
1140 #define RT5677_I2S_PD1_8 (0x5 << 12)
1141 #define RT5677_I2S_PD1_12 (0x6 << 12)
1142 #define RT5677_I2S_PD1_16 (0x7 << 12)
1143 #define RT5677_I2S_BCLK_MS2_MASK (0x1 << 11)
1144 #define RT5677_I2S_BCLK_MS2_SFT 11
1145 #define RT5677_I2S_BCLK_MS2_32 (0x0 << 11)
1146 #define RT5677_I2S_BCLK_MS2_64 (0x1 << 11)
1147 #define RT5677_I2S_PD2_MASK (0x7 << 8)
1148 #define RT5677_I2S_PD2_SFT 8
1149 #define RT5677_I2S_PD2_1 (0x0 << 8)
1150 #define RT5677_I2S_PD2_2 (0x1 << 8)
1151 #define RT5677_I2S_PD2_3 (0x2 << 8)
1152 #define RT5677_I2S_PD2_4 (0x3 << 8)
1153 #define RT5677_I2S_PD2_6 (0x4 << 8)
1154 #define RT5677_I2S_PD2_8 (0x5 << 8)
1155 #define RT5677_I2S_PD2_12 (0x6 << 8)
1156 #define RT5677_I2S_PD2_16 (0x7 << 8)
1157 #define RT5677_I2S_BCLK_MS3_MASK (0x1 << 7)
1158 #define RT5677_I2S_BCLK_MS3_SFT 7
1159 #define RT5677_I2S_BCLK_MS3_32 (0x0 << 7)
1160 #define RT5677_I2S_BCLK_MS3_64 (0x1 << 7)
1161 #define RT5677_I2S_PD3_MASK (0x7 << 4)
1162 #define RT5677_I2S_PD3_SFT 4
1163 #define RT5677_I2S_PD3_1 (0x0 << 4)
1164 #define RT5677_I2S_PD3_2 (0x1 << 4)
1165 #define RT5677_I2S_PD3_3 (0x2 << 4)
1166 #define RT5677_I2S_PD3_4 (0x3 << 4)
1167 #define RT5677_I2S_PD3_6 (0x4 << 4)
1168 #define RT5677_I2S_PD3_8 (0x5 << 4)
1169 #define RT5677_I2S_PD3_12 (0x6 << 4)
1170 #define RT5677_I2S_PD3_16 (0x7 << 4)
1171 #define RT5677_I2S_BCLK_MS4_MASK (0x1 << 3)
1172 #define RT5677_I2S_BCLK_MS4_SFT 3
1173 #define RT5677_I2S_BCLK_MS4_32 (0x0 << 3)
1174 #define RT5677_I2S_BCLK_MS4_64 (0x1 << 3)
1175 #define RT5677_I2S_PD4_MASK (0x7 << 0)
1176 #define RT5677_I2S_PD4_SFT 0
1177 #define RT5677_I2S_PD4_1 (0x0 << 0)
1178 #define RT5677_I2S_PD4_2 (0x1 << 0)
1179 #define RT5677_I2S_PD4_3 (0x2 << 0)
1180 #define RT5677_I2S_PD4_4 (0x3 << 0)
1181 #define RT5677_I2S_PD4_6 (0x4 << 0)
1182 #define RT5677_I2S_PD4_8 (0x5 << 0)
1183 #define RT5677_I2S_PD4_12 (0x6 << 0)
1184 #define RT5677_I2S_PD4_16 (0x7 << 0)
1186 /* Clock Tree Control 2 (0x74) */
1187 #define RT5677_I2S_PD5_MASK (0x7 << 12)
1188 #define RT5677_I2S_PD5_SFT 12
1189 #define RT5677_I2S_PD5_1 (0x0 << 12)
1190 #define RT5677_I2S_PD5_2 (0x1 << 12)
1191 #define RT5677_I2S_PD5_3 (0x2 << 12)
1192 #define RT5677_I2S_PD5_4 (0x3 << 12)
1193 #define RT5677_I2S_PD5_6 (0x4 << 12)
1194 #define RT5677_I2S_PD5_8 (0x5 << 12)
1195 #define RT5677_I2S_PD5_12 (0x6 << 12)
1196 #define RT5677_I2S_PD5_16 (0x7 << 12)
1197 #define RT5677_I2S_PD6_MASK (0x7 << 8)
1198 #define RT5677_I2S_PD6_SFT 8
1199 #define RT5677_I2S_PD6_1 (0x0 << 8)
1200 #define RT5677_I2S_PD6_2 (0x1 << 8)
1201 #define RT5677_I2S_PD6_3 (0x2 << 8)
1202 #define RT5677_I2S_PD6_4 (0x3 << 8)
1203 #define RT5677_I2S_PD6_6 (0x4 << 8)
1204 #define RT5677_I2S_PD6_8 (0x5 << 8)
1205 #define RT5677_I2S_PD6_12 (0x6 << 8)
1206 #define RT5677_I2S_PD6_16 (0x7 << 8)
1207 #define RT5677_I2S_PD7_MASK (0x7 << 4)
1208 #define RT5677_I2S_PD7_SFT 4
1209 #define RT5677_I2S_PD7_1 (0x0 << 4)
1210 #define RT5677_I2S_PD7_2 (0x1 << 4)
1211 #define RT5677_I2S_PD7_3 (0x2 << 4)
1212 #define RT5677_I2S_PD7_4 (0x3 << 4)
1213 #define RT5677_I2S_PD7_6 (0x4 << 4)
1214 #define RT5677_I2S_PD7_8 (0x5 << 4)
1215 #define RT5677_I2S_PD7_12 (0x6 << 4)
1216 #define RT5677_I2S_PD7_16 (0x7 << 4)
1217 #define RT5677_I2S_PD8_MASK (0x7 << 0)
1218 #define RT5677_I2S_PD8_SFT 0
1219 #define RT5677_I2S_PD8_1 (0x0 << 0)
1220 #define RT5677_I2S_PD8_2 (0x1 << 0)
1221 #define RT5677_I2S_PD8_3 (0x2 << 0)
1222 #define RT5677_I2S_PD8_4 (0x3 << 0)
1223 #define RT5677_I2S_PD8_6 (0x4 << 0)
1224 #define RT5677_I2S_PD8_8 (0x5 << 0)
1225 #define RT5677_I2S_PD8_12 (0x6 << 0)
1226 #define RT5677_I2S_PD8_16 (0x7 << 0)
1228 /* Clock Tree Control 3 (0x75) */
1229 #define RT5677_DSP_ASRC_O_MASK (0x3 << 6)
1230 #define RT5677_DSP_ASRC_O_SFT 6
1231 #define RT5677_DSP_ASRC_O_1_0 (0x0 << 6)
1232 #define RT5677_DSP_ASRC_O_1_5 (0x1 << 6)
1233 #define RT5677_DSP_ASRC_O_2_0 (0x2 << 6)
1234 #define RT5677_DSP_ASRC_O_3_0 (0x3 << 6)
1235 #define RT5677_DSP_ASRC_I_MASK (0x3 << 4)
1236 #define RT5677_DSP_ASRC_I_SFT 4
1237 #define RT5677_DSP_ASRC_I_1_0 (0x0 << 4)
1238 #define RT5677_DSP_ASRC_I_1_5 (0x1 << 4)
1239 #define RT5677_DSP_ASRC_I_2_0 (0x2 << 4)
1240 #define RT5677_DSP_ASRC_I_3_0 (0x3 << 4)
1241 #define RT5677_DSP_BUS_PD_MASK (0x7 << 0)
1242 #define RT5677_DSP_BUS_PD_SFT 0
1243 #define RT5677_DSP_BUS_PD_1 (0x0 << 0)
1244 #define RT5677_DSP_BUS_PD_2 (0x1 << 0)
1245 #define RT5677_DSP_BUS_PD_3 (0x2 << 0)
1246 #define RT5677_DSP_BUS_PD_4 (0x3 << 0)
1247 #define RT5677_DSP_BUS_PD_6 (0x4 << 0)
1248 #define RT5677_DSP_BUS_PD_8 (0x5 << 0)
1249 #define RT5677_DSP_BUS_PD_12 (0x6 << 0)
1250 #define RT5677_DSP_BUS_PD_16 (0x7 << 0)
1252 #define RT5677_PLL_INP_MAX 40000000
1253 #define RT5677_PLL_INP_MIN 2048000
1254 /* PLL M/N/K Code Control 1 (0x7a 0x7c) */
1255 #define RT5677_PLL_N_MAX 0x1ff
1256 #define RT5677_PLL_N_MASK (RT5677_PLL_N_MAX << 7)
1257 #define RT5677_PLL_N_SFT 7
1258 #define RT5677_PLL_K_BP (0x1 << 5)
1259 #define RT5677_PLL_K_BP_SFT 5
1260 #define RT5677_PLL_K_MAX 0x1f
1261 #define RT5677_PLL_K_MASK (RT5677_PLL_K_MAX)
1262 #define RT5677_PLL_K_SFT 0
1264 /* PLL M/N/K Code Control 2 (0x7b 0x7d) */
1265 #define RT5677_PLL_M_MAX 0xf
1266 #define RT5677_PLL_M_MASK (RT5677_PLL_M_MAX << 12)
1267 #define RT5677_PLL_M_SFT 12
1268 #define RT5677_PLL_M_BP (0x1 << 11)
1269 #define RT5677_PLL_M_BP_SFT 11
1271 /* Global Clock Control 1 (0x80) */
1272 #define RT5677_SCLK_SRC_MASK (0x3 << 14)
1273 #define RT5677_SCLK_SRC_SFT 14
1274 #define RT5677_SCLK_SRC_MCLK (0x0 << 14)
1275 #define RT5677_SCLK_SRC_PLL1 (0x1 << 14)
1276 #define RT5677_SCLK_SRC_RCCLK (0x2 << 14) /* 25MHz */
1277 #define RT5677_SCLK_SRC_SLIM (0x3 << 14)
1278 #define RT5677_PLL1_SRC_MASK (0x7 << 11)
1279 #define RT5677_PLL1_SRC_SFT 11
1280 #define RT5677_PLL1_SRC_MCLK (0x0 << 11)
1281 #define RT5677_PLL1_SRC_BCLK1 (0x1 << 11)
1282 #define RT5677_PLL1_SRC_BCLK2 (0x2 << 11)
1283 #define RT5677_PLL1_SRC_BCLK3 (0x3 << 11)
1284 #define RT5677_PLL1_SRC_BCLK4 (0x4 << 11)
1285 #define RT5677_PLL1_SRC_RCCLK (0x5 << 11)
1286 #define RT5677_PLL1_SRC_SLIM (0x6 << 11)
1287 #define RT5677_MCLK_SRC_MASK (0x1 << 10)
1288 #define RT5677_MCLK_SRC_SFT 10
1289 #define RT5677_MCLK1_SRC (0x0 << 10)
1290 #define RT5677_MCLK2_SRC (0x1 << 10)
1291 #define RT5677_PLL1_PD_MASK (0x1 << 8)
1292 #define RT5677_PLL1_PD_SFT 8
1293 #define RT5677_PLL1_PD_1 (0x0 << 8)
1294 #define RT5677_PLL1_PD_2 (0x1 << 8)
1295 #define RT5671_DAC_OSR_MASK (0x3 << 6)
1296 #define RT5671_DAC_OSR_SFT 6
1297 #define RT5671_DAC_OSR_128 (0x0 << 6)
1298 #define RT5671_DAC_OSR_64 (0x1 << 6)
1299 #define RT5671_DAC_OSR_32 (0x2 << 6)
1300 #define RT5671_ADC_OSR_MASK (0x3 << 4)
1301 #define RT5671_ADC_OSR_SFT 4
1302 #define RT5671_ADC_OSR_128 (0x0 << 4)
1303 #define RT5671_ADC_OSR_64 (0x1 << 4)
1304 #define RT5671_ADC_OSR_32 (0x2 << 4)
1306 /* Global Clock Control 2 (0x81) */
1307 #define RT5677_PLL2_PR_SRC_MASK (0x1 << 15)
1308 #define RT5677_PLL2_PR_SRC_SFT 15
1309 #define RT5677_PLL2_PR_SRC_MCLK1 (0x0 << 15)
1310 #define RT5677_PLL2_PR_SRC_MCLK2 (0x1 << 15)
1311 #define RT5677_PLL2_SRC_MASK (0x7 << 12)
1312 #define RT5677_PLL2_SRC_SFT 12
1313 #define RT5677_PLL2_SRC_MCLK (0x0 << 12)
1314 #define RT5677_PLL2_SRC_BCLK1 (0x1 << 12)
1315 #define RT5677_PLL2_SRC_BCLK2 (0x2 << 12)
1316 #define RT5677_PLL2_SRC_BCLK3 (0x3 << 12)
1317 #define RT5677_PLL2_SRC_BCLK4 (0x4 << 12)
1318 #define RT5677_PLL2_SRC_RCCLK (0x5 << 12)
1319 #define RT5677_PLL2_SRC_SLIM (0x6 << 12)
1320 #define RT5671_DSP_ASRC_O_SRC (0x3 << 10)
1321 #define RT5671_DSP_ASRC_O_SRC_SFT 10
1322 #define RT5671_DSP_ASRC_O_MCLK (0x0 << 10)
1323 #define RT5671_DSP_ASRC_O_PLL1 (0x1 << 10)
1324 #define RT5671_DSP_ASRC_O_SLIM (0x2 << 10)
1325 #define RT5671_DSP_ASRC_O_RCCLK (0x3 << 10)
1326 #define RT5671_DSP_ASRC_I_SRC (0x3 << 8)
1327 #define RT5671_DSP_ASRC_I_SRC_SFT 8
1328 #define RT5671_DSP_ASRC_I_MCLK (0x0 << 8)
1329 #define RT5671_DSP_ASRC_I_PLL1 (0x1 << 8)
1330 #define RT5671_DSP_ASRC_I_SLIM (0x2 << 8)
1331 #define RT5671_DSP_ASRC_I_RCCLK (0x3 << 8)
1332 #define RT5677_DSP_CLK_SRC_MASK (0x1 << 7)
1333 #define RT5677_DSP_CLK_SRC_SFT 7
1334 #define RT5677_DSP_CLK_SRC_PLL2 (0x0 << 7)
1335 #define RT5677_DSP_CLK_SRC_BYPASS (0x1 << 7)
1337 /* VAD Function Control 4 (0x9f) */
1338 #define RT5677_VAD_SRC_MASK (0x7 << 8)
1339 #define RT5677_VAD_SRC_SFT 8
1341 /* DSP InBound Control (0xa3) */
1342 #define RT5677_IB01_SRC_MASK (0x7 << 12)
1343 #define RT5677_IB01_SRC_SFT 12
1344 #define RT5677_IB23_SRC_MASK (0x7 << 8)
1345 #define RT5677_IB23_SRC_SFT 8
1346 #define RT5677_IB45_SRC_MASK (0x7 << 4)
1347 #define RT5677_IB45_SRC_SFT 4
1348 #define RT5677_IB6_SRC_MASK (0x7 << 0)
1349 #define RT5677_IB6_SRC_SFT 0
1351 /* DSP InBound Control (0xa4) */
1352 #define RT5677_IB7_SRC_MASK (0x7 << 12)
1353 #define RT5677_IB7_SRC_SFT 12
1354 #define RT5677_IB8_SRC_MASK (0x7 << 8)
1355 #define RT5677_IB8_SRC_SFT 8
1356 #define RT5677_IB9_SRC_MASK (0x7 << 4)
1357 #define RT5677_IB9_SRC_SFT 4
1359 /* DSP In/OutBound Control (0xa5) */
1360 #define RT5677_SEL_SRC_OB23 (0x1 << 4)
1361 #define RT5677_SEL_SRC_OB23_SFT 4
1362 #define RT5677_SEL_SRC_OB01 (0x1 << 3)
1363 #define RT5677_SEL_SRC_OB01_SFT 3
1364 #define RT5677_SEL_SRC_IB45 (0x1 << 2)
1365 #define RT5677_SEL_SRC_IB45_SFT 2
1366 #define RT5677_SEL_SRC_IB23 (0x1 << 1)
1367 #define RT5677_SEL_SRC_IB23_SFT 1
1368 #define RT5677_SEL_SRC_IB01 (0x1 << 0)
1369 #define RT5677_SEL_SRC_IB01_SFT 0
1371 /* Virtual DSP Mixer Control (0xf7 0xf8 0xf9) */
1372 #define RT5677_DSP_IB_01_H (0x1 << 15)
1373 #define RT5677_DSP_IB_01_H_SFT 15
1374 #define RT5677_DSP_IB_23_H (0x1 << 14)
1375 #define RT5677_DSP_IB_23_H_SFT 14
1376 #define RT5677_DSP_IB_45_H (0x1 << 13)
1377 #define RT5677_DSP_IB_45_H_SFT 13
1378 #define RT5677_DSP_IB_6_H (0x1 << 12)
1379 #define RT5677_DSP_IB_6_H_SFT 12
1380 #define RT5677_DSP_IB_7_H (0x1 << 11)
1381 #define RT5677_DSP_IB_7_H_SFT 11
1382 #define RT5677_DSP_IB_8_H (0x1 << 10)
1383 #define RT5677_DSP_IB_8_H_SFT 10
1384 #define RT5677_DSP_IB_9_H (0x1 << 9)
1385 #define RT5677_DSP_IB_9_H_SFT 9
1386 #define RT5677_DSP_IB_01_L (0x1 << 7)
1387 #define RT5677_DSP_IB_01_L_SFT 7
1388 #define RT5677_DSP_IB_23_L (0x1 << 6)
1389 #define RT5677_DSP_IB_23_L_SFT 6
1390 #define RT5677_DSP_IB_45_L (0x1 << 5)
1391 #define RT5677_DSP_IB_45_L_SFT 5
1392 #define RT5677_DSP_IB_6_L (0x1 << 4)
1393 #define RT5677_DSP_IB_6_L_SFT 4
1394 #define RT5677_DSP_IB_7_L (0x1 << 3)
1395 #define RT5677_DSP_IB_7_L_SFT 3
1396 #define RT5677_DSP_IB_8_L (0x1 << 2)
1397 #define RT5677_DSP_IB_8_L_SFT 2
1398 #define RT5677_DSP_IB_9_L (0x1 << 1)
1399 #define RT5677_DSP_IB_9_L_SFT 1
1401 #define RT5677_SW_RESET 0x10EC
1403 /* System Clock Source */
1407 RT5677_SCLK_S_RCCLK,
1413 RT5677_PLL1_S_BCLK1,
1414 RT5677_PLL1_S_BCLK2,
1415 RT5677_PLL1_S_BCLK3,
1416 RT5677_PLL1_S_BCLK4,
1428 #endif /* __DRIVERS_SOUND_RT5677_H__ */
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