2 * drivers/soc/tegra/pmc.c
4 * Copyright (c) 2010 Google, Inc
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #define pr_fmt(fmt) "tegra-pmc: " fmt
22 #include <linux/kernel.h>
23 #include <linux/clk.h>
24 #include <linux/clk/tegra.h>
25 #include <linux/debugfs.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <linux/export.h>
29 #include <linux/init.h>
31 #include <linux/iopoll.h>
33 #include <linux/of_address.h>
34 #include <linux/of_platform.h>
35 #include <linux/platform_device.h>
36 #include <linux/pm_domain.h>
37 #include <linux/reboot.h>
38 #include <linux/reset.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
43 #include <soc/tegra/common.h>
44 #include <soc/tegra/fuse.h>
45 #include <soc/tegra/pmc.h>
48 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
49 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
50 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
51 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
52 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
53 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
54 #define PMC_CNTRL_MAIN_RST BIT(4)
56 #define DPD_SAMPLE 0x020
57 #define DPD_SAMPLE_ENABLE BIT(0)
58 #define DPD_SAMPLE_DISABLE (0 << 0)
60 #define PWRGATE_TOGGLE 0x30
61 #define PWRGATE_TOGGLE_START BIT(8)
63 #define REMOVE_CLAMPING 0x34
65 #define PWRGATE_STATUS 0x38
67 #define PMC_PWR_DET 0x48
69 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
70 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
71 #define PMC_SCRATCH0_MODE_RCM BIT(1)
72 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
73 PMC_SCRATCH0_MODE_BOOTLOADER | \
74 PMC_SCRATCH0_MODE_RCM)
76 #define PMC_CPUPWRGOOD_TIMER 0xc8
77 #define PMC_CPUPWROFF_TIMER 0xcc
79 #define PMC_PWR_DET_VALUE 0xe4
81 #define PMC_SCRATCH41 0x140
83 #define PMC_SENSOR_CTRL 0x1b0
84 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
85 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
87 #define PMC_RST_STATUS 0x1b4
88 #define PMC_RST_STATUS_POR 0
89 #define PMC_RST_STATUS_WATCHDOG 1
90 #define PMC_RST_STATUS_SENSOR 2
91 #define PMC_RST_STATUS_SW_MAIN 3
92 #define PMC_RST_STATUS_LP0 4
93 #define PMC_RST_STATUS_AOTAG 5
95 #define IO_DPD_REQ 0x1b8
96 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
97 #define IO_DPD_REQ_CODE_OFF (1U << 30)
98 #define IO_DPD_REQ_CODE_ON (2U << 30)
99 #define IO_DPD_REQ_CODE_MASK (3U << 30)
101 #define IO_DPD_STATUS 0x1bc
102 #define IO_DPD2_REQ 0x1c0
103 #define IO_DPD2_STATUS 0x1c4
104 #define SEL_DPD_TIM 0x1c8
106 #define PMC_SCRATCH54 0x258
107 #define PMC_SCRATCH54_DATA_SHIFT 8
108 #define PMC_SCRATCH54_ADDR_SHIFT 0
110 #define PMC_SCRATCH55 0x25c
111 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
112 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
113 #define PMC_SCRATCH55_PINMUX_SHIFT 24
114 #define PMC_SCRATCH55_16BITOP BIT(15)
115 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
116 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
118 #define GPU_RG_CNTRL 0x2d4
120 /* Tegra186 and later */
121 #define WAKE_AOWAKE_CTRL 0x4f4
122 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
124 struct tegra_powergate {
125 struct generic_pm_domain genpd;
126 struct tegra_pmc *pmc;
129 unsigned int num_clks;
130 struct reset_control *reset;
133 struct tegra_io_pad_soc {
134 enum tegra_io_pad id;
136 unsigned int voltage;
139 struct tegra_pmc_regs {
140 unsigned int scratch0;
141 unsigned int dpd_req;
142 unsigned int dpd_status;
143 unsigned int dpd2_req;
144 unsigned int dpd2_status;
147 struct tegra_pmc_soc {
148 unsigned int num_powergates;
149 const char *const *powergates;
150 unsigned int num_cpu_powergates;
151 const u8 *cpu_powergates;
153 bool has_tsense_reset;
155 bool needs_mbist_war;
157 const struct tegra_io_pad_soc *io_pads;
158 unsigned int num_io_pads;
160 const struct tegra_pmc_regs *regs;
161 void (*init)(struct tegra_pmc *pmc);
162 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
163 struct device_node *np,
168 * struct tegra_pmc - NVIDIA Tegra PMC
169 * @dev: pointer to PMC device structure
170 * @base: pointer to I/O remapped register region
171 * @clk: pointer to pclk clock
172 * @soc: pointer to SoC data structure
173 * @debugfs: pointer to debugfs entry
174 * @rate: currently configured rate of pclk
175 * @suspend_mode: lowest suspend mode available
176 * @cpu_good_time: CPU power good time (in microseconds)
177 * @cpu_off_time: CPU power off time (in microsecends)
178 * @core_osc_time: core power good OSC time (in microseconds)
179 * @core_pmu_time: core power good PMU time (in microseconds)
180 * @core_off_time: core power off time (in microseconds)
181 * @corereq_high: core power request is active-high
182 * @sysclkreq_high: system clock request is active-high
183 * @combined_req: combined power request for CPU & core
184 * @cpu_pwr_good_en: CPU power good signal is enabled
185 * @lp0_vec_phys: physical base address of the LP0 warm boot code
186 * @lp0_vec_size: size of the LP0 warm boot code
187 * @powergates_available: Bitmap of available power gates
188 * @powergates_lock: mutex for power gate register access
195 void __iomem *scratch;
197 struct dentry *debugfs;
199 const struct tegra_pmc_soc *soc;
203 enum tegra_suspend_mode suspend_mode;
212 bool cpu_pwr_good_en;
215 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
217 struct mutex powergates_lock;
220 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
222 .suspend_mode = TEGRA_SUSPEND_NONE,
225 static inline struct tegra_powergate *
226 to_powergate(struct generic_pm_domain *domain)
228 return container_of(domain, struct tegra_powergate, genpd);
231 static u32 tegra_pmc_readl(unsigned long offset)
233 return readl(pmc->base + offset);
236 static void tegra_pmc_writel(u32 value, unsigned long offset)
238 writel(value, pmc->base + offset);
241 static inline bool tegra_powergate_state(int id)
243 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
244 return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0;
246 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0;
249 static inline bool tegra_powergate_is_valid(int id)
251 return (pmc->soc && pmc->soc->powergates[id]);
254 static inline bool tegra_powergate_is_available(int id)
256 return test_bit(id, pmc->powergates_available);
259 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
263 if (!pmc || !pmc->soc || !name)
266 for (i = 0; i < pmc->soc->num_powergates; i++) {
267 if (!tegra_powergate_is_valid(i))
270 if (!strcmp(name, pmc->soc->powergates[i]))
278 * tegra_powergate_set() - set the state of a partition
280 * @new_state: new state of the partition
282 static int tegra_powergate_set(unsigned int id, bool new_state)
287 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
290 mutex_lock(&pmc->powergates_lock);
292 if (tegra_powergate_state(id) == new_state) {
293 mutex_unlock(&pmc->powergates_lock);
297 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
299 err = readx_poll_timeout(tegra_powergate_state, id, status,
300 status == new_state, 10, 100000);
302 mutex_unlock(&pmc->powergates_lock);
307 static int __tegra_powergate_remove_clamping(unsigned int id)
311 mutex_lock(&pmc->powergates_lock);
314 * On Tegra124 and later, the clamps for the GPU are controlled by a
315 * separate register (with different semantics).
317 if (id == TEGRA_POWERGATE_3D) {
318 if (pmc->soc->has_gpu_clamps) {
319 tegra_pmc_writel(0, GPU_RG_CNTRL);
325 * Tegra 2 has a bug where PCIE and VDE clamping masks are
326 * swapped relatively to the partition ids
328 if (id == TEGRA_POWERGATE_VDEC)
329 mask = (1 << TEGRA_POWERGATE_PCIE);
330 else if (id == TEGRA_POWERGATE_PCIE)
331 mask = (1 << TEGRA_POWERGATE_VDEC);
335 tegra_pmc_writel(mask, REMOVE_CLAMPING);
338 mutex_unlock(&pmc->powergates_lock);
343 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
347 for (i = 0; i < pg->num_clks; i++)
348 clk_disable_unprepare(pg->clks[i]);
351 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
356 for (i = 0; i < pg->num_clks; i++) {
357 err = clk_prepare_enable(pg->clks[i]);
366 clk_disable_unprepare(pg->clks[i]);
371 int __weak tegra210_clk_handle_mbist_war(unsigned int id)
376 static int tegra_powergate_power_up(struct tegra_powergate *pg,
381 err = reset_control_assert(pg->reset);
385 usleep_range(10, 20);
387 err = tegra_powergate_set(pg->id, true);
391 usleep_range(10, 20);
393 err = tegra_powergate_enable_clocks(pg);
397 usleep_range(10, 20);
399 err = __tegra_powergate_remove_clamping(pg->id);
403 usleep_range(10, 20);
405 err = reset_control_deassert(pg->reset);
409 usleep_range(10, 20);
411 if (pg->pmc->soc->needs_mbist_war)
412 err = tegra210_clk_handle_mbist_war(pg->id);
417 tegra_powergate_disable_clocks(pg);
422 tegra_powergate_disable_clocks(pg);
423 usleep_range(10, 20);
426 tegra_powergate_set(pg->id, false);
431 static int tegra_powergate_power_down(struct tegra_powergate *pg)
435 err = tegra_powergate_enable_clocks(pg);
439 usleep_range(10, 20);
441 err = reset_control_assert(pg->reset);
445 usleep_range(10, 20);
447 tegra_powergate_disable_clocks(pg);
449 usleep_range(10, 20);
451 err = tegra_powergate_set(pg->id, false);
458 tegra_powergate_enable_clocks(pg);
459 usleep_range(10, 20);
460 reset_control_deassert(pg->reset);
461 usleep_range(10, 20);
464 tegra_powergate_disable_clocks(pg);
469 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
471 struct tegra_powergate *pg = to_powergate(domain);
474 err = tegra_powergate_power_up(pg, true);
476 pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name,
482 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
484 struct tegra_powergate *pg = to_powergate(domain);
487 err = tegra_powergate_power_down(pg);
489 pr_err("failed to turn off PM domain %s: %d\n",
490 pg->genpd.name, err);
496 * tegra_powergate_power_on() - power on partition
499 int tegra_powergate_power_on(unsigned int id)
501 if (!tegra_powergate_is_available(id))
504 return tegra_powergate_set(id, true);
508 * tegra_powergate_power_off() - power off partition
511 int tegra_powergate_power_off(unsigned int id)
513 if (!tegra_powergate_is_available(id))
516 return tegra_powergate_set(id, false);
518 EXPORT_SYMBOL(tegra_powergate_power_off);
521 * tegra_powergate_is_powered() - check if partition is powered
524 int tegra_powergate_is_powered(unsigned int id)
528 if (!tegra_powergate_is_valid(id))
531 mutex_lock(&pmc->powergates_lock);
532 status = tegra_powergate_state(id);
533 mutex_unlock(&pmc->powergates_lock);
539 * tegra_powergate_remove_clamping() - remove power clamps for partition
542 int tegra_powergate_remove_clamping(unsigned int id)
544 if (!tegra_powergate_is_available(id))
547 return __tegra_powergate_remove_clamping(id);
549 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
552 * tegra_powergate_sequence_power_up() - power up partition
554 * @clk: clock for partition
555 * @rst: reset for partition
557 * Must be called with clk disabled, and returns with clk enabled.
559 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
560 struct reset_control *rst)
562 struct tegra_powergate pg;
565 if (!tegra_powergate_is_available(id))
574 err = tegra_powergate_power_up(&pg, false);
576 pr_err("failed to turn on partition %d: %d\n", id, err);
580 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
584 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
585 * @cpuid: CPU partition ID
587 * Returns the partition ID corresponding to the CPU partition ID or a
588 * negative error code on failure.
590 static int tegra_get_cpu_powergate_id(unsigned int cpuid)
592 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
593 return pmc->soc->cpu_powergates[cpuid];
599 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
600 * @cpuid: CPU partition ID
602 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
606 id = tegra_get_cpu_powergate_id(cpuid);
610 return tegra_powergate_is_powered(id);
614 * tegra_pmc_cpu_power_on() - power on CPU partition
615 * @cpuid: CPU partition ID
617 int tegra_pmc_cpu_power_on(unsigned int cpuid)
621 id = tegra_get_cpu_powergate_id(cpuid);
625 return tegra_powergate_set(id, true);
629 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
630 * @cpuid: CPU partition ID
632 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
636 id = tegra_get_cpu_powergate_id(cpuid);
640 return tegra_powergate_remove_clamping(id);
642 #endif /* CONFIG_SMP */
644 static int tegra_pmc_restart_notify(struct notifier_block *this,
645 unsigned long action, void *data)
647 const char *cmd = data;
650 value = readl(pmc->scratch + pmc->soc->regs->scratch0);
651 value &= ~PMC_SCRATCH0_MODE_MASK;
654 if (strcmp(cmd, "recovery") == 0)
655 value |= PMC_SCRATCH0_MODE_RECOVERY;
657 if (strcmp(cmd, "bootloader") == 0)
658 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
660 if (strcmp(cmd, "forced-recovery") == 0)
661 value |= PMC_SCRATCH0_MODE_RCM;
664 writel(value, pmc->scratch + pmc->soc->regs->scratch0);
666 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
667 value = tegra_pmc_readl(PMC_CNTRL);
668 value |= PMC_CNTRL_MAIN_RST;
669 tegra_pmc_writel(value, PMC_CNTRL);
674 static struct notifier_block tegra_pmc_restart_handler = {
675 .notifier_call = tegra_pmc_restart_notify,
679 static int powergate_show(struct seq_file *s, void *data)
684 seq_printf(s, " powergate powered\n");
685 seq_printf(s, "------------------\n");
687 for (i = 0; i < pmc->soc->num_powergates; i++) {
688 status = tegra_powergate_is_powered(i);
692 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
693 status ? "yes" : "no");
699 static int powergate_open(struct inode *inode, struct file *file)
701 return single_open(file, powergate_show, inode->i_private);
704 static const struct file_operations powergate_fops = {
705 .open = powergate_open,
708 .release = single_release,
711 static int tegra_powergate_debugfs_init(void)
713 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
721 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
722 struct device_node *np)
725 unsigned int i, count;
728 count = of_count_phandle_with_args(np, "clocks", "#clock-cells");
732 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
736 for (i = 0; i < count; i++) {
737 pg->clks[i] = of_clk_get(np, i);
738 if (IS_ERR(pg->clks[i])) {
739 err = PTR_ERR(pg->clks[i]);
744 pg->num_clks = count;
750 clk_put(pg->clks[i]);
757 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
758 struct device_node *np, bool off)
762 pg->reset = of_reset_control_array_get_exclusive(np);
763 if (IS_ERR(pg->reset)) {
764 err = PTR_ERR(pg->reset);
765 pr_err("failed to get device resets: %d\n", err);
770 err = reset_control_assert(pg->reset);
772 err = reset_control_deassert(pg->reset);
775 reset_control_put(pg->reset);
780 static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
782 struct tegra_powergate *pg;
786 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
790 id = tegra_powergate_lookup(pmc, np->name);
792 pr_err("powergate lookup failed for %s: %d\n", np->name, id);
797 * Clear the bit for this powergate so it cannot be managed
798 * directly via the legacy APIs for controlling powergates.
800 clear_bit(id, pmc->powergates_available);
803 pg->genpd.name = np->name;
804 pg->genpd.power_off = tegra_genpd_power_off;
805 pg->genpd.power_on = tegra_genpd_power_on;
808 off = !tegra_powergate_is_powered(pg->id);
810 err = tegra_powergate_of_get_clks(pg, np);
812 pr_err("failed to get clocks for %s: %d\n", np->name, err);
816 err = tegra_powergate_of_get_resets(pg, np, off);
818 pr_err("failed to get resets for %s: %d\n", np->name, err);
822 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
824 WARN_ON(tegra_powergate_power_up(pg, true));
830 * FIXME: If XHCI is enabled for Tegra, then power-up the XUSB
831 * host and super-speed partitions. Once the XHCI driver
832 * manages the partitions itself this code can be removed. Note
833 * that we don't register these partitions with the genpd core
834 * to avoid it from powering down the partitions as they appear
837 if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) &&
838 (id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC)) {
840 WARN_ON(tegra_powergate_power_up(pg, true));
845 err = pm_genpd_init(&pg->genpd, NULL, off);
847 pr_err("failed to initialise PM domain %s: %d\n", np->name,
852 err = of_genpd_add_provider_simple(np, &pg->genpd);
854 pr_err("failed to add PM domain provider for %s: %d\n",
859 pr_debug("added PM domain %s\n", pg->genpd.name);
864 pm_genpd_remove(&pg->genpd);
867 reset_control_put(pg->reset);
870 while (pg->num_clks--)
871 clk_put(pg->clks[pg->num_clks]);
876 set_bit(id, pmc->powergates_available);
882 static void tegra_powergate_init(struct tegra_pmc *pmc,
883 struct device_node *parent)
885 struct device_node *np, *child;
888 /* Create a bitmap of the available and valid partitions */
889 for (i = 0; i < pmc->soc->num_powergates; i++)
890 if (pmc->soc->powergates[i])
891 set_bit(i, pmc->powergates_available);
893 np = of_get_child_by_name(parent, "powergates");
897 for_each_child_of_node(np, child)
898 tegra_powergate_add(pmc, child);
903 static const struct tegra_io_pad_soc *
904 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
908 for (i = 0; i < pmc->soc->num_io_pads; i++)
909 if (pmc->soc->io_pads[i].id == id)
910 return &pmc->soc->io_pads[i];
915 static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request,
916 unsigned long *status, u32 *mask)
918 const struct tegra_io_pad_soc *pad;
919 unsigned long rate, value;
921 pad = tegra_io_pad_find(pmc, id);
923 pr_err("invalid I/O pad ID %u\n", id);
927 if (pad->dpd == UINT_MAX)
930 *mask = BIT(pad->dpd % 32);
933 *status = pmc->soc->regs->dpd_status;
934 *request = pmc->soc->regs->dpd_req;
936 *status = pmc->soc->regs->dpd2_status;
937 *request = pmc->soc->regs->dpd2_req;
941 rate = clk_get_rate(pmc->clk);
943 pr_err("failed to get clock rate\n");
947 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
949 /* must be at least 200 ns, in APB (PCLK) clock cycles */
950 value = DIV_ROUND_UP(1000000000, rate);
951 value = DIV_ROUND_UP(200, value);
952 tegra_pmc_writel(value, SEL_DPD_TIM);
958 static int tegra_io_pad_poll(unsigned long offset, u32 mask,
959 u32 val, unsigned long timeout)
963 timeout = jiffies + msecs_to_jiffies(timeout);
965 while (time_after(timeout, jiffies)) {
966 value = tegra_pmc_readl(offset);
967 if ((value & mask) == val)
970 usleep_range(250, 1000);
976 static void tegra_io_pad_unprepare(void)
979 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
983 * tegra_io_pad_power_enable() - enable power to I/O pad
984 * @id: Tegra I/O pad ID for which to enable power
986 * Returns: 0 on success or a negative error code on failure.
988 int tegra_io_pad_power_enable(enum tegra_io_pad id)
990 unsigned long request, status;
994 mutex_lock(&pmc->powergates_lock);
996 err = tegra_io_pad_prepare(id, &request, &status, &mask);
998 pr_err("failed to prepare I/O pad: %d\n", err);
1002 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | mask, request);
1004 err = tegra_io_pad_poll(status, mask, 0, 250);
1006 pr_err("failed to enable I/O pad: %d\n", err);
1010 tegra_io_pad_unprepare();
1013 mutex_unlock(&pmc->powergates_lock);
1016 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1019 * tegra_io_pad_power_disable() - disable power to I/O pad
1020 * @id: Tegra I/O pad ID for which to disable power
1022 * Returns: 0 on success or a negative error code on failure.
1024 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1026 unsigned long request, status;
1030 mutex_lock(&pmc->powergates_lock);
1032 err = tegra_io_pad_prepare(id, &request, &status, &mask);
1034 pr_err("failed to prepare I/O pad: %d\n", err);
1038 tegra_pmc_writel(IO_DPD_REQ_CODE_ON | mask, request);
1040 err = tegra_io_pad_poll(status, mask, mask, 250);
1042 pr_err("failed to disable I/O pad: %d\n", err);
1046 tegra_io_pad_unprepare();
1049 mutex_unlock(&pmc->powergates_lock);
1052 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1054 int tegra_io_pad_set_voltage(enum tegra_io_pad id,
1055 enum tegra_io_pad_voltage voltage)
1057 const struct tegra_io_pad_soc *pad;
1060 pad = tegra_io_pad_find(pmc, id);
1064 if (pad->voltage == UINT_MAX)
1067 mutex_lock(&pmc->powergates_lock);
1069 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1070 value = tegra_pmc_readl(PMC_PWR_DET);
1071 value |= BIT(pad->voltage);
1072 tegra_pmc_writel(value, PMC_PWR_DET);
1074 /* update I/O voltage */
1075 value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
1077 if (voltage == TEGRA_IO_PAD_1800000UV)
1078 value &= ~BIT(pad->voltage);
1080 value |= BIT(pad->voltage);
1082 tegra_pmc_writel(value, PMC_PWR_DET_VALUE);
1084 mutex_unlock(&pmc->powergates_lock);
1086 usleep_range(100, 250);
1090 EXPORT_SYMBOL(tegra_io_pad_set_voltage);
1092 int tegra_io_pad_get_voltage(enum tegra_io_pad id)
1094 const struct tegra_io_pad_soc *pad;
1097 pad = tegra_io_pad_find(pmc, id);
1101 if (pad->voltage == UINT_MAX)
1104 value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
1106 if ((value & BIT(pad->voltage)) == 0)
1107 return TEGRA_IO_PAD_1800000UV;
1109 return TEGRA_IO_PAD_3300000UV;
1111 EXPORT_SYMBOL(tegra_io_pad_get_voltage);
1114 * tegra_io_rail_power_on() - enable power to I/O rail
1115 * @id: Tegra I/O pad ID for which to enable power
1117 * See also: tegra_io_pad_power_enable()
1119 int tegra_io_rail_power_on(unsigned int id)
1121 return tegra_io_pad_power_enable(id);
1123 EXPORT_SYMBOL(tegra_io_rail_power_on);
1126 * tegra_io_rail_power_off() - disable power to I/O rail
1127 * @id: Tegra I/O pad ID for which to disable power
1129 * See also: tegra_io_pad_power_disable()
1131 int tegra_io_rail_power_off(unsigned int id)
1133 return tegra_io_pad_power_disable(id);
1135 EXPORT_SYMBOL(tegra_io_rail_power_off);
1137 #ifdef CONFIG_PM_SLEEP
1138 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1140 return pmc->suspend_mode;
1143 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1145 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1148 pmc->suspend_mode = mode;
1151 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1153 unsigned long long rate = 0;
1157 case TEGRA_SUSPEND_LP1:
1161 case TEGRA_SUSPEND_LP2:
1162 rate = clk_get_rate(pmc->clk);
1169 if (WARN_ON_ONCE(rate == 0))
1172 if (rate != pmc->rate) {
1175 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1176 do_div(ticks, USEC_PER_SEC);
1177 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER);
1179 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1180 do_div(ticks, USEC_PER_SEC);
1181 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER);
1188 value = tegra_pmc_readl(PMC_CNTRL);
1189 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1190 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1191 tegra_pmc_writel(value, PMC_CNTRL);
1195 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1197 u32 value, values[2];
1199 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1203 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1207 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1211 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1215 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1220 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1222 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1223 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1225 pmc->cpu_good_time = value;
1227 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1228 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1230 pmc->cpu_off_time = value;
1232 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1233 values, ARRAY_SIZE(values)))
1234 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1236 pmc->core_osc_time = values[0];
1237 pmc->core_pmu_time = values[1];
1239 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1240 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1242 pmc->core_off_time = value;
1244 pmc->corereq_high = of_property_read_bool(np,
1245 "nvidia,core-power-req-active-high");
1247 pmc->sysclkreq_high = of_property_read_bool(np,
1248 "nvidia,sys-clock-req-active-high");
1250 pmc->combined_req = of_property_read_bool(np,
1251 "nvidia,combined-power-req");
1253 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1254 "nvidia,cpu-pwr-good-en");
1256 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1257 ARRAY_SIZE(values)))
1258 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1259 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1261 pmc->lp0_vec_phys = values[0];
1262 pmc->lp0_vec_size = values[1];
1267 static void tegra_pmc_init(struct tegra_pmc *pmc)
1270 pmc->soc->init(pmc);
1273 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1275 static const char disabled[] = "emergency thermal reset disabled";
1276 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1277 struct device *dev = pmc->dev;
1278 struct device_node *np;
1279 u32 value, checksum;
1281 if (!pmc->soc->has_tsense_reset)
1284 np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip");
1286 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1290 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1291 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1295 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1296 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1300 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1301 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1305 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
1306 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1310 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1313 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
1314 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1315 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
1317 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1318 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1319 tegra_pmc_writel(value, PMC_SCRATCH54);
1321 value = PMC_SCRATCH55_RESET_TEGRA;
1322 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1323 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1324 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1327 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1328 * contain the checksum and are currently zero, so they are not added.
1330 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1331 + ((value >> 24) & 0xff);
1333 checksum = 0x100 - checksum;
1335 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1337 tegra_pmc_writel(value, PMC_SCRATCH55);
1339 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
1340 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1341 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
1343 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1349 static int tegra_pmc_probe(struct platform_device *pdev)
1352 struct resource *res;
1356 * Early initialisation should have configured an initial
1357 * register mapping and setup the soc data pointer. If these
1358 * are not valid then something went badly wrong!
1360 if (WARN_ON(!pmc->base || !pmc->soc))
1363 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
1367 /* take over the memory region from the early initialization */
1368 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1369 base = devm_ioremap_resource(&pdev->dev, res);
1371 return PTR_ERR(base);
1373 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
1375 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
1376 if (IS_ERR(pmc->wake))
1377 return PTR_ERR(pmc->wake);
1382 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
1384 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
1385 if (IS_ERR(pmc->aotag))
1386 return PTR_ERR(pmc->aotag);
1391 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
1393 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
1394 if (IS_ERR(pmc->scratch))
1395 return PTR_ERR(pmc->scratch);
1397 pmc->scratch = base;
1400 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
1401 if (IS_ERR(pmc->clk)) {
1402 err = PTR_ERR(pmc->clk);
1404 if (err != -ENOENT) {
1405 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
1412 pmc->dev = &pdev->dev;
1414 tegra_pmc_init(pmc);
1416 tegra_pmc_init_tsense_reset(pmc);
1418 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1419 err = tegra_powergate_debugfs_init();
1424 err = register_restart_handler(&tegra_pmc_restart_handler);
1426 debugfs_remove(pmc->debugfs);
1427 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
1432 mutex_lock(&pmc->powergates_lock);
1435 mutex_unlock(&pmc->powergates_lock);
1440 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1441 static int tegra_pmc_suspend(struct device *dev)
1443 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
1448 static int tegra_pmc_resume(struct device *dev)
1450 tegra_pmc_writel(0x0, PMC_SCRATCH41);
1455 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
1459 static const char * const tegra20_powergates[] = {
1460 [TEGRA_POWERGATE_CPU] = "cpu",
1461 [TEGRA_POWERGATE_3D] = "3d",
1462 [TEGRA_POWERGATE_VENC] = "venc",
1463 [TEGRA_POWERGATE_VDEC] = "vdec",
1464 [TEGRA_POWERGATE_PCIE] = "pcie",
1465 [TEGRA_POWERGATE_L2] = "l2",
1466 [TEGRA_POWERGATE_MPE] = "mpe",
1469 static const struct tegra_pmc_regs tegra20_pmc_regs = {
1472 .dpd_status = 0x1bc,
1474 .dpd2_status = 0x1c4,
1477 static void tegra20_pmc_init(struct tegra_pmc *pmc)
1481 /* Always enable CPU power request */
1482 value = tegra_pmc_readl(PMC_CNTRL);
1483 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1484 tegra_pmc_writel(value, PMC_CNTRL);
1486 value = tegra_pmc_readl(PMC_CNTRL);
1488 if (pmc->sysclkreq_high)
1489 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
1491 value |= PMC_CNTRL_SYSCLK_POLARITY;
1493 /* configure the output polarity while the request is tristated */
1494 tegra_pmc_writel(value, PMC_CNTRL);
1496 /* now enable the request */
1497 value = tegra_pmc_readl(PMC_CNTRL);
1498 value |= PMC_CNTRL_SYSCLK_OE;
1499 tegra_pmc_writel(value, PMC_CNTRL);
1502 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
1503 struct device_node *np,
1508 value = tegra_pmc_readl(PMC_CNTRL);
1511 value |= PMC_CNTRL_INTR_POLARITY;
1513 value &= ~PMC_CNTRL_INTR_POLARITY;
1515 tegra_pmc_writel(value, PMC_CNTRL);
1518 static const struct tegra_pmc_soc tegra20_pmc_soc = {
1519 .num_powergates = ARRAY_SIZE(tegra20_powergates),
1520 .powergates = tegra20_powergates,
1521 .num_cpu_powergates = 0,
1522 .cpu_powergates = NULL,
1523 .has_tsense_reset = false,
1524 .has_gpu_clamps = false,
1527 .regs = &tegra20_pmc_regs,
1528 .init = tegra20_pmc_init,
1529 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
1532 static const char * const tegra30_powergates[] = {
1533 [TEGRA_POWERGATE_CPU] = "cpu0",
1534 [TEGRA_POWERGATE_3D] = "3d0",
1535 [TEGRA_POWERGATE_VENC] = "venc",
1536 [TEGRA_POWERGATE_VDEC] = "vdec",
1537 [TEGRA_POWERGATE_PCIE] = "pcie",
1538 [TEGRA_POWERGATE_L2] = "l2",
1539 [TEGRA_POWERGATE_MPE] = "mpe",
1540 [TEGRA_POWERGATE_HEG] = "heg",
1541 [TEGRA_POWERGATE_SATA] = "sata",
1542 [TEGRA_POWERGATE_CPU1] = "cpu1",
1543 [TEGRA_POWERGATE_CPU2] = "cpu2",
1544 [TEGRA_POWERGATE_CPU3] = "cpu3",
1545 [TEGRA_POWERGATE_CELP] = "celp",
1546 [TEGRA_POWERGATE_3D1] = "3d1",
1549 static const u8 tegra30_cpu_powergates[] = {
1550 TEGRA_POWERGATE_CPU,
1551 TEGRA_POWERGATE_CPU1,
1552 TEGRA_POWERGATE_CPU2,
1553 TEGRA_POWERGATE_CPU3,
1556 static const struct tegra_pmc_soc tegra30_pmc_soc = {
1557 .num_powergates = ARRAY_SIZE(tegra30_powergates),
1558 .powergates = tegra30_powergates,
1559 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
1560 .cpu_powergates = tegra30_cpu_powergates,
1561 .has_tsense_reset = true,
1562 .has_gpu_clamps = false,
1565 .regs = &tegra20_pmc_regs,
1566 .init = tegra20_pmc_init,
1567 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
1570 static const char * const tegra114_powergates[] = {
1571 [TEGRA_POWERGATE_CPU] = "crail",
1572 [TEGRA_POWERGATE_3D] = "3d",
1573 [TEGRA_POWERGATE_VENC] = "venc",
1574 [TEGRA_POWERGATE_VDEC] = "vdec",
1575 [TEGRA_POWERGATE_MPE] = "mpe",
1576 [TEGRA_POWERGATE_HEG] = "heg",
1577 [TEGRA_POWERGATE_CPU1] = "cpu1",
1578 [TEGRA_POWERGATE_CPU2] = "cpu2",
1579 [TEGRA_POWERGATE_CPU3] = "cpu3",
1580 [TEGRA_POWERGATE_CELP] = "celp",
1581 [TEGRA_POWERGATE_CPU0] = "cpu0",
1582 [TEGRA_POWERGATE_C0NC] = "c0nc",
1583 [TEGRA_POWERGATE_C1NC] = "c1nc",
1584 [TEGRA_POWERGATE_DIS] = "dis",
1585 [TEGRA_POWERGATE_DISB] = "disb",
1586 [TEGRA_POWERGATE_XUSBA] = "xusba",
1587 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1588 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1591 static const u8 tegra114_cpu_powergates[] = {
1592 TEGRA_POWERGATE_CPU0,
1593 TEGRA_POWERGATE_CPU1,
1594 TEGRA_POWERGATE_CPU2,
1595 TEGRA_POWERGATE_CPU3,
1598 static const struct tegra_pmc_soc tegra114_pmc_soc = {
1599 .num_powergates = ARRAY_SIZE(tegra114_powergates),
1600 .powergates = tegra114_powergates,
1601 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
1602 .cpu_powergates = tegra114_cpu_powergates,
1603 .has_tsense_reset = true,
1604 .has_gpu_clamps = false,
1607 .regs = &tegra20_pmc_regs,
1608 .init = tegra20_pmc_init,
1609 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
1612 static const char * const tegra124_powergates[] = {
1613 [TEGRA_POWERGATE_CPU] = "crail",
1614 [TEGRA_POWERGATE_3D] = "3d",
1615 [TEGRA_POWERGATE_VENC] = "venc",
1616 [TEGRA_POWERGATE_PCIE] = "pcie",
1617 [TEGRA_POWERGATE_VDEC] = "vdec",
1618 [TEGRA_POWERGATE_MPE] = "mpe",
1619 [TEGRA_POWERGATE_HEG] = "heg",
1620 [TEGRA_POWERGATE_SATA] = "sata",
1621 [TEGRA_POWERGATE_CPU1] = "cpu1",
1622 [TEGRA_POWERGATE_CPU2] = "cpu2",
1623 [TEGRA_POWERGATE_CPU3] = "cpu3",
1624 [TEGRA_POWERGATE_CELP] = "celp",
1625 [TEGRA_POWERGATE_CPU0] = "cpu0",
1626 [TEGRA_POWERGATE_C0NC] = "c0nc",
1627 [TEGRA_POWERGATE_C1NC] = "c1nc",
1628 [TEGRA_POWERGATE_SOR] = "sor",
1629 [TEGRA_POWERGATE_DIS] = "dis",
1630 [TEGRA_POWERGATE_DISB] = "disb",
1631 [TEGRA_POWERGATE_XUSBA] = "xusba",
1632 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1633 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1634 [TEGRA_POWERGATE_VIC] = "vic",
1635 [TEGRA_POWERGATE_IRAM] = "iram",
1638 static const u8 tegra124_cpu_powergates[] = {
1639 TEGRA_POWERGATE_CPU0,
1640 TEGRA_POWERGATE_CPU1,
1641 TEGRA_POWERGATE_CPU2,
1642 TEGRA_POWERGATE_CPU3,
1645 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
1646 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
1647 { .id = TEGRA_IO_PAD_BB, .dpd = 15, .voltage = UINT_MAX },
1648 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = UINT_MAX },
1649 { .id = TEGRA_IO_PAD_COMP, .dpd = 22, .voltage = UINT_MAX },
1650 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1651 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1652 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
1653 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1654 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
1655 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
1656 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
1657 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
1658 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1659 { .id = TEGRA_IO_PAD_HV, .dpd = 38, .voltage = UINT_MAX },
1660 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
1661 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1662 { .id = TEGRA_IO_PAD_NAND, .dpd = 13, .voltage = UINT_MAX },
1663 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
1664 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
1665 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1666 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
1667 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = UINT_MAX },
1668 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = UINT_MAX },
1669 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 35, .voltage = UINT_MAX },
1670 { .id = TEGRA_IO_PAD_SYS_DDC, .dpd = 58, .voltage = UINT_MAX },
1671 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
1672 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1673 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1674 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1675 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1678 static const struct tegra_pmc_soc tegra124_pmc_soc = {
1679 .num_powergates = ARRAY_SIZE(tegra124_powergates),
1680 .powergates = tegra124_powergates,
1681 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
1682 .cpu_powergates = tegra124_cpu_powergates,
1683 .has_tsense_reset = true,
1684 .has_gpu_clamps = true,
1685 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
1686 .io_pads = tegra124_io_pads,
1687 .regs = &tegra20_pmc_regs,
1688 .init = tegra20_pmc_init,
1689 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
1692 static const char * const tegra210_powergates[] = {
1693 [TEGRA_POWERGATE_CPU] = "crail",
1694 [TEGRA_POWERGATE_3D] = "3d",
1695 [TEGRA_POWERGATE_VENC] = "venc",
1696 [TEGRA_POWERGATE_PCIE] = "pcie",
1697 [TEGRA_POWERGATE_MPE] = "mpe",
1698 [TEGRA_POWERGATE_SATA] = "sata",
1699 [TEGRA_POWERGATE_CPU1] = "cpu1",
1700 [TEGRA_POWERGATE_CPU2] = "cpu2",
1701 [TEGRA_POWERGATE_CPU3] = "cpu3",
1702 [TEGRA_POWERGATE_CPU0] = "cpu0",
1703 [TEGRA_POWERGATE_C0NC] = "c0nc",
1704 [TEGRA_POWERGATE_SOR] = "sor",
1705 [TEGRA_POWERGATE_DIS] = "dis",
1706 [TEGRA_POWERGATE_DISB] = "disb",
1707 [TEGRA_POWERGATE_XUSBA] = "xusba",
1708 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1709 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1710 [TEGRA_POWERGATE_VIC] = "vic",
1711 [TEGRA_POWERGATE_IRAM] = "iram",
1712 [TEGRA_POWERGATE_NVDEC] = "nvdec",
1713 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
1714 [TEGRA_POWERGATE_AUD] = "aud",
1715 [TEGRA_POWERGATE_DFD] = "dfd",
1716 [TEGRA_POWERGATE_VE2] = "ve2",
1719 static const u8 tegra210_cpu_powergates[] = {
1720 TEGRA_POWERGATE_CPU0,
1721 TEGRA_POWERGATE_CPU1,
1722 TEGRA_POWERGATE_CPU2,
1723 TEGRA_POWERGATE_CPU3,
1726 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
1727 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = 5 },
1728 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 18 },
1729 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = 10 },
1730 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1731 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1732 { .id = TEGRA_IO_PAD_CSIC, .dpd = 42, .voltage = UINT_MAX },
1733 { .id = TEGRA_IO_PAD_CSID, .dpd = 43, .voltage = UINT_MAX },
1734 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
1735 { .id = TEGRA_IO_PAD_CSIF, .dpd = 45, .voltage = UINT_MAX },
1736 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = 19 },
1737 { .id = TEGRA_IO_PAD_DEBUG_NONAO, .dpd = 26, .voltage = UINT_MAX },
1738 { .id = TEGRA_IO_PAD_DMIC, .dpd = 50, .voltage = 20 },
1739 { .id = TEGRA_IO_PAD_DP, .dpd = 51, .voltage = UINT_MAX },
1740 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1741 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
1742 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
1743 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
1744 { .id = TEGRA_IO_PAD_EMMC, .dpd = 35, .voltage = UINT_MAX },
1745 { .id = TEGRA_IO_PAD_EMMC2, .dpd = 37, .voltage = UINT_MAX },
1746 { .id = TEGRA_IO_PAD_GPIO, .dpd = 27, .voltage = 21 },
1747 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
1748 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1749 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
1750 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1751 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
1752 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
1753 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1754 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = UINT_MAX, .voltage = 11 },
1755 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = 12 },
1756 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = 13 },
1757 { .id = TEGRA_IO_PAD_SPI, .dpd = 46, .voltage = 22 },
1758 { .id = TEGRA_IO_PAD_SPI_HV, .dpd = 47, .voltage = 23 },
1759 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = 2 },
1760 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1761 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1762 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1763 { .id = TEGRA_IO_PAD_USB3, .dpd = 18, .voltage = UINT_MAX },
1764 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1767 static const struct tegra_pmc_soc tegra210_pmc_soc = {
1768 .num_powergates = ARRAY_SIZE(tegra210_powergates),
1769 .powergates = tegra210_powergates,
1770 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
1771 .cpu_powergates = tegra210_cpu_powergates,
1772 .has_tsense_reset = true,
1773 .has_gpu_clamps = true,
1774 .needs_mbist_war = true,
1775 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
1776 .io_pads = tegra210_io_pads,
1777 .regs = &tegra20_pmc_regs,
1778 .init = tegra20_pmc_init,
1779 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
1782 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
1783 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1784 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1785 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1786 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1787 { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX },
1788 { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX },
1789 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1790 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX },
1791 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1792 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1793 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1794 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1795 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
1796 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
1797 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1798 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX },
1799 { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX },
1800 { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX },
1801 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
1802 { .id = TEGRA_IO_PAD_SDMMC2_HV, .dpd = 34, .voltage = UINT_MAX },
1803 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX },
1804 { .id = TEGRA_IO_PAD_CAM, .dpd = 38, .voltage = UINT_MAX },
1805 { .id = TEGRA_IO_PAD_DSIB, .dpd = 40, .voltage = UINT_MAX },
1806 { .id = TEGRA_IO_PAD_DSIC, .dpd = 41, .voltage = UINT_MAX },
1807 { .id = TEGRA_IO_PAD_DSID, .dpd = 42, .voltage = UINT_MAX },
1808 { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX },
1809 { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX },
1810 { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX },
1811 { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX },
1812 { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX },
1813 { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX },
1814 { .id = TEGRA_IO_PAD_DMIC_HV, .dpd = 52, .voltage = UINT_MAX },
1815 { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX },
1816 { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX },
1817 { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX },
1818 { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX },
1819 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX },
1822 static const struct tegra_pmc_regs tegra186_pmc_regs = {
1827 .dpd2_status = 0x80,
1830 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
1831 struct device_node *np,
1834 struct resource regs;
1839 index = of_property_match_string(np, "reg-names", "wake");
1841 pr_err("failed to find PMC wake registers\n");
1845 of_address_to_resource(np, index, ®s);
1847 wake = ioremap_nocache(regs.start, resource_size(®s));
1849 pr_err("failed to map PMC wake registers\n");
1853 value = readl(wake + WAKE_AOWAKE_CTRL);
1856 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
1858 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
1860 writel(value, wake + WAKE_AOWAKE_CTRL);
1865 static const struct tegra_pmc_soc tegra186_pmc_soc = {
1866 .num_powergates = 0,
1868 .num_cpu_powergates = 0,
1869 .cpu_powergates = NULL,
1870 .has_tsense_reset = false,
1871 .has_gpu_clamps = false,
1872 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
1873 .io_pads = tegra186_io_pads,
1874 .regs = &tegra186_pmc_regs,
1876 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
1879 static const struct of_device_id tegra_pmc_match[] = {
1880 { .compatible = "nvidia,tegra194-pmc", .data = &tegra186_pmc_soc },
1881 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
1882 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
1883 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
1884 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
1885 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
1886 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
1887 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
1891 static struct platform_driver tegra_pmc_driver = {
1893 .name = "tegra-pmc",
1894 .suppress_bind_attrs = true,
1895 .of_match_table = tegra_pmc_match,
1896 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1897 .pm = &tegra_pmc_pm_ops,
1900 .probe = tegra_pmc_probe,
1902 builtin_platform_driver(tegra_pmc_driver);
1905 * Early initialization to allow access to registers in the very early boot
1908 static int __init tegra_pmc_early_init(void)
1910 const struct of_device_id *match;
1911 struct device_node *np;
1912 struct resource regs;
1915 mutex_init(&pmc->powergates_lock);
1917 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
1920 * Fall back to legacy initialization for 32-bit ARM only. All
1921 * 64-bit ARM device tree files for Tegra are required to have
1924 * This is for backwards-compatibility with old device trees
1925 * that didn't contain a PMC node. Note that in this case the
1926 * SoC data can't be matched and therefore powergating is
1929 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
1930 pr_warn("DT node not found, powergating disabled\n");
1932 regs.start = 0x7000e400;
1933 regs.end = 0x7000e7ff;
1934 regs.flags = IORESOURCE_MEM;
1936 pr_warn("Using memory region %pR\n", ®s);
1939 * At this point we're not running on Tegra, so play
1940 * nice with multi-platform kernels.
1946 * Extract information from the device tree if we've found a
1949 if (of_address_to_resource(np, 0, ®s) < 0) {
1950 pr_err("failed to get PMC registers\n");
1956 pmc->base = ioremap_nocache(regs.start, resource_size(®s));
1958 pr_err("failed to map PMC registers\n");
1964 pmc->soc = match->data;
1966 tegra_powergate_init(pmc, np);
1969 * Invert the interrupt polarity if a PMC device tree node
1970 * exists and contains the nvidia,invert-interrupt property.
1972 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
1974 pmc->soc->setup_irq_polarity(pmc, np, invert);
1981 early_initcall(tegra_pmc_early_init);