2 * drivers/soc/tegra/pmc.c
4 * Copyright (c) 2010 Google, Inc
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #define pr_fmt(fmt) "tegra-pmc: " fmt
22 #include <linux/kernel.h>
23 #include <linux/clk.h>
24 #include <linux/clk/tegra.h>
25 #include <linux/debugfs.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <linux/export.h>
29 #include <linux/init.h>
31 #include <linux/iopoll.h>
33 #include <linux/of_address.h>
34 #include <linux/of_clk.h>
35 #include <linux/of_platform.h>
36 #include <linux/platform_device.h>
37 #include <linux/pm_domain.h>
38 #include <linux/reboot.h>
39 #include <linux/reset.h>
40 #include <linux/seq_file.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
44 #include <soc/tegra/common.h>
45 #include <soc/tegra/fuse.h>
46 #include <soc/tegra/pmc.h>
49 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
50 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
51 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
52 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
53 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
54 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
55 #define PMC_CNTRL_MAIN_RST BIT(4)
57 #define DPD_SAMPLE 0x020
58 #define DPD_SAMPLE_ENABLE BIT(0)
59 #define DPD_SAMPLE_DISABLE (0 << 0)
61 #define PWRGATE_TOGGLE 0x30
62 #define PWRGATE_TOGGLE_START BIT(8)
64 #define REMOVE_CLAMPING 0x34
66 #define PWRGATE_STATUS 0x38
68 #define PMC_PWR_DET 0x48
70 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
71 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
72 #define PMC_SCRATCH0_MODE_RCM BIT(1)
73 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
74 PMC_SCRATCH0_MODE_BOOTLOADER | \
75 PMC_SCRATCH0_MODE_RCM)
77 #define PMC_CPUPWRGOOD_TIMER 0xc8
78 #define PMC_CPUPWROFF_TIMER 0xcc
80 #define PMC_PWR_DET_VALUE 0xe4
82 #define PMC_SCRATCH41 0x140
84 #define PMC_SENSOR_CTRL 0x1b0
85 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
86 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
88 #define PMC_RST_STATUS 0x1b4
89 #define PMC_RST_STATUS_POR 0
90 #define PMC_RST_STATUS_WATCHDOG 1
91 #define PMC_RST_STATUS_SENSOR 2
92 #define PMC_RST_STATUS_SW_MAIN 3
93 #define PMC_RST_STATUS_LP0 4
94 #define PMC_RST_STATUS_AOTAG 5
96 #define IO_DPD_REQ 0x1b8
97 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
98 #define IO_DPD_REQ_CODE_OFF (1U << 30)
99 #define IO_DPD_REQ_CODE_ON (2U << 30)
100 #define IO_DPD_REQ_CODE_MASK (3U << 30)
102 #define IO_DPD_STATUS 0x1bc
103 #define IO_DPD2_REQ 0x1c0
104 #define IO_DPD2_STATUS 0x1c4
105 #define SEL_DPD_TIM 0x1c8
107 #define PMC_SCRATCH54 0x258
108 #define PMC_SCRATCH54_DATA_SHIFT 8
109 #define PMC_SCRATCH54_ADDR_SHIFT 0
111 #define PMC_SCRATCH55 0x25c
112 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
113 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
114 #define PMC_SCRATCH55_PINMUX_SHIFT 24
115 #define PMC_SCRATCH55_16BITOP BIT(15)
116 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
117 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
119 #define GPU_RG_CNTRL 0x2d4
121 /* Tegra186 and later */
122 #define WAKE_AOWAKE_CTRL 0x4f4
123 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
125 struct tegra_powergate {
126 struct generic_pm_domain genpd;
127 struct tegra_pmc *pmc;
130 unsigned int num_clks;
131 struct reset_control *reset;
134 struct tegra_io_pad_soc {
135 enum tegra_io_pad id;
137 unsigned int voltage;
140 struct tegra_pmc_regs {
141 unsigned int scratch0;
142 unsigned int dpd_req;
143 unsigned int dpd_status;
144 unsigned int dpd2_req;
145 unsigned int dpd2_status;
148 struct tegra_pmc_soc {
149 unsigned int num_powergates;
150 const char *const *powergates;
151 unsigned int num_cpu_powergates;
152 const u8 *cpu_powergates;
154 bool has_tsense_reset;
156 bool needs_mbist_war;
158 const struct tegra_io_pad_soc *io_pads;
159 unsigned int num_io_pads;
161 const struct tegra_pmc_regs *regs;
162 void (*init)(struct tegra_pmc *pmc);
163 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
164 struct device_node *np,
169 * struct tegra_pmc - NVIDIA Tegra PMC
170 * @dev: pointer to PMC device structure
171 * @base: pointer to I/O remapped register region
172 * @clk: pointer to pclk clock
173 * @soc: pointer to SoC data structure
174 * @debugfs: pointer to debugfs entry
175 * @rate: currently configured rate of pclk
176 * @suspend_mode: lowest suspend mode available
177 * @cpu_good_time: CPU power good time (in microseconds)
178 * @cpu_off_time: CPU power off time (in microsecends)
179 * @core_osc_time: core power good OSC time (in microseconds)
180 * @core_pmu_time: core power good PMU time (in microseconds)
181 * @core_off_time: core power off time (in microseconds)
182 * @corereq_high: core power request is active-high
183 * @sysclkreq_high: system clock request is active-high
184 * @combined_req: combined power request for CPU & core
185 * @cpu_pwr_good_en: CPU power good signal is enabled
186 * @lp0_vec_phys: physical base address of the LP0 warm boot code
187 * @lp0_vec_size: size of the LP0 warm boot code
188 * @powergates_available: Bitmap of available power gates
189 * @powergates_lock: mutex for power gate register access
196 void __iomem *scratch;
198 struct dentry *debugfs;
200 const struct tegra_pmc_soc *soc;
204 enum tegra_suspend_mode suspend_mode;
213 bool cpu_pwr_good_en;
216 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
218 struct mutex powergates_lock;
221 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
223 .suspend_mode = TEGRA_SUSPEND_NONE,
226 static inline struct tegra_powergate *
227 to_powergate(struct generic_pm_domain *domain)
229 return container_of(domain, struct tegra_powergate, genpd);
232 static u32 tegra_pmc_readl(unsigned long offset)
234 return readl(pmc->base + offset);
237 static void tegra_pmc_writel(u32 value, unsigned long offset)
239 writel(value, pmc->base + offset);
242 static inline bool tegra_powergate_state(int id)
244 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
245 return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0;
247 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0;
250 static inline bool tegra_powergate_is_valid(int id)
252 return (pmc->soc && pmc->soc->powergates[id]);
255 static inline bool tegra_powergate_is_available(int id)
257 return test_bit(id, pmc->powergates_available);
260 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
264 if (!pmc || !pmc->soc || !name)
267 for (i = 0; i < pmc->soc->num_powergates; i++) {
268 if (!tegra_powergate_is_valid(i))
271 if (!strcmp(name, pmc->soc->powergates[i]))
279 * tegra_powergate_set() - set the state of a partition
281 * @new_state: new state of the partition
283 static int tegra_powergate_set(unsigned int id, bool new_state)
288 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
291 mutex_lock(&pmc->powergates_lock);
293 if (tegra_powergate_state(id) == new_state) {
294 mutex_unlock(&pmc->powergates_lock);
298 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
300 err = readx_poll_timeout(tegra_powergate_state, id, status,
301 status == new_state, 10, 100000);
303 mutex_unlock(&pmc->powergates_lock);
308 static int __tegra_powergate_remove_clamping(unsigned int id)
312 mutex_lock(&pmc->powergates_lock);
315 * On Tegra124 and later, the clamps for the GPU are controlled by a
316 * separate register (with different semantics).
318 if (id == TEGRA_POWERGATE_3D) {
319 if (pmc->soc->has_gpu_clamps) {
320 tegra_pmc_writel(0, GPU_RG_CNTRL);
326 * Tegra 2 has a bug where PCIE and VDE clamping masks are
327 * swapped relatively to the partition ids
329 if (id == TEGRA_POWERGATE_VDEC)
330 mask = (1 << TEGRA_POWERGATE_PCIE);
331 else if (id == TEGRA_POWERGATE_PCIE)
332 mask = (1 << TEGRA_POWERGATE_VDEC);
336 tegra_pmc_writel(mask, REMOVE_CLAMPING);
339 mutex_unlock(&pmc->powergates_lock);
344 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
348 for (i = 0; i < pg->num_clks; i++)
349 clk_disable_unprepare(pg->clks[i]);
352 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
357 for (i = 0; i < pg->num_clks; i++) {
358 err = clk_prepare_enable(pg->clks[i]);
367 clk_disable_unprepare(pg->clks[i]);
372 int __weak tegra210_clk_handle_mbist_war(unsigned int id)
377 static int tegra_powergate_power_up(struct tegra_powergate *pg,
382 err = reset_control_assert(pg->reset);
386 usleep_range(10, 20);
388 err = tegra_powergate_set(pg->id, true);
392 usleep_range(10, 20);
394 err = tegra_powergate_enable_clocks(pg);
398 usleep_range(10, 20);
400 err = __tegra_powergate_remove_clamping(pg->id);
404 usleep_range(10, 20);
406 err = reset_control_deassert(pg->reset);
410 usleep_range(10, 20);
412 if (pg->pmc->soc->needs_mbist_war)
413 err = tegra210_clk_handle_mbist_war(pg->id);
418 tegra_powergate_disable_clocks(pg);
423 tegra_powergate_disable_clocks(pg);
424 usleep_range(10, 20);
427 tegra_powergate_set(pg->id, false);
432 static int tegra_powergate_power_down(struct tegra_powergate *pg)
436 err = tegra_powergate_enable_clocks(pg);
440 usleep_range(10, 20);
442 err = reset_control_assert(pg->reset);
446 usleep_range(10, 20);
448 tegra_powergate_disable_clocks(pg);
450 usleep_range(10, 20);
452 err = tegra_powergate_set(pg->id, false);
459 tegra_powergate_enable_clocks(pg);
460 usleep_range(10, 20);
461 reset_control_deassert(pg->reset);
462 usleep_range(10, 20);
465 tegra_powergate_disable_clocks(pg);
470 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
472 struct tegra_powergate *pg = to_powergate(domain);
475 err = tegra_powergate_power_up(pg, true);
477 pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name,
483 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
485 struct tegra_powergate *pg = to_powergate(domain);
488 err = tegra_powergate_power_down(pg);
490 pr_err("failed to turn off PM domain %s: %d\n",
491 pg->genpd.name, err);
497 * tegra_powergate_power_on() - power on partition
500 int tegra_powergate_power_on(unsigned int id)
502 if (!tegra_powergate_is_available(id))
505 return tegra_powergate_set(id, true);
509 * tegra_powergate_power_off() - power off partition
512 int tegra_powergate_power_off(unsigned int id)
514 if (!tegra_powergate_is_available(id))
517 return tegra_powergate_set(id, false);
519 EXPORT_SYMBOL(tegra_powergate_power_off);
522 * tegra_powergate_is_powered() - check if partition is powered
525 int tegra_powergate_is_powered(unsigned int id)
529 if (!tegra_powergate_is_valid(id))
532 mutex_lock(&pmc->powergates_lock);
533 status = tegra_powergate_state(id);
534 mutex_unlock(&pmc->powergates_lock);
540 * tegra_powergate_remove_clamping() - remove power clamps for partition
543 int tegra_powergate_remove_clamping(unsigned int id)
545 if (!tegra_powergate_is_available(id))
548 return __tegra_powergate_remove_clamping(id);
550 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
553 * tegra_powergate_sequence_power_up() - power up partition
555 * @clk: clock for partition
556 * @rst: reset for partition
558 * Must be called with clk disabled, and returns with clk enabled.
560 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
561 struct reset_control *rst)
563 struct tegra_powergate pg;
566 if (!tegra_powergate_is_available(id))
575 err = tegra_powergate_power_up(&pg, false);
577 pr_err("failed to turn on partition %d: %d\n", id, err);
581 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
585 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
586 * @cpuid: CPU partition ID
588 * Returns the partition ID corresponding to the CPU partition ID or a
589 * negative error code on failure.
591 static int tegra_get_cpu_powergate_id(unsigned int cpuid)
593 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
594 return pmc->soc->cpu_powergates[cpuid];
600 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
601 * @cpuid: CPU partition ID
603 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
607 id = tegra_get_cpu_powergate_id(cpuid);
611 return tegra_powergate_is_powered(id);
615 * tegra_pmc_cpu_power_on() - power on CPU partition
616 * @cpuid: CPU partition ID
618 int tegra_pmc_cpu_power_on(unsigned int cpuid)
622 id = tegra_get_cpu_powergate_id(cpuid);
626 return tegra_powergate_set(id, true);
630 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
631 * @cpuid: CPU partition ID
633 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
637 id = tegra_get_cpu_powergate_id(cpuid);
641 return tegra_powergate_remove_clamping(id);
643 #endif /* CONFIG_SMP */
645 static int tegra_pmc_restart_notify(struct notifier_block *this,
646 unsigned long action, void *data)
648 const char *cmd = data;
651 value = readl(pmc->scratch + pmc->soc->regs->scratch0);
652 value &= ~PMC_SCRATCH0_MODE_MASK;
655 if (strcmp(cmd, "recovery") == 0)
656 value |= PMC_SCRATCH0_MODE_RECOVERY;
658 if (strcmp(cmd, "bootloader") == 0)
659 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
661 if (strcmp(cmd, "forced-recovery") == 0)
662 value |= PMC_SCRATCH0_MODE_RCM;
665 writel(value, pmc->scratch + pmc->soc->regs->scratch0);
667 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
668 value = tegra_pmc_readl(PMC_CNTRL);
669 value |= PMC_CNTRL_MAIN_RST;
670 tegra_pmc_writel(value, PMC_CNTRL);
675 static struct notifier_block tegra_pmc_restart_handler = {
676 .notifier_call = tegra_pmc_restart_notify,
680 static int powergate_show(struct seq_file *s, void *data)
685 seq_printf(s, " powergate powered\n");
686 seq_printf(s, "------------------\n");
688 for (i = 0; i < pmc->soc->num_powergates; i++) {
689 status = tegra_powergate_is_powered(i);
693 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
694 status ? "yes" : "no");
700 static int powergate_open(struct inode *inode, struct file *file)
702 return single_open(file, powergate_show, inode->i_private);
705 static const struct file_operations powergate_fops = {
706 .open = powergate_open,
709 .release = single_release,
712 static int tegra_powergate_debugfs_init(void)
714 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
722 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
723 struct device_node *np)
726 unsigned int i, count;
729 count = of_clk_get_parent_count(np);
733 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
737 for (i = 0; i < count; i++) {
738 pg->clks[i] = of_clk_get(np, i);
739 if (IS_ERR(pg->clks[i])) {
740 err = PTR_ERR(pg->clks[i]);
745 pg->num_clks = count;
751 clk_put(pg->clks[i]);
758 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
759 struct device_node *np, bool off)
763 pg->reset = of_reset_control_array_get_exclusive(np);
764 if (IS_ERR(pg->reset)) {
765 err = PTR_ERR(pg->reset);
766 pr_err("failed to get device resets: %d\n", err);
771 err = reset_control_assert(pg->reset);
773 err = reset_control_deassert(pg->reset);
776 reset_control_put(pg->reset);
781 static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
783 struct tegra_powergate *pg;
787 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
791 id = tegra_powergate_lookup(pmc, np->name);
793 pr_err("powergate lookup failed for %s: %d\n", np->name, id);
798 * Clear the bit for this powergate so it cannot be managed
799 * directly via the legacy APIs for controlling powergates.
801 clear_bit(id, pmc->powergates_available);
804 pg->genpd.name = np->name;
805 pg->genpd.power_off = tegra_genpd_power_off;
806 pg->genpd.power_on = tegra_genpd_power_on;
809 off = !tegra_powergate_is_powered(pg->id);
811 err = tegra_powergate_of_get_clks(pg, np);
813 pr_err("failed to get clocks for %s: %d\n", np->name, err);
817 err = tegra_powergate_of_get_resets(pg, np, off);
819 pr_err("failed to get resets for %s: %d\n", np->name, err);
823 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
825 WARN_ON(tegra_powergate_power_up(pg, true));
831 * FIXME: If XHCI is enabled for Tegra, then power-up the XUSB
832 * host and super-speed partitions. Once the XHCI driver
833 * manages the partitions itself this code can be removed. Note
834 * that we don't register these partitions with the genpd core
835 * to avoid it from powering down the partitions as they appear
838 if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) &&
839 (id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC)) {
841 WARN_ON(tegra_powergate_power_up(pg, true));
846 err = pm_genpd_init(&pg->genpd, NULL, off);
848 pr_err("failed to initialise PM domain %s: %d\n", np->name,
853 err = of_genpd_add_provider_simple(np, &pg->genpd);
855 pr_err("failed to add PM domain provider for %s: %d\n",
860 pr_debug("added PM domain %s\n", pg->genpd.name);
865 pm_genpd_remove(&pg->genpd);
868 reset_control_put(pg->reset);
871 while (pg->num_clks--)
872 clk_put(pg->clks[pg->num_clks]);
877 set_bit(id, pmc->powergates_available);
883 static void tegra_powergate_init(struct tegra_pmc *pmc,
884 struct device_node *parent)
886 struct device_node *np, *child;
889 /* Create a bitmap of the available and valid partitions */
890 for (i = 0; i < pmc->soc->num_powergates; i++)
891 if (pmc->soc->powergates[i])
892 set_bit(i, pmc->powergates_available);
894 np = of_get_child_by_name(parent, "powergates");
898 for_each_child_of_node(np, child)
899 tegra_powergate_add(pmc, child);
904 static const struct tegra_io_pad_soc *
905 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
909 for (i = 0; i < pmc->soc->num_io_pads; i++)
910 if (pmc->soc->io_pads[i].id == id)
911 return &pmc->soc->io_pads[i];
916 static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request,
917 unsigned long *status, u32 *mask)
919 const struct tegra_io_pad_soc *pad;
920 unsigned long rate, value;
922 pad = tegra_io_pad_find(pmc, id);
924 pr_err("invalid I/O pad ID %u\n", id);
928 if (pad->dpd == UINT_MAX)
931 *mask = BIT(pad->dpd % 32);
934 *status = pmc->soc->regs->dpd_status;
935 *request = pmc->soc->regs->dpd_req;
937 *status = pmc->soc->regs->dpd2_status;
938 *request = pmc->soc->regs->dpd2_req;
942 rate = clk_get_rate(pmc->clk);
944 pr_err("failed to get clock rate\n");
948 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
950 /* must be at least 200 ns, in APB (PCLK) clock cycles */
951 value = DIV_ROUND_UP(1000000000, rate);
952 value = DIV_ROUND_UP(200, value);
953 tegra_pmc_writel(value, SEL_DPD_TIM);
959 static int tegra_io_pad_poll(unsigned long offset, u32 mask,
960 u32 val, unsigned long timeout)
964 timeout = jiffies + msecs_to_jiffies(timeout);
966 while (time_after(timeout, jiffies)) {
967 value = tegra_pmc_readl(offset);
968 if ((value & mask) == val)
971 usleep_range(250, 1000);
977 static void tegra_io_pad_unprepare(void)
980 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
984 * tegra_io_pad_power_enable() - enable power to I/O pad
985 * @id: Tegra I/O pad ID for which to enable power
987 * Returns: 0 on success or a negative error code on failure.
989 int tegra_io_pad_power_enable(enum tegra_io_pad id)
991 unsigned long request, status;
995 mutex_lock(&pmc->powergates_lock);
997 err = tegra_io_pad_prepare(id, &request, &status, &mask);
999 pr_err("failed to prepare I/O pad: %d\n", err);
1003 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | mask, request);
1005 err = tegra_io_pad_poll(status, mask, 0, 250);
1007 pr_err("failed to enable I/O pad: %d\n", err);
1011 tegra_io_pad_unprepare();
1014 mutex_unlock(&pmc->powergates_lock);
1017 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1020 * tegra_io_pad_power_disable() - disable power to I/O pad
1021 * @id: Tegra I/O pad ID for which to disable power
1023 * Returns: 0 on success or a negative error code on failure.
1025 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1027 unsigned long request, status;
1031 mutex_lock(&pmc->powergates_lock);
1033 err = tegra_io_pad_prepare(id, &request, &status, &mask);
1035 pr_err("failed to prepare I/O pad: %d\n", err);
1039 tegra_pmc_writel(IO_DPD_REQ_CODE_ON | mask, request);
1041 err = tegra_io_pad_poll(status, mask, mask, 250);
1043 pr_err("failed to disable I/O pad: %d\n", err);
1047 tegra_io_pad_unprepare();
1050 mutex_unlock(&pmc->powergates_lock);
1053 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1055 int tegra_io_pad_set_voltage(enum tegra_io_pad id,
1056 enum tegra_io_pad_voltage voltage)
1058 const struct tegra_io_pad_soc *pad;
1061 pad = tegra_io_pad_find(pmc, id);
1065 if (pad->voltage == UINT_MAX)
1068 mutex_lock(&pmc->powergates_lock);
1070 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1071 value = tegra_pmc_readl(PMC_PWR_DET);
1072 value |= BIT(pad->voltage);
1073 tegra_pmc_writel(value, PMC_PWR_DET);
1075 /* update I/O voltage */
1076 value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
1078 if (voltage == TEGRA_IO_PAD_1800000UV)
1079 value &= ~BIT(pad->voltage);
1081 value |= BIT(pad->voltage);
1083 tegra_pmc_writel(value, PMC_PWR_DET_VALUE);
1085 mutex_unlock(&pmc->powergates_lock);
1087 usleep_range(100, 250);
1091 EXPORT_SYMBOL(tegra_io_pad_set_voltage);
1093 int tegra_io_pad_get_voltage(enum tegra_io_pad id)
1095 const struct tegra_io_pad_soc *pad;
1098 pad = tegra_io_pad_find(pmc, id);
1102 if (pad->voltage == UINT_MAX)
1105 value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
1107 if ((value & BIT(pad->voltage)) == 0)
1108 return TEGRA_IO_PAD_1800000UV;
1110 return TEGRA_IO_PAD_3300000UV;
1112 EXPORT_SYMBOL(tegra_io_pad_get_voltage);
1115 * tegra_io_rail_power_on() - enable power to I/O rail
1116 * @id: Tegra I/O pad ID for which to enable power
1118 * See also: tegra_io_pad_power_enable()
1120 int tegra_io_rail_power_on(unsigned int id)
1122 return tegra_io_pad_power_enable(id);
1124 EXPORT_SYMBOL(tegra_io_rail_power_on);
1127 * tegra_io_rail_power_off() - disable power to I/O rail
1128 * @id: Tegra I/O pad ID for which to disable power
1130 * See also: tegra_io_pad_power_disable()
1132 int tegra_io_rail_power_off(unsigned int id)
1134 return tegra_io_pad_power_disable(id);
1136 EXPORT_SYMBOL(tegra_io_rail_power_off);
1138 #ifdef CONFIG_PM_SLEEP
1139 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1141 return pmc->suspend_mode;
1144 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1146 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1149 pmc->suspend_mode = mode;
1152 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1154 unsigned long long rate = 0;
1158 case TEGRA_SUSPEND_LP1:
1162 case TEGRA_SUSPEND_LP2:
1163 rate = clk_get_rate(pmc->clk);
1170 if (WARN_ON_ONCE(rate == 0))
1173 if (rate != pmc->rate) {
1176 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1177 do_div(ticks, USEC_PER_SEC);
1178 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER);
1180 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1181 do_div(ticks, USEC_PER_SEC);
1182 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER);
1189 value = tegra_pmc_readl(PMC_CNTRL);
1190 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1191 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1192 tegra_pmc_writel(value, PMC_CNTRL);
1196 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1198 u32 value, values[2];
1200 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1204 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1208 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1212 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1216 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1221 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1223 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1224 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1226 pmc->cpu_good_time = value;
1228 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1229 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1231 pmc->cpu_off_time = value;
1233 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1234 values, ARRAY_SIZE(values)))
1235 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1237 pmc->core_osc_time = values[0];
1238 pmc->core_pmu_time = values[1];
1240 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1241 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1243 pmc->core_off_time = value;
1245 pmc->corereq_high = of_property_read_bool(np,
1246 "nvidia,core-power-req-active-high");
1248 pmc->sysclkreq_high = of_property_read_bool(np,
1249 "nvidia,sys-clock-req-active-high");
1251 pmc->combined_req = of_property_read_bool(np,
1252 "nvidia,combined-power-req");
1254 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1255 "nvidia,cpu-pwr-good-en");
1257 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1258 ARRAY_SIZE(values)))
1259 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1260 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1262 pmc->lp0_vec_phys = values[0];
1263 pmc->lp0_vec_size = values[1];
1268 static void tegra_pmc_init(struct tegra_pmc *pmc)
1271 pmc->soc->init(pmc);
1274 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1276 static const char disabled[] = "emergency thermal reset disabled";
1277 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1278 struct device *dev = pmc->dev;
1279 struct device_node *np;
1280 u32 value, checksum;
1282 if (!pmc->soc->has_tsense_reset)
1285 np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip");
1287 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1291 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1292 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1296 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1297 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1301 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1302 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1306 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
1307 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1311 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1314 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
1315 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1316 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
1318 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1319 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1320 tegra_pmc_writel(value, PMC_SCRATCH54);
1322 value = PMC_SCRATCH55_RESET_TEGRA;
1323 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1324 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1325 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1328 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1329 * contain the checksum and are currently zero, so they are not added.
1331 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1332 + ((value >> 24) & 0xff);
1334 checksum = 0x100 - checksum;
1336 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1338 tegra_pmc_writel(value, PMC_SCRATCH55);
1340 value = tegra_pmc_readl(PMC_SENSOR_CTRL);
1341 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1342 tegra_pmc_writel(value, PMC_SENSOR_CTRL);
1344 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1350 static int tegra_pmc_probe(struct platform_device *pdev)
1353 struct resource *res;
1357 * Early initialisation should have configured an initial
1358 * register mapping and setup the soc data pointer. If these
1359 * are not valid then something went badly wrong!
1361 if (WARN_ON(!pmc->base || !pmc->soc))
1364 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
1368 /* take over the memory region from the early initialization */
1369 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1370 base = devm_ioremap_resource(&pdev->dev, res);
1372 return PTR_ERR(base);
1374 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
1376 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
1377 if (IS_ERR(pmc->wake))
1378 return PTR_ERR(pmc->wake);
1383 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
1385 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
1386 if (IS_ERR(pmc->aotag))
1387 return PTR_ERR(pmc->aotag);
1392 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
1394 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
1395 if (IS_ERR(pmc->scratch))
1396 return PTR_ERR(pmc->scratch);
1398 pmc->scratch = base;
1401 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
1402 if (IS_ERR(pmc->clk)) {
1403 err = PTR_ERR(pmc->clk);
1405 if (err != -ENOENT) {
1406 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
1413 pmc->dev = &pdev->dev;
1415 tegra_pmc_init(pmc);
1417 tegra_pmc_init_tsense_reset(pmc);
1419 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1420 err = tegra_powergate_debugfs_init();
1425 err = register_restart_handler(&tegra_pmc_restart_handler);
1427 debugfs_remove(pmc->debugfs);
1428 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
1433 mutex_lock(&pmc->powergates_lock);
1436 mutex_unlock(&pmc->powergates_lock);
1441 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1442 static int tegra_pmc_suspend(struct device *dev)
1444 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
1449 static int tegra_pmc_resume(struct device *dev)
1451 tegra_pmc_writel(0x0, PMC_SCRATCH41);
1456 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
1460 static const char * const tegra20_powergates[] = {
1461 [TEGRA_POWERGATE_CPU] = "cpu",
1462 [TEGRA_POWERGATE_3D] = "3d",
1463 [TEGRA_POWERGATE_VENC] = "venc",
1464 [TEGRA_POWERGATE_VDEC] = "vdec",
1465 [TEGRA_POWERGATE_PCIE] = "pcie",
1466 [TEGRA_POWERGATE_L2] = "l2",
1467 [TEGRA_POWERGATE_MPE] = "mpe",
1470 static const struct tegra_pmc_regs tegra20_pmc_regs = {
1473 .dpd_status = 0x1bc,
1475 .dpd2_status = 0x1c4,
1478 static void tegra20_pmc_init(struct tegra_pmc *pmc)
1482 /* Always enable CPU power request */
1483 value = tegra_pmc_readl(PMC_CNTRL);
1484 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1485 tegra_pmc_writel(value, PMC_CNTRL);
1487 value = tegra_pmc_readl(PMC_CNTRL);
1489 if (pmc->sysclkreq_high)
1490 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
1492 value |= PMC_CNTRL_SYSCLK_POLARITY;
1494 /* configure the output polarity while the request is tristated */
1495 tegra_pmc_writel(value, PMC_CNTRL);
1497 /* now enable the request */
1498 value = tegra_pmc_readl(PMC_CNTRL);
1499 value |= PMC_CNTRL_SYSCLK_OE;
1500 tegra_pmc_writel(value, PMC_CNTRL);
1503 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
1504 struct device_node *np,
1509 value = tegra_pmc_readl(PMC_CNTRL);
1512 value |= PMC_CNTRL_INTR_POLARITY;
1514 value &= ~PMC_CNTRL_INTR_POLARITY;
1516 tegra_pmc_writel(value, PMC_CNTRL);
1519 static const struct tegra_pmc_soc tegra20_pmc_soc = {
1520 .num_powergates = ARRAY_SIZE(tegra20_powergates),
1521 .powergates = tegra20_powergates,
1522 .num_cpu_powergates = 0,
1523 .cpu_powergates = NULL,
1524 .has_tsense_reset = false,
1525 .has_gpu_clamps = false,
1528 .regs = &tegra20_pmc_regs,
1529 .init = tegra20_pmc_init,
1530 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
1533 static const char * const tegra30_powergates[] = {
1534 [TEGRA_POWERGATE_CPU] = "cpu0",
1535 [TEGRA_POWERGATE_3D] = "3d0",
1536 [TEGRA_POWERGATE_VENC] = "venc",
1537 [TEGRA_POWERGATE_VDEC] = "vdec",
1538 [TEGRA_POWERGATE_PCIE] = "pcie",
1539 [TEGRA_POWERGATE_L2] = "l2",
1540 [TEGRA_POWERGATE_MPE] = "mpe",
1541 [TEGRA_POWERGATE_HEG] = "heg",
1542 [TEGRA_POWERGATE_SATA] = "sata",
1543 [TEGRA_POWERGATE_CPU1] = "cpu1",
1544 [TEGRA_POWERGATE_CPU2] = "cpu2",
1545 [TEGRA_POWERGATE_CPU3] = "cpu3",
1546 [TEGRA_POWERGATE_CELP] = "celp",
1547 [TEGRA_POWERGATE_3D1] = "3d1",
1550 static const u8 tegra30_cpu_powergates[] = {
1551 TEGRA_POWERGATE_CPU,
1552 TEGRA_POWERGATE_CPU1,
1553 TEGRA_POWERGATE_CPU2,
1554 TEGRA_POWERGATE_CPU3,
1557 static const struct tegra_pmc_soc tegra30_pmc_soc = {
1558 .num_powergates = ARRAY_SIZE(tegra30_powergates),
1559 .powergates = tegra30_powergates,
1560 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
1561 .cpu_powergates = tegra30_cpu_powergates,
1562 .has_tsense_reset = true,
1563 .has_gpu_clamps = false,
1566 .regs = &tegra20_pmc_regs,
1567 .init = tegra20_pmc_init,
1568 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
1571 static const char * const tegra114_powergates[] = {
1572 [TEGRA_POWERGATE_CPU] = "crail",
1573 [TEGRA_POWERGATE_3D] = "3d",
1574 [TEGRA_POWERGATE_VENC] = "venc",
1575 [TEGRA_POWERGATE_VDEC] = "vdec",
1576 [TEGRA_POWERGATE_MPE] = "mpe",
1577 [TEGRA_POWERGATE_HEG] = "heg",
1578 [TEGRA_POWERGATE_CPU1] = "cpu1",
1579 [TEGRA_POWERGATE_CPU2] = "cpu2",
1580 [TEGRA_POWERGATE_CPU3] = "cpu3",
1581 [TEGRA_POWERGATE_CELP] = "celp",
1582 [TEGRA_POWERGATE_CPU0] = "cpu0",
1583 [TEGRA_POWERGATE_C0NC] = "c0nc",
1584 [TEGRA_POWERGATE_C1NC] = "c1nc",
1585 [TEGRA_POWERGATE_DIS] = "dis",
1586 [TEGRA_POWERGATE_DISB] = "disb",
1587 [TEGRA_POWERGATE_XUSBA] = "xusba",
1588 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1589 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1592 static const u8 tegra114_cpu_powergates[] = {
1593 TEGRA_POWERGATE_CPU0,
1594 TEGRA_POWERGATE_CPU1,
1595 TEGRA_POWERGATE_CPU2,
1596 TEGRA_POWERGATE_CPU3,
1599 static const struct tegra_pmc_soc tegra114_pmc_soc = {
1600 .num_powergates = ARRAY_SIZE(tegra114_powergates),
1601 .powergates = tegra114_powergates,
1602 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
1603 .cpu_powergates = tegra114_cpu_powergates,
1604 .has_tsense_reset = true,
1605 .has_gpu_clamps = false,
1608 .regs = &tegra20_pmc_regs,
1609 .init = tegra20_pmc_init,
1610 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
1613 static const char * const tegra124_powergates[] = {
1614 [TEGRA_POWERGATE_CPU] = "crail",
1615 [TEGRA_POWERGATE_3D] = "3d",
1616 [TEGRA_POWERGATE_VENC] = "venc",
1617 [TEGRA_POWERGATE_PCIE] = "pcie",
1618 [TEGRA_POWERGATE_VDEC] = "vdec",
1619 [TEGRA_POWERGATE_MPE] = "mpe",
1620 [TEGRA_POWERGATE_HEG] = "heg",
1621 [TEGRA_POWERGATE_SATA] = "sata",
1622 [TEGRA_POWERGATE_CPU1] = "cpu1",
1623 [TEGRA_POWERGATE_CPU2] = "cpu2",
1624 [TEGRA_POWERGATE_CPU3] = "cpu3",
1625 [TEGRA_POWERGATE_CELP] = "celp",
1626 [TEGRA_POWERGATE_CPU0] = "cpu0",
1627 [TEGRA_POWERGATE_C0NC] = "c0nc",
1628 [TEGRA_POWERGATE_C1NC] = "c1nc",
1629 [TEGRA_POWERGATE_SOR] = "sor",
1630 [TEGRA_POWERGATE_DIS] = "dis",
1631 [TEGRA_POWERGATE_DISB] = "disb",
1632 [TEGRA_POWERGATE_XUSBA] = "xusba",
1633 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1634 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1635 [TEGRA_POWERGATE_VIC] = "vic",
1636 [TEGRA_POWERGATE_IRAM] = "iram",
1639 static const u8 tegra124_cpu_powergates[] = {
1640 TEGRA_POWERGATE_CPU0,
1641 TEGRA_POWERGATE_CPU1,
1642 TEGRA_POWERGATE_CPU2,
1643 TEGRA_POWERGATE_CPU3,
1646 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
1647 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
1648 { .id = TEGRA_IO_PAD_BB, .dpd = 15, .voltage = UINT_MAX },
1649 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = UINT_MAX },
1650 { .id = TEGRA_IO_PAD_COMP, .dpd = 22, .voltage = UINT_MAX },
1651 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1652 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1653 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
1654 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1655 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
1656 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
1657 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
1658 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
1659 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1660 { .id = TEGRA_IO_PAD_HV, .dpd = 38, .voltage = UINT_MAX },
1661 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
1662 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1663 { .id = TEGRA_IO_PAD_NAND, .dpd = 13, .voltage = UINT_MAX },
1664 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
1665 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
1666 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1667 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
1668 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = UINT_MAX },
1669 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = UINT_MAX },
1670 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 35, .voltage = UINT_MAX },
1671 { .id = TEGRA_IO_PAD_SYS_DDC, .dpd = 58, .voltage = UINT_MAX },
1672 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
1673 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1674 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1675 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1676 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1679 static const struct tegra_pmc_soc tegra124_pmc_soc = {
1680 .num_powergates = ARRAY_SIZE(tegra124_powergates),
1681 .powergates = tegra124_powergates,
1682 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
1683 .cpu_powergates = tegra124_cpu_powergates,
1684 .has_tsense_reset = true,
1685 .has_gpu_clamps = true,
1686 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
1687 .io_pads = tegra124_io_pads,
1688 .regs = &tegra20_pmc_regs,
1689 .init = tegra20_pmc_init,
1690 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
1693 static const char * const tegra210_powergates[] = {
1694 [TEGRA_POWERGATE_CPU] = "crail",
1695 [TEGRA_POWERGATE_3D] = "3d",
1696 [TEGRA_POWERGATE_VENC] = "venc",
1697 [TEGRA_POWERGATE_PCIE] = "pcie",
1698 [TEGRA_POWERGATE_MPE] = "mpe",
1699 [TEGRA_POWERGATE_SATA] = "sata",
1700 [TEGRA_POWERGATE_CPU1] = "cpu1",
1701 [TEGRA_POWERGATE_CPU2] = "cpu2",
1702 [TEGRA_POWERGATE_CPU3] = "cpu3",
1703 [TEGRA_POWERGATE_CPU0] = "cpu0",
1704 [TEGRA_POWERGATE_C0NC] = "c0nc",
1705 [TEGRA_POWERGATE_SOR] = "sor",
1706 [TEGRA_POWERGATE_DIS] = "dis",
1707 [TEGRA_POWERGATE_DISB] = "disb",
1708 [TEGRA_POWERGATE_XUSBA] = "xusba",
1709 [TEGRA_POWERGATE_XUSBB] = "xusbb",
1710 [TEGRA_POWERGATE_XUSBC] = "xusbc",
1711 [TEGRA_POWERGATE_VIC] = "vic",
1712 [TEGRA_POWERGATE_IRAM] = "iram",
1713 [TEGRA_POWERGATE_NVDEC] = "nvdec",
1714 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
1715 [TEGRA_POWERGATE_AUD] = "aud",
1716 [TEGRA_POWERGATE_DFD] = "dfd",
1717 [TEGRA_POWERGATE_VE2] = "ve2",
1720 static const u8 tegra210_cpu_powergates[] = {
1721 TEGRA_POWERGATE_CPU0,
1722 TEGRA_POWERGATE_CPU1,
1723 TEGRA_POWERGATE_CPU2,
1724 TEGRA_POWERGATE_CPU3,
1727 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
1728 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = 5 },
1729 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 18 },
1730 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = 10 },
1731 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1732 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1733 { .id = TEGRA_IO_PAD_CSIC, .dpd = 42, .voltage = UINT_MAX },
1734 { .id = TEGRA_IO_PAD_CSID, .dpd = 43, .voltage = UINT_MAX },
1735 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
1736 { .id = TEGRA_IO_PAD_CSIF, .dpd = 45, .voltage = UINT_MAX },
1737 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = 19 },
1738 { .id = TEGRA_IO_PAD_DEBUG_NONAO, .dpd = 26, .voltage = UINT_MAX },
1739 { .id = TEGRA_IO_PAD_DMIC, .dpd = 50, .voltage = 20 },
1740 { .id = TEGRA_IO_PAD_DP, .dpd = 51, .voltage = UINT_MAX },
1741 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1742 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
1743 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
1744 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
1745 { .id = TEGRA_IO_PAD_EMMC, .dpd = 35, .voltage = UINT_MAX },
1746 { .id = TEGRA_IO_PAD_EMMC2, .dpd = 37, .voltage = UINT_MAX },
1747 { .id = TEGRA_IO_PAD_GPIO, .dpd = 27, .voltage = 21 },
1748 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
1749 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1750 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
1751 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1752 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
1753 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
1754 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1755 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = UINT_MAX, .voltage = 11 },
1756 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = 12 },
1757 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = 13 },
1758 { .id = TEGRA_IO_PAD_SPI, .dpd = 46, .voltage = 22 },
1759 { .id = TEGRA_IO_PAD_SPI_HV, .dpd = 47, .voltage = 23 },
1760 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = 2 },
1761 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1762 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1763 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1764 { .id = TEGRA_IO_PAD_USB3, .dpd = 18, .voltage = UINT_MAX },
1765 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1768 static const struct tegra_pmc_soc tegra210_pmc_soc = {
1769 .num_powergates = ARRAY_SIZE(tegra210_powergates),
1770 .powergates = tegra210_powergates,
1771 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
1772 .cpu_powergates = tegra210_cpu_powergates,
1773 .has_tsense_reset = true,
1774 .has_gpu_clamps = true,
1775 .needs_mbist_war = true,
1776 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
1777 .io_pads = tegra210_io_pads,
1778 .regs = &tegra20_pmc_regs,
1779 .init = tegra20_pmc_init,
1780 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
1783 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
1784 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1785 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1786 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1787 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1788 { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX },
1789 { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX },
1790 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1791 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX },
1792 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1793 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1794 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1795 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1796 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
1797 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
1798 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1799 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX },
1800 { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX },
1801 { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX },
1802 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
1803 { .id = TEGRA_IO_PAD_SDMMC2_HV, .dpd = 34, .voltage = UINT_MAX },
1804 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX },
1805 { .id = TEGRA_IO_PAD_CAM, .dpd = 38, .voltage = UINT_MAX },
1806 { .id = TEGRA_IO_PAD_DSIB, .dpd = 40, .voltage = UINT_MAX },
1807 { .id = TEGRA_IO_PAD_DSIC, .dpd = 41, .voltage = UINT_MAX },
1808 { .id = TEGRA_IO_PAD_DSID, .dpd = 42, .voltage = UINT_MAX },
1809 { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX },
1810 { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX },
1811 { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX },
1812 { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX },
1813 { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX },
1814 { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX },
1815 { .id = TEGRA_IO_PAD_DMIC_HV, .dpd = 52, .voltage = UINT_MAX },
1816 { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX },
1817 { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX },
1818 { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX },
1819 { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX },
1820 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX },
1823 static const struct tegra_pmc_regs tegra186_pmc_regs = {
1828 .dpd2_status = 0x80,
1831 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
1832 struct device_node *np,
1835 struct resource regs;
1840 index = of_property_match_string(np, "reg-names", "wake");
1842 pr_err("failed to find PMC wake registers\n");
1846 of_address_to_resource(np, index, ®s);
1848 wake = ioremap_nocache(regs.start, resource_size(®s));
1850 pr_err("failed to map PMC wake registers\n");
1854 value = readl(wake + WAKE_AOWAKE_CTRL);
1857 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
1859 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
1861 writel(value, wake + WAKE_AOWAKE_CTRL);
1866 static const struct tegra_pmc_soc tegra186_pmc_soc = {
1867 .num_powergates = 0,
1869 .num_cpu_powergates = 0,
1870 .cpu_powergates = NULL,
1871 .has_tsense_reset = false,
1872 .has_gpu_clamps = false,
1873 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
1874 .io_pads = tegra186_io_pads,
1875 .regs = &tegra186_pmc_regs,
1877 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
1880 static const struct of_device_id tegra_pmc_match[] = {
1881 { .compatible = "nvidia,tegra194-pmc", .data = &tegra186_pmc_soc },
1882 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
1883 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
1884 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
1885 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
1886 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
1887 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
1888 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
1892 static struct platform_driver tegra_pmc_driver = {
1894 .name = "tegra-pmc",
1895 .suppress_bind_attrs = true,
1896 .of_match_table = tegra_pmc_match,
1897 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1898 .pm = &tegra_pmc_pm_ops,
1901 .probe = tegra_pmc_probe,
1903 builtin_platform_driver(tegra_pmc_driver);
1906 * Early initialization to allow access to registers in the very early boot
1909 static int __init tegra_pmc_early_init(void)
1911 const struct of_device_id *match;
1912 struct device_node *np;
1913 struct resource regs;
1916 mutex_init(&pmc->powergates_lock);
1918 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
1921 * Fall back to legacy initialization for 32-bit ARM only. All
1922 * 64-bit ARM device tree files for Tegra are required to have
1925 * This is for backwards-compatibility with old device trees
1926 * that didn't contain a PMC node. Note that in this case the
1927 * SoC data can't be matched and therefore powergating is
1930 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
1931 pr_warn("DT node not found, powergating disabled\n");
1933 regs.start = 0x7000e400;
1934 regs.end = 0x7000e7ff;
1935 regs.flags = IORESOURCE_MEM;
1937 pr_warn("Using memory region %pR\n", ®s);
1940 * At this point we're not running on Tegra, so play
1941 * nice with multi-platform kernels.
1947 * Extract information from the device tree if we've found a
1950 if (of_address_to_resource(np, 0, ®s) < 0) {
1951 pr_err("failed to get PMC registers\n");
1957 pmc->base = ioremap_nocache(regs.start, resource_size(®s));
1959 pr_err("failed to map PMC registers\n");
1965 pmc->soc = match->data;
1967 tegra_powergate_init(pmc, np);
1970 * Invert the interrupt polarity if a PMC device tree node
1971 * exists and contains the nvidia,invert-interrupt property.
1973 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
1975 pmc->soc->setup_irq_polarity(pmc, np, invert);
1982 early_initcall(tegra_pmc_early_init);