drivers/soc/sifive/sifive_ccache.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SiFive composable cache controller Driver
   4  *
   5  * Copyright (C) 2018-2022 SiFive, Inc.
   6  *
   7  */
   8
   9 #define pr_fmt(fmt) "CCACHE: " fmt
  10
  11 #include <linux/debugfs.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/of_irq.h>
  14 #include <linux/of_address.h>
  15 #include <linux/device.h>
  16 #include <linux/bitfield.h>
  17 #include <asm/cacheinfo.h>
  18 #include <soc/sifive/sifive_ccache.h>
  19
  20 #define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
  21 #define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104
  22 #define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108
  23
  24 #define SIFIVE_CCACHE_DIRECCFAIL_LOW 0x120
  25 #define SIFIVE_CCACHE_DIRECCFAIL_HIGH 0x124
  26 #define SIFIVE_CCACHE_DIRECCFAIL_COUNT 0x128
  27
  28 #define SIFIVE_CCACHE_DATECCFIX_LOW 0x140
  29 #define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144
  30 #define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148
  31
  32 #define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160
  33 #define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164
  34 #define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
  35
  36 #define SIFIVE_CCACHE_CONFIG 0x00
  37 #define SIFIVE_CCACHE_CONFIG_BANK_MASK GENMASK_ULL(7, 0)
  38 #define SIFIVE_CCACHE_CONFIG_WAYS_MASK GENMASK_ULL(15, 8)
  39 #define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16)
  40 #define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24)
  41
  42 #define SIFIVE_CCACHE_WAYENABLE 0x08
  43 #define SIFIVE_CCACHE_ECCINJECTERR 0x40
  44
  45 #define SIFIVE_CCACHE_MAX_ECCINTR 4
  46
  47 static void __iomem *ccache_base;
  48 static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
  49 static struct riscv_cacheinfo_ops ccache_cache_ops;
  50 static int level;
  51
  52 enum {
  53         DIR_CORR = 0,
  54         DATA_CORR,
  55         DATA_UNCORR,
  56         DIR_UNCORR,
  57 };
  58
  59 #ifdef CONFIG_DEBUG_FS
  60 static struct dentry *sifive_test;
  61
  62 static ssize_t ccache_write(struct file *file, const char __user *data,
  63                             size_t count, loff_t *ppos)
  64 {
  65         unsigned int val;
  66
  67         if (kstrtouint_from_user(data, count, 0, &val))
  68                 return -EINVAL;
  69         if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
  70                 writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
  71         else
  72                 return -EINVAL;
  73         return count;
  74 }
  75
  76 static const struct file_operations ccache_fops = {
  77         .owner = THIS_MODULE,
  78         .open = simple_open,
  79         .write = ccache_write
  80 };
  81
  82 static void setup_sifive_debug(void)
  83 {
  84         sifive_test = debugfs_create_dir("sifive_ccache_cache", NULL);
  85
  86         debugfs_create_file("sifive_debug_inject_error", 0200,
  87                             sifive_test, NULL, &ccache_fops);
  88 }
  89 #endif
  90
  91 static void ccache_config_read(void)
  92 {
  93         u32 cfg;
  94
  95         cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
  96         pr_info("%llu banks, %llu ways, sets/bank=%llu, bytes/block=%llu\n",
  97                 FIELD_GET(SIFIVE_CCACHE_CONFIG_BANK_MASK, cfg),
  98                 FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS_MASK, cfg),
  99                 BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_SETS_MASK, cfg)),
 100                 BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_BLKS_MASK, cfg)));
 101
 102         cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
 103         pr_info("Index of the largest way enabled: %u\n", cfg);
 104 }
 105
 106 static const struct of_device_id sifive_ccache_ids[] = {
 107         { .compatible = "sifive,fu540-c000-ccache" },
 108         { .compatible = "sifive,fu740-c000-ccache" },
 109         { .compatible = "sifive,ccache0" },
 110         { .compatible = "starfive,jh7110-ccache" },
 111         { /* end of table */ }
 112 };
 113
 114 static ATOMIC_NOTIFIER_HEAD(ccache_err_chain);
 115
 116 int register_sifive_ccache_error_notifier(struct notifier_block *nb)
 117 {
 118         return atomic_notifier_chain_register(&ccache_err_chain, nb);
 119 }
 120 EXPORT_SYMBOL_GPL(register_sifive_ccache_error_notifier);
 121
 122 int unregister_sifive_ccache_error_notifier(struct notifier_block *nb)
 123 {
 124         return atomic_notifier_chain_unregister(&ccache_err_chain, nb);
 125 }
 126 EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier);
 127
 128 static int ccache_largest_wayenabled(void)
 129 {
 130         return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF;
 131 }
 132
 133 static ssize_t number_of_ways_enabled_show(struct device *dev,
 134                                            struct device_attribute *attr,
 135                                            char *buf)
 136 {
 137         return sprintf(buf, "%u\n", ccache_largest_wayenabled());
 138 }
 139
 140 static DEVICE_ATTR_RO(number_of_ways_enabled);
 141
 142 static struct attribute *priv_attrs[] = {
 143         &dev_attr_number_of_ways_enabled.attr,
 144         NULL,
 145 };
 146
 147 static const struct attribute_group priv_attr_group = {
 148         .attrs = priv_attrs,
 149 };
 150
 151 static const struct attribute_group *ccache_get_priv_group(struct cacheinfo
 152                                                            *this_leaf)
 153 {
 154         /* We want to use private group for composable cache only */
 155         if (this_leaf->level == level)
 156                 return &priv_attr_group;
 157         else
 158                 return NULL;
 159 }
 160
 161 static irqreturn_t ccache_int_handler(int irq, void *device)
 162 {
 163         unsigned int add_h, add_l;
 164
 165         if (irq == g_irq[DIR_CORR]) {
 166                 add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH);
 167                 add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW);
 168                 pr_err("DirError @ 0x%08X.%08X\n", add_h, add_l);
 169                 /* Reading this register clears the DirError interrupt sig */
 170                 readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT);
 171                 atomic_notifier_call_chain(&ccache_err_chain,
 172                                            SIFIVE_CCACHE_ERR_TYPE_CE,
 173                                            "DirECCFix");
 174         }
 175         if (irq == g_irq[DIR_UNCORR]) {
 176                 add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_HIGH);
 177                 add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_LOW);
 178                 /* Reading this register clears the DirFail interrupt sig */
 179                 readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_COUNT);
 180                 atomic_notifier_call_chain(&ccache_err_chain,
 181                                            SIFIVE_CCACHE_ERR_TYPE_UE,
 182                                            "DirECCFail");
 183                 panic("CCACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l);
 184         }
 185         if (irq == g_irq[DATA_CORR]) {
 186                 add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH);
 187                 add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW);
 188                 pr_err("DataError @ 0x%08X.%08X\n", add_h, add_l);
 189                 /* Reading this register clears the DataError interrupt sig */
 190                 readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT);
 191                 atomic_notifier_call_chain(&ccache_err_chain,
 192                                            SIFIVE_CCACHE_ERR_TYPE_CE,
 193                                            "DatECCFix");
 194         }
 195         if (irq == g_irq[DATA_UNCORR]) {
 196                 add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH);
 197                 add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW);
 198                 pr_err("DataFail @ 0x%08X.%08X\n", add_h, add_l);
 199                 /* Reading this register clears the DataFail interrupt sig */
 200                 readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT);
 201                 atomic_notifier_call_chain(&ccache_err_chain,
 202                                            SIFIVE_CCACHE_ERR_TYPE_UE,
 203                                            "DatECCFail");
 204         }
 205
 206         return IRQ_HANDLED;
 207 }
 208
 209 static int __init sifive_ccache_init(void)
 210 {
 211         struct device_node *np;
 212         struct resource res;
 213         int i, rc, intr_num;
 214
 215         np = of_find_matching_node(NULL, sifive_ccache_ids);
 216         if (!np)
 217                 return -ENODEV;
 218
 219         if (of_address_to_resource(np, 0, &res)) {
 220                 rc = -ENODEV;
 221                 goto err_node_put;
 222         }
 223
 224         ccache_base = ioremap(res.start, resource_size(&res));
 225         if (!ccache_base) {
 226                 rc = -ENOMEM;
 227                 goto err_node_put;
 228         }
 229
 230         if (of_property_read_u32(np, "cache-level", &level)) {
 231                 rc = -ENOENT;
 232                 goto err_unmap;
 233         }
 234
 235         intr_num = of_property_count_u32_elems(np, "interrupts");
 236         if (!intr_num) {
 237                 pr_err("No interrupts property\n");
 238                 rc = -ENODEV;
 239                 goto err_unmap;
 240         }
 241
 242         for (i = 0; i < intr_num; i++) {
 243                 g_irq[i] = irq_of_parse_and_map(np, i);
 244                 rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc",
 245                                  NULL);
 246                 if (rc) {
 247                         pr_err("Could not request IRQ %d\n", g_irq[i]);
 248                         goto err_free_irq;
 249                 }
 250         }
 251         of_node_put(np);
 252
 253         ccache_config_read();
 254
 255         ccache_cache_ops.get_priv_group = ccache_get_priv_group;
 256         riscv_set_cacheinfo_ops(&ccache_cache_ops);
 257
 258 #ifdef CONFIG_DEBUG_FS
 259         setup_sifive_debug();
 260 #endif
 261         return 0;
 262
 263 err_free_irq:
 264         while (--i >= 0)
 265                 free_irq(g_irq[i], NULL);
 266 err_unmap:
 267         iounmap(ccache_base);
 268 err_node_put:
 269         of_node_put(np);
 270         return rc;
 271 }
 272
 273 device_initcall(sifive_ccache_init);