drivers/soc/samsung/pm_domains.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Exynos Generic power domain support.
   4 //
   5 // Copyright (c) 2012 Samsung Electronics Co., Ltd.
   6 //              http://www.samsung.com
   7 //
   8 // Implementation of Exynos specific power domain control which is used in
   9 // conjunction with runtime-pm. Support for both device-tree and non-device-tree
  10 // based power domain support is included.
  11
  12 #include <linux/io.h>
  13 #include <linux/err.h>
  14 #include <linux/slab.h>
  15 #include <linux/pm_domain.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/sched.h>
  21
  22 #define MAX_CLK_PER_DOMAIN      4
  23
  24 struct exynos_pm_domain_config {
  25         /* Value for LOCAL_PWR_CFG and STATUS fields for each domain */
  26         u32 local_pwr_cfg;
  27 };
  28
  29 /*
  30  * Exynos specific wrapper around the generic power domain
  31  */
  32 struct exynos_pm_domain {
  33         void __iomem *base;
  34         bool is_off;
  35         struct generic_pm_domain pd;
  36         struct clk *oscclk;
  37         struct clk *clk[MAX_CLK_PER_DOMAIN];
  38         struct clk *pclk[MAX_CLK_PER_DOMAIN];
  39         struct clk *asb_clk[MAX_CLK_PER_DOMAIN];
  40         u32 local_pwr_cfg;
  41 };
  42
  43 static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
  44 {
  45         struct exynos_pm_domain *pd;
  46         void __iomem *base;
  47         u32 timeout, pwr;
  48         char *op;
  49         int i;
  50
  51         pd = container_of(domain, struct exynos_pm_domain, pd);
  52         base = pd->base;
  53
  54         for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
  55                 if (IS_ERR(pd->asb_clk[i]))
  56                         break;
  57                 clk_prepare_enable(pd->asb_clk[i]);
  58         }
  59
  60         /* Set oscclk before powering off a domain*/
  61         if (!power_on) {
  62                 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
  63                         if (IS_ERR(pd->clk[i]))
  64                                 break;
  65                         pd->pclk[i] = clk_get_parent(pd->clk[i]);
  66                         if (clk_set_parent(pd->clk[i], pd->oscclk))
  67                                 pr_err("%s: error setting oscclk as parent to clock %d\n",
  68                                                 domain->name, i);
  69                 }
  70         }
  71
  72         pwr = power_on ? pd->local_pwr_cfg : 0;
  73         writel_relaxed(pwr, base);
  74
  75         /* Wait max 1ms */
  76         timeout = 10;
  77
  78         while ((readl_relaxed(base + 0x4) & pd->local_pwr_cfg) != pwr) {
  79                 if (!timeout) {
  80                         op = (power_on) ? "enable" : "disable";
  81                         pr_err("Power domain %s %s failed\n", domain->name, op);
  82                         return -ETIMEDOUT;
  83                 }
  84                 timeout--;
  85                 cpu_relax();
  86                 usleep_range(80, 100);
  87         }
  88
  89         /* Restore clocks after powering on a domain*/
  90         if (power_on) {
  91                 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
  92                         if (IS_ERR(pd->clk[i]))
  93                                 break;
  94
  95                         if (IS_ERR(pd->pclk[i]))
  96                                 continue; /* Skip on first power up */
  97                         if (clk_set_parent(pd->clk[i], pd->pclk[i]))
  98                                 pr_err("%s: error setting parent to clock%d\n",
  99                                                 domain->name, i);
 100                 }
 101         }
 102
 103         for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
 104                 if (IS_ERR(pd->asb_clk[i]))
 105                         break;
 106                 clk_disable_unprepare(pd->asb_clk[i]);
 107         }
 108
 109         return 0;
 110 }
 111
 112 static int exynos_pd_power_on(struct generic_pm_domain *domain)
 113 {
 114         return exynos_pd_power(domain, true);
 115 }
 116
 117 static int exynos_pd_power_off(struct generic_pm_domain *domain)
 118 {
 119         return exynos_pd_power(domain, false);
 120 }
 121
 122 static const struct exynos_pm_domain_config exynos4210_cfg __initconst = {
 123         .local_pwr_cfg          = 0x7,
 124 };
 125
 126 static const struct exynos_pm_domain_config exynos5433_cfg __initconst = {
 127         .local_pwr_cfg          = 0xf,
 128 };
 129
 130 static const struct of_device_id exynos_pm_domain_of_match[] __initconst = {
 131         {
 132                 .compatible = "samsung,exynos4210-pd",
 133                 .data = &exynos4210_cfg,
 134         }, {
 135                 .compatible = "samsung,exynos5433-pd",
 136                 .data = &exynos5433_cfg,
 137         },
 138         { },
 139 };
 140
 141 static __init const char *exynos_get_domain_name(struct device_node *node)
 142 {
 143         const char *name;
 144
 145         if (of_property_read_string(node, "label", &name) < 0)
 146                 name = kbasename(node->full_name);
 147         return kstrdup_const(name, GFP_KERNEL);
 148 }
 149
 150 static const char *soc_force_no_clk[] = {
 151         "samsung,exynos5420-clock",
 152         "samsung,exynos5800-clock",
 153 };
 154
 155 static __init int exynos4_pm_init_power_domain(void)
 156 {
 157         struct device_node *np;
 158         const struct of_device_id *match;
 159
 160         for_each_matching_node_and_match(np, exynos_pm_domain_of_match, &match) {
 161                 const struct exynos_pm_domain_config *pm_domain_cfg;
 162                 struct exynos_pm_domain *pd;
 163                 int on, i;
 164
 165                 pm_domain_cfg = match->data;
 166
 167                 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 168                 if (!pd) {
 169                         of_node_put(np);
 170                         return -ENOMEM;
 171                 }
 172                 pd->pd.name = exynos_get_domain_name(np);
 173                 if (!pd->pd.name) {
 174                         kfree(pd);
 175                         of_node_put(np);
 176                         return -ENOMEM;
 177                 }
 178
 179                 pd->base = of_iomap(np, 0);
 180                 if (!pd->base) {
 181                         pr_warn("%s: failed to map memory\n", __func__);
 182                         kfree_const(pd->pd.name);
 183                         kfree(pd);
 184                         continue;
 185                 }
 186
 187                 pd->pd.power_off = exynos_pd_power_off;
 188                 pd->pd.power_on = exynos_pd_power_on;
 189                 pd->local_pwr_cfg = pm_domain_cfg->local_pwr_cfg;
 190
 191                 for (i = 0; i < ARRAY_SIZE(soc_force_no_clk); i++)
 192                         if (of_find_compatible_node(NULL, NULL,
 193                                                     soc_force_no_clk[i]))
 194                                 goto no_clk;
 195
 196                 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
 197                         char clk_name[8];
 198
 199                         snprintf(clk_name, sizeof(clk_name), "asb%d", i);
 200                         pd->asb_clk[i] = of_clk_get_by_name(np, clk_name);
 201                         if (IS_ERR(pd->asb_clk[i]))
 202                                 break;
 203                 }
 204
 205                 pd->oscclk = of_clk_get_by_name(np, "oscclk");
 206                 if (IS_ERR(pd->oscclk))
 207                         goto no_clk;
 208
 209                 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
 210                         char clk_name[8];
 211
 212                         snprintf(clk_name, sizeof(clk_name), "clk%d", i);
 213                         pd->clk[i] = of_clk_get_by_name(np, clk_name);
 214                         if (IS_ERR(pd->clk[i]))
 215                                 break;
 216                         /*
 217                          * Skip setting parent on first power up.
 218                          * The parent at this time may not be useful at all.
 219                          */
 220                         pd->pclk[i] = ERR_PTR(-EINVAL);
 221                 }
 222
 223                 if (IS_ERR(pd->clk[0]))
 224                         clk_put(pd->oscclk);
 225
 226 no_clk:
 227                 on = readl_relaxed(pd->base + 0x4) & pd->local_pwr_cfg;
 228
 229                 pm_genpd_init(&pd->pd, NULL, !on);
 230                 of_genpd_add_provider_simple(np, &pd->pd);
 231         }
 232
 233         /* Assign the child power domains to their parents */
 234         for_each_matching_node(np, exynos_pm_domain_of_match) {
 235                 struct of_phandle_args child, parent;
 236
 237                 child.np = np;
 238                 child.args_count = 0;
 239
 240                 if (of_parse_phandle_with_args(np, "power-domains",
 241                                                "#power-domain-cells", 0,
 242                                                &parent) != 0)
 243                         continue;
 244
 245                 if (of_genpd_add_subdomain(&parent, &child))
 246                         pr_warn("%pOF failed to add subdomain: %pOF\n",
 247                                 parent.np, child.np);
 248                 else
 249                         pr_info("%pOF has as child subdomain: %pOF.\n",
 250                                 parent.np, child.np);
 251         }
 252
 253         return 0;
 254 }
 255 core_initcall(exynos4_pm_init_power_domain);