1 // SPDX-License-Identifier: GPL-2.0
3 // Exynos Generic power domain support.
5 // Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 // http://www.samsung.com
8 // Implementation of Exynos specific power domain control which is used in
9 // conjunction with runtime-pm. Support for both device-tree and non-device-tree
10 // based power domain support is included.
13 #include <linux/err.h>
14 #include <linux/slab.h>
15 #include <linux/pm_domain.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/of_address.h>
19 #include <linux/of_platform.h>
20 #include <linux/sched.h>
22 #define MAX_CLK_PER_DOMAIN 4
24 struct exynos_pm_domain_config {
25 /* Value for LOCAL_PWR_CFG and STATUS fields for each domain */
30 * Exynos specific wrapper around the generic power domain
32 struct exynos_pm_domain {
35 struct generic_pm_domain pd;
37 struct clk *clk[MAX_CLK_PER_DOMAIN];
38 struct clk *pclk[MAX_CLK_PER_DOMAIN];
39 struct clk *asb_clk[MAX_CLK_PER_DOMAIN];
43 static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
45 struct exynos_pm_domain *pd;
51 pd = container_of(domain, struct exynos_pm_domain, pd);
54 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
55 if (IS_ERR(pd->asb_clk[i]))
57 clk_prepare_enable(pd->asb_clk[i]);
60 /* Set oscclk before powering off a domain*/
62 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
63 if (IS_ERR(pd->clk[i]))
65 pd->pclk[i] = clk_get_parent(pd->clk[i]);
66 if (clk_set_parent(pd->clk[i], pd->oscclk))
67 pr_err("%s: error setting oscclk as parent to clock %d\n",
72 pwr = power_on ? pd->local_pwr_cfg : 0;
73 writel_relaxed(pwr, base);
78 while ((readl_relaxed(base + 0x4) & pd->local_pwr_cfg) != pwr) {
80 op = (power_on) ? "enable" : "disable";
81 pr_err("Power domain %s %s failed\n", domain->name, op);
86 usleep_range(80, 100);
89 /* Restore clocks after powering on a domain*/
91 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
92 if (IS_ERR(pd->clk[i]))
95 if (IS_ERR(pd->pclk[i]))
96 continue; /* Skip on first power up */
97 if (clk_set_parent(pd->clk[i], pd->pclk[i]))
98 pr_err("%s: error setting parent to clock%d\n",
103 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
104 if (IS_ERR(pd->asb_clk[i]))
106 clk_disable_unprepare(pd->asb_clk[i]);
112 static int exynos_pd_power_on(struct generic_pm_domain *domain)
114 return exynos_pd_power(domain, true);
117 static int exynos_pd_power_off(struct generic_pm_domain *domain)
119 return exynos_pd_power(domain, false);
122 static const struct exynos_pm_domain_config exynos4210_cfg __initconst = {
123 .local_pwr_cfg = 0x7,
126 static const struct exynos_pm_domain_config exynos5433_cfg __initconst = {
127 .local_pwr_cfg = 0xf,
130 static const struct of_device_id exynos_pm_domain_of_match[] __initconst = {
132 .compatible = "samsung,exynos4210-pd",
133 .data = &exynos4210_cfg,
135 .compatible = "samsung,exynos5433-pd",
136 .data = &exynos5433_cfg,
141 static __init const char *exynos_get_domain_name(struct device_node *node)
145 if (of_property_read_string(node, "label", &name) < 0)
146 name = kbasename(node->full_name);
147 return kstrdup_const(name, GFP_KERNEL);
150 static const char *soc_force_no_clk[] = {
153 static __init int exynos4_pm_init_power_domain(void)
155 struct device_node *np;
156 const struct of_device_id *match;
158 for_each_matching_node_and_match(np, exynos_pm_domain_of_match, &match) {
159 const struct exynos_pm_domain_config *pm_domain_cfg;
160 struct exynos_pm_domain *pd;
163 pm_domain_cfg = match->data;
165 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
170 pd->pd.name = exynos_get_domain_name(np);
177 pd->base = of_iomap(np, 0);
179 pr_warn("%s: failed to map memory\n", __func__);
180 kfree_const(pd->pd.name);
185 pd->pd.power_off = exynos_pd_power_off;
186 pd->pd.power_on = exynos_pd_power_on;
187 pd->local_pwr_cfg = pm_domain_cfg->local_pwr_cfg;
189 for (i = 0; i < ARRAY_SIZE(soc_force_no_clk); i++)
190 if (of_find_compatible_node(NULL, NULL,
191 soc_force_no_clk[i]))
194 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
197 snprintf(clk_name, sizeof(clk_name), "asb%d", i);
198 pd->asb_clk[i] = of_clk_get_by_name(np, clk_name);
199 if (IS_ERR(pd->asb_clk[i]))
203 pd->oscclk = of_clk_get_by_name(np, "oscclk");
204 if (IS_ERR(pd->oscclk))
207 for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
210 snprintf(clk_name, sizeof(clk_name), "clk%d", i);
211 pd->clk[i] = of_clk_get_by_name(np, clk_name);
212 if (IS_ERR(pd->clk[i]))
215 * Skip setting parent on first power up.
216 * The parent at this time may not be useful at all.
218 pd->pclk[i] = ERR_PTR(-EINVAL);
221 if (IS_ERR(pd->clk[0]))
225 on = readl_relaxed(pd->base + 0x4) & pd->local_pwr_cfg;
227 pm_genpd_init(&pd->pd, NULL, !on);
228 of_genpd_add_provider_simple(np, &pd->pd);
231 /* Assign the child power domains to their parents */
232 for_each_matching_node(np, exynos_pm_domain_of_match) {
233 struct of_phandle_args child, parent;
236 child.args_count = 0;
238 if (of_parse_phandle_with_args(np, "power-domains",
239 "#power-domain-cells", 0,
243 if (of_genpd_add_subdomain(&parent, &child))
244 pr_warn("%pOF failed to add subdomain: %pOF\n",
245 parent.np, child.np);
247 pr_info("%pOF has as child subdomain: %pOF.\n",
248 parent.np, child.np);
253 core_initcall(exynos4_pm_init_power_domain);