2 * Rockchip Generic power domain support.
4 * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/iopoll.h>
13 #include <linux/err.h>
14 #include <linux/pm_clock.h>
15 #include <linux/pm_domain.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include <linux/clk.h>
19 #include <linux/regmap.h>
20 #include <linux/mfd/syscon.h>
21 #include <dt-bindings/power/rk3288-power.h>
22 #include <dt-bindings/power/rk3328-power.h>
23 #include <dt-bindings/power/rk3366-power.h>
24 #include <dt-bindings/power/rk3368-power.h>
25 #include <dt-bindings/power/rk3399-power.h>
27 struct rockchip_domain_info {
38 struct rockchip_pmu_info {
45 u32 core_pwrcnt_offset;
46 u32 gpu_pwrcnt_offset;
48 unsigned int core_power_transition_time;
49 unsigned int gpu_power_transition_time;
52 const struct rockchip_domain_info *domain_info;
55 #define MAX_QOS_REGS_NUM 5
56 #define QOS_PRIORITY 0x08
58 #define QOS_BANDWIDTH 0x10
59 #define QOS_SATURATION 0x14
60 #define QOS_EXTCONTROL 0x18
62 struct rockchip_pm_domain {
63 struct generic_pm_domain genpd;
64 const struct rockchip_domain_info *info;
65 struct rockchip_pmu *pmu;
67 struct regmap **qos_regmap;
68 u32 *qos_save_regs[MAX_QOS_REGS_NUM];
70 struct clk_bulk_data *clks;
75 struct regmap *regmap;
76 const struct rockchip_pmu_info *info;
77 struct mutex mutex; /* mutex lock for pmu */
78 struct genpd_onecell_data genpd_data;
79 struct generic_pm_domain *domains[];
82 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
84 #define DOMAIN(pwr, status, req, idle, ack, wakeup) \
86 .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0, \
87 .status_mask = (status >= 0) ? BIT(status) : 0, \
88 .req_mask = (req >= 0) ? BIT(req) : 0, \
89 .idle_mask = (idle >= 0) ? BIT(idle) : 0, \
90 .ack_mask = (ack >= 0) ? BIT(ack) : 0, \
91 .active_wakeup = wakeup, \
94 #define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \
96 .pwr_w_mask = (pwr >= 0) ? BIT(pwr + 16) : 0, \
97 .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0, \
98 .status_mask = (status >= 0) ? BIT(status) : 0, \
99 .req_w_mask = (req >= 0) ? BIT(req + 16) : 0, \
100 .req_mask = (req >= 0) ? BIT(req) : 0, \
101 .idle_mask = (idle >= 0) ? BIT(idle) : 0, \
102 .ack_mask = (ack >= 0) ? BIT(ack) : 0, \
103 .active_wakeup = wakeup, \
106 #define DOMAIN_RK3288(pwr, status, req, wakeup) \
107 DOMAIN(pwr, status, req, req, (req) + 16, wakeup)
109 #define DOMAIN_RK3328(pwr, status, req, wakeup) \
110 DOMAIN_M(pwr, pwr, req, (req) + 10, req, wakeup)
112 #define DOMAIN_RK3368(pwr, status, req, wakeup) \
113 DOMAIN(pwr, status, req, (req) + 16, req, wakeup)
115 #define DOMAIN_RK3399(pwr, status, req, wakeup) \
116 DOMAIN(pwr, status, req, req, req, wakeup)
118 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
120 struct rockchip_pmu *pmu = pd->pmu;
121 const struct rockchip_domain_info *pd_info = pd->info;
124 regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
125 return (val & pd_info->idle_mask) == pd_info->idle_mask;
128 static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
132 regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
136 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
139 const struct rockchip_domain_info *pd_info = pd->info;
140 struct generic_pm_domain *genpd = &pd->genpd;
141 struct rockchip_pmu *pmu = pd->pmu;
142 unsigned int target_ack;
147 if (pd_info->req_mask == 0)
149 else if (pd_info->req_w_mask)
150 regmap_write(pmu->regmap, pmu->info->req_offset,
151 idle ? (pd_info->req_mask | pd_info->req_w_mask) :
152 pd_info->req_w_mask);
154 regmap_update_bits(pmu->regmap, pmu->info->req_offset,
155 pd_info->req_mask, idle ? -1U : 0);
159 /* Wait util idle_ack = 1 */
160 target_ack = idle ? pd_info->ack_mask : 0;
161 ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val,
162 (val & pd_info->ack_mask) == target_ack,
166 "failed to get ack on domain '%s', val=0x%x\n",
171 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle, pd,
172 is_idle, is_idle == idle, 0, 10000);
175 "failed to set idle on domain '%s', val=%d\n",
176 genpd->name, is_idle);
183 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
187 for (i = 0; i < pd->num_qos; i++) {
188 regmap_read(pd->qos_regmap[i],
190 &pd->qos_save_regs[0][i]);
191 regmap_read(pd->qos_regmap[i],
193 &pd->qos_save_regs[1][i]);
194 regmap_read(pd->qos_regmap[i],
196 &pd->qos_save_regs[2][i]);
197 regmap_read(pd->qos_regmap[i],
199 &pd->qos_save_regs[3][i]);
200 regmap_read(pd->qos_regmap[i],
202 &pd->qos_save_regs[4][i]);
207 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
211 for (i = 0; i < pd->num_qos; i++) {
212 regmap_write(pd->qos_regmap[i],
214 pd->qos_save_regs[0][i]);
215 regmap_write(pd->qos_regmap[i],
217 pd->qos_save_regs[1][i]);
218 regmap_write(pd->qos_regmap[i],
220 pd->qos_save_regs[2][i]);
221 regmap_write(pd->qos_regmap[i],
223 pd->qos_save_regs[3][i]);
224 regmap_write(pd->qos_regmap[i],
226 pd->qos_save_regs[4][i]);
232 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
234 struct rockchip_pmu *pmu = pd->pmu;
237 /* check idle status for idle-only domains */
238 if (pd->info->status_mask == 0)
239 return !rockchip_pmu_domain_is_idle(pd);
241 regmap_read(pmu->regmap, pmu->info->status_offset, &val);
243 /* 1'b0: power on, 1'b1: power off */
244 return !(val & pd->info->status_mask);
247 static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
250 struct rockchip_pmu *pmu = pd->pmu;
251 struct generic_pm_domain *genpd = &pd->genpd;
254 if (pd->info->pwr_mask == 0)
256 else if (pd->info->pwr_w_mask)
257 regmap_write(pmu->regmap, pmu->info->pwr_offset,
258 on ? pd->info->pwr_mask :
259 (pd->info->pwr_mask | pd->info->pwr_w_mask));
261 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,
262 pd->info->pwr_mask, on ? 0 : -1U);
266 if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
267 is_on == on, 0, 10000)) {
269 "failed to set domain '%s', val=%d\n",
275 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
277 struct rockchip_pmu *pmu = pd->pmu;
280 mutex_lock(&pmu->mutex);
282 if (rockchip_pmu_domain_is_on(pd) != power_on) {
283 ret = clk_bulk_enable(pd->num_clks, pd->clks);
285 dev_err(pmu->dev, "failed to enable clocks\n");
286 mutex_unlock(&pmu->mutex);
291 rockchip_pmu_save_qos(pd);
293 /* if powering down, idle request to NIU first */
294 rockchip_pmu_set_idle_request(pd, true);
297 rockchip_do_pmu_set_power_domain(pd, power_on);
300 /* if powering up, leave idle mode */
301 rockchip_pmu_set_idle_request(pd, false);
303 rockchip_pmu_restore_qos(pd);
306 clk_bulk_disable(pd->num_clks, pd->clks);
309 mutex_unlock(&pmu->mutex);
313 static int rockchip_pd_power_on(struct generic_pm_domain *domain)
315 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
317 return rockchip_pd_power(pd, true);
320 static int rockchip_pd_power_off(struct generic_pm_domain *domain)
322 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
324 return rockchip_pd_power(pd, false);
327 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
334 dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
336 error = pm_clk_create(dev);
338 dev_err(dev, "pm_clk_create failed %d\n", error);
343 while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
344 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
345 error = pm_clk_add_clk(dev, clk);
347 dev_err(dev, "pm_clk_add_clk failed %d\n", error);
357 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
360 dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
365 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
366 struct device_node *node)
368 const struct rockchip_domain_info *pd_info;
369 struct rockchip_pm_domain *pd;
370 struct device_node *qos_node;
375 error = of_property_read_u32(node, "reg", &id);
378 "%s: failed to retrieve domain id (reg): %d\n",
383 if (id >= pmu->info->num_domains) {
384 dev_err(pmu->dev, "%s: invalid domain id %d\n",
389 pd_info = &pmu->info->domain_info[id];
391 dev_err(pmu->dev, "%s: undefined domain id %d\n",
396 pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL);
403 pd->num_clks = of_count_phandle_with_args(node, "clocks",
405 if (pd->num_clks > 0) {
406 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
407 sizeof(*pd->clks), GFP_KERNEL);
411 dev_dbg(pmu->dev, "%s: doesn't have clocks: %d\n",
412 node->name, pd->num_clks);
416 for (i = 0; i < pd->num_clks; i++) {
417 pd->clks[i].clk = of_clk_get(node, i);
418 if (IS_ERR(pd->clks[i].clk)) {
419 error = PTR_ERR(pd->clks[i].clk);
421 "%s: failed to get clk at index %d: %d\n",
422 node->name, i, error);
427 error = clk_bulk_prepare(pd->num_clks, pd->clks);
431 pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
434 if (pd->num_qos > 0) {
435 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
436 sizeof(*pd->qos_regmap),
438 if (!pd->qos_regmap) {
440 goto err_unprepare_clocks;
443 for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
444 pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
448 if (!pd->qos_save_regs[j]) {
450 goto err_unprepare_clocks;
454 for (j = 0; j < pd->num_qos; j++) {
455 qos_node = of_parse_phandle(node, "pm_qos", j);
458 goto err_unprepare_clocks;
460 pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
461 if (IS_ERR(pd->qos_regmap[j])) {
463 of_node_put(qos_node);
464 goto err_unprepare_clocks;
466 of_node_put(qos_node);
470 error = rockchip_pd_power(pd, true);
473 "failed to power on domain '%s': %d\n",
475 goto err_unprepare_clocks;
478 pd->genpd.name = node->name;
479 pd->genpd.power_off = rockchip_pd_power_off;
480 pd->genpd.power_on = rockchip_pd_power_on;
481 pd->genpd.attach_dev = rockchip_pd_attach_dev;
482 pd->genpd.detach_dev = rockchip_pd_detach_dev;
483 pd->genpd.flags = GENPD_FLAG_PM_CLK;
484 if (pd_info->active_wakeup)
485 pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
486 pm_genpd_init(&pd->genpd, NULL, false);
488 pmu->genpd_data.domains[id] = &pd->genpd;
491 err_unprepare_clocks:
492 clk_bulk_unprepare(pd->num_clks, pd->clks);
494 clk_bulk_put(pd->num_clks, pd->clks);
498 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
503 * We're in the error cleanup already, so we only complain,
504 * but won't emit another error on top of the original one.
506 ret = pm_genpd_remove(&pd->genpd);
508 dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n",
509 pd->genpd.name, ret);
511 clk_bulk_unprepare(pd->num_clks, pd->clks);
512 clk_bulk_put(pd->num_clks, pd->clks);
514 /* protect the zeroing of pm->num_clks */
515 mutex_lock(&pd->pmu->mutex);
517 mutex_unlock(&pd->pmu->mutex);
519 /* devm will free our memory */
522 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
524 struct generic_pm_domain *genpd;
525 struct rockchip_pm_domain *pd;
528 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
529 genpd = pmu->genpd_data.domains[i];
531 pd = to_rockchip_pd(genpd);
532 rockchip_pm_remove_one_domain(pd);
536 /* devm will free our memory */
539 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
540 u32 domain_reg_offset,
543 /* First configure domain power down transition count ... */
544 regmap_write(pmu->regmap, domain_reg_offset, count);
545 /* ... and then power up count. */
546 regmap_write(pmu->regmap, domain_reg_offset + 4, count);
549 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
550 struct device_node *parent)
552 struct device_node *np;
553 struct generic_pm_domain *child_domain, *parent_domain;
556 for_each_child_of_node(parent, np) {
559 error = of_property_read_u32(parent, "reg", &idx);
562 "%s: failed to retrieve domain id (reg): %d\n",
563 parent->name, error);
566 parent_domain = pmu->genpd_data.domains[idx];
568 error = rockchip_pm_add_one_domain(pmu, np);
570 dev_err(pmu->dev, "failed to handle node %s: %d\n",
575 error = of_property_read_u32(np, "reg", &idx);
578 "%s: failed to retrieve domain id (reg): %d\n",
582 child_domain = pmu->genpd_data.domains[idx];
584 error = pm_genpd_add_subdomain(parent_domain, child_domain);
586 dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
587 parent_domain->name, child_domain->name, error);
590 dev_dbg(pmu->dev, "%s add subdomain: %s\n",
591 parent_domain->name, child_domain->name);
594 rockchip_pm_add_subdomain(pmu, np);
604 static int rockchip_pm_domain_probe(struct platform_device *pdev)
606 struct device *dev = &pdev->dev;
607 struct device_node *np = dev->of_node;
608 struct device_node *node;
609 struct device *parent;
610 struct rockchip_pmu *pmu;
611 const struct of_device_id *match;
612 const struct rockchip_pmu_info *pmu_info;
616 dev_err(dev, "device tree node not found\n");
620 match = of_match_device(dev->driver->of_match_table, dev);
621 if (!match || !match->data) {
622 dev_err(dev, "missing pmu data\n");
626 pmu_info = match->data;
628 pmu = devm_kzalloc(dev,
630 pmu_info->num_domains * sizeof(pmu->domains[0]),
635 pmu->dev = &pdev->dev;
636 mutex_init(&pmu->mutex);
638 pmu->info = pmu_info;
640 pmu->genpd_data.domains = pmu->domains;
641 pmu->genpd_data.num_domains = pmu_info->num_domains;
643 parent = dev->parent;
645 dev_err(dev, "no parent for syscon devices\n");
649 pmu->regmap = syscon_node_to_regmap(parent->of_node);
650 if (IS_ERR(pmu->regmap)) {
651 dev_err(dev, "no regmap available\n");
652 return PTR_ERR(pmu->regmap);
656 * Configure power up and down transition delays for CORE
659 if (pmu_info->core_power_transition_time)
660 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
661 pmu_info->core_power_transition_time);
662 if (pmu_info->gpu_pwrcnt_offset)
663 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
664 pmu_info->gpu_power_transition_time);
668 for_each_available_child_of_node(np, node) {
669 error = rockchip_pm_add_one_domain(pmu, node);
671 dev_err(dev, "failed to handle node %s: %d\n",
677 error = rockchip_pm_add_subdomain(pmu, node);
679 dev_err(dev, "failed to handle subdomain node %s: %d\n",
687 dev_dbg(dev, "no power domains defined\n");
691 error = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
693 dev_err(dev, "failed to add provider: %d\n", error);
700 rockchip_pm_domain_cleanup(pmu);
704 static const struct rockchip_domain_info rk3288_pm_domains[] = {
705 [RK3288_PD_VIO] = DOMAIN_RK3288(7, 7, 4, false),
706 [RK3288_PD_HEVC] = DOMAIN_RK3288(14, 10, 9, false),
707 [RK3288_PD_VIDEO] = DOMAIN_RK3288(8, 8, 3, false),
708 [RK3288_PD_GPU] = DOMAIN_RK3288(9, 9, 2, false),
711 static const struct rockchip_domain_info rk3328_pm_domains[] = {
712 [RK3328_PD_CORE] = DOMAIN_RK3328(-1, 0, 0, false),
713 [RK3328_PD_GPU] = DOMAIN_RK3328(-1, 1, 1, false),
714 [RK3328_PD_BUS] = DOMAIN_RK3328(-1, 2, 2, true),
715 [RK3328_PD_MSCH] = DOMAIN_RK3328(-1, 3, 3, true),
716 [RK3328_PD_PERI] = DOMAIN_RK3328(-1, 4, 4, true),
717 [RK3328_PD_VIDEO] = DOMAIN_RK3328(-1, 5, 5, false),
718 [RK3328_PD_HEVC] = DOMAIN_RK3328(-1, 6, 6, false),
719 [RK3328_PD_VIO] = DOMAIN_RK3328(-1, 8, 8, false),
720 [RK3328_PD_VPU] = DOMAIN_RK3328(-1, 9, 9, false),
723 static const struct rockchip_domain_info rk3366_pm_domains[] = {
724 [RK3366_PD_PERI] = DOMAIN_RK3368(10, 10, 6, true),
725 [RK3366_PD_VIO] = DOMAIN_RK3368(14, 14, 8, false),
726 [RK3366_PD_VIDEO] = DOMAIN_RK3368(13, 13, 7, false),
727 [RK3366_PD_RKVDEC] = DOMAIN_RK3368(11, 11, 7, false),
728 [RK3366_PD_WIFIBT] = DOMAIN_RK3368(8, 8, 9, false),
729 [RK3366_PD_VPU] = DOMAIN_RK3368(12, 12, 7, false),
730 [RK3366_PD_GPU] = DOMAIN_RK3368(15, 15, 2, false),
733 static const struct rockchip_domain_info rk3368_pm_domains[] = {
734 [RK3368_PD_PERI] = DOMAIN_RK3368(13, 12, 6, true),
735 [RK3368_PD_VIO] = DOMAIN_RK3368(15, 14, 8, false),
736 [RK3368_PD_VIDEO] = DOMAIN_RK3368(14, 13, 7, false),
737 [RK3368_PD_GPU_0] = DOMAIN_RK3368(16, 15, 2, false),
738 [RK3368_PD_GPU_1] = DOMAIN_RK3368(17, 16, 2, false),
741 static const struct rockchip_domain_info rk3399_pm_domains[] = {
742 [RK3399_PD_TCPD0] = DOMAIN_RK3399(8, 8, -1, false),
743 [RK3399_PD_TCPD1] = DOMAIN_RK3399(9, 9, -1, false),
744 [RK3399_PD_CCI] = DOMAIN_RK3399(10, 10, -1, true),
745 [RK3399_PD_CCI0] = DOMAIN_RK3399(-1, -1, 15, true),
746 [RK3399_PD_CCI1] = DOMAIN_RK3399(-1, -1, 16, true),
747 [RK3399_PD_PERILP] = DOMAIN_RK3399(11, 11, 1, true),
748 [RK3399_PD_PERIHP] = DOMAIN_RK3399(12, 12, 2, true),
749 [RK3399_PD_CENTER] = DOMAIN_RK3399(13, 13, 14, true),
750 [RK3399_PD_VIO] = DOMAIN_RK3399(14, 14, 17, false),
751 [RK3399_PD_GPU] = DOMAIN_RK3399(15, 15, 0, false),
752 [RK3399_PD_VCODEC] = DOMAIN_RK3399(16, 16, 3, false),
753 [RK3399_PD_VDU] = DOMAIN_RK3399(17, 17, 4, false),
754 [RK3399_PD_RGA] = DOMAIN_RK3399(18, 18, 5, false),
755 [RK3399_PD_IEP] = DOMAIN_RK3399(19, 19, 6, false),
756 [RK3399_PD_VO] = DOMAIN_RK3399(20, 20, -1, false),
757 [RK3399_PD_VOPB] = DOMAIN_RK3399(-1, -1, 7, false),
758 [RK3399_PD_VOPL] = DOMAIN_RK3399(-1, -1, 8, false),
759 [RK3399_PD_ISP0] = DOMAIN_RK3399(22, 22, 9, false),
760 [RK3399_PD_ISP1] = DOMAIN_RK3399(23, 23, 10, false),
761 [RK3399_PD_HDCP] = DOMAIN_RK3399(24, 24, 11, false),
762 [RK3399_PD_GMAC] = DOMAIN_RK3399(25, 25, 23, true),
763 [RK3399_PD_EMMC] = DOMAIN_RK3399(26, 26, 24, true),
764 [RK3399_PD_USB3] = DOMAIN_RK3399(27, 27, 12, true),
765 [RK3399_PD_EDP] = DOMAIN_RK3399(28, 28, 22, false),
766 [RK3399_PD_GIC] = DOMAIN_RK3399(29, 29, 27, true),
767 [RK3399_PD_SD] = DOMAIN_RK3399(30, 30, 28, true),
768 [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(31, 31, 29, true),
771 static const struct rockchip_pmu_info rk3288_pmu = {
773 .status_offset = 0x0c,
778 .core_pwrcnt_offset = 0x34,
779 .gpu_pwrcnt_offset = 0x3c,
781 .core_power_transition_time = 24, /* 1us */
782 .gpu_power_transition_time = 24, /* 1us */
784 .num_domains = ARRAY_SIZE(rk3288_pm_domains),
785 .domain_info = rk3288_pm_domains,
788 static const struct rockchip_pmu_info rk3328_pmu = {
790 .idle_offset = 0x484,
793 .num_domains = ARRAY_SIZE(rk3328_pm_domains),
794 .domain_info = rk3328_pm_domains,
797 static const struct rockchip_pmu_info rk3366_pmu = {
799 .status_offset = 0x10,
804 .core_pwrcnt_offset = 0x48,
805 .gpu_pwrcnt_offset = 0x50,
807 .core_power_transition_time = 24,
808 .gpu_power_transition_time = 24,
810 .num_domains = ARRAY_SIZE(rk3366_pm_domains),
811 .domain_info = rk3366_pm_domains,
814 static const struct rockchip_pmu_info rk3368_pmu = {
816 .status_offset = 0x10,
821 .core_pwrcnt_offset = 0x48,
822 .gpu_pwrcnt_offset = 0x50,
824 .core_power_transition_time = 24,
825 .gpu_power_transition_time = 24,
827 .num_domains = ARRAY_SIZE(rk3368_pm_domains),
828 .domain_info = rk3368_pm_domains,
831 static const struct rockchip_pmu_info rk3399_pmu = {
833 .status_offset = 0x18,
838 /* ARM Trusted Firmware manages power transition times */
840 .num_domains = ARRAY_SIZE(rk3399_pm_domains),
841 .domain_info = rk3399_pm_domains,
844 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
846 .compatible = "rockchip,rk3288-power-controller",
847 .data = (void *)&rk3288_pmu,
850 .compatible = "rockchip,rk3328-power-controller",
851 .data = (void *)&rk3328_pmu,
854 .compatible = "rockchip,rk3366-power-controller",
855 .data = (void *)&rk3366_pmu,
858 .compatible = "rockchip,rk3368-power-controller",
859 .data = (void *)&rk3368_pmu,
862 .compatible = "rockchip,rk3399-power-controller",
863 .data = (void *)&rk3399_pmu,
868 static struct platform_driver rockchip_pm_domain_driver = {
869 .probe = rockchip_pm_domain_probe,
871 .name = "rockchip-pm-domain",
872 .of_match_table = rockchip_pm_domain_dt_match,
874 * We can't forcibly eject devices form power domain,
875 * so we can't really remove power domains once they
878 .suppress_bind_attrs = true,
882 static int __init rockchip_pm_domain_drv_register(void)
884 return platform_driver_register(&rockchip_pm_domain_driver);
886 postcore_initcall(rockchip_pm_domain_drv_register);