1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
7 #include <linux/iopoll.h>
8 #include <linux/module.h>
9 #include <linux/of_device.h>
10 #include <linux/of_address.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
13 #include <linux/soc/mediatek/mtk-mmsys.h>
14 #include <linux/soc/mediatek/mtk-mutex.h>
15 #include <linux/soc/mediatek/mtk-cmdq.h>
17 #define MT2701_MUTEX0_MOD0 0x2c
18 #define MT2701_MUTEX0_SOF0 0x30
19 #define MT8183_MUTEX0_MOD0 0x30
20 #define MT8183_MUTEX0_SOF0 0x2c
22 #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
23 #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
24 #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
25 #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n))
26 #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n))
27 #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
29 #define INT_MUTEX BIT(1)
31 #define MT8186_MUTEX_MOD_DISP_OVL0 0
32 #define MT8186_MUTEX_MOD_DISP_OVL0_2L 1
33 #define MT8186_MUTEX_MOD_DISP_RDMA0 2
34 #define MT8186_MUTEX_MOD_DISP_COLOR0 4
35 #define MT8186_MUTEX_MOD_DISP_CCORR0 5
36 #define MT8186_MUTEX_MOD_DISP_AAL0 7
37 #define MT8186_MUTEX_MOD_DISP_GAMMA0 8
38 #define MT8186_MUTEX_MOD_DISP_POSTMASK0 9
39 #define MT8186_MUTEX_MOD_DISP_DITHER0 10
40 #define MT8186_MUTEX_MOD_DISP_RDMA1 17
42 #define MT8186_MUTEX_SOF_SINGLE_MODE 0
43 #define MT8186_MUTEX_SOF_DSI0 1
44 #define MT8186_MUTEX_SOF_DPI0 2
45 #define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6)
46 #define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6)
48 #define MT8167_MUTEX_MOD_DISP_PWM 1
49 #define MT8167_MUTEX_MOD_DISP_OVL0 6
50 #define MT8167_MUTEX_MOD_DISP_OVL1 7
51 #define MT8167_MUTEX_MOD_DISP_RDMA0 8
52 #define MT8167_MUTEX_MOD_DISP_RDMA1 9
53 #define MT8167_MUTEX_MOD_DISP_WDMA0 10
54 #define MT8167_MUTEX_MOD_DISP_CCORR 11
55 #define MT8167_MUTEX_MOD_DISP_COLOR 12
56 #define MT8167_MUTEX_MOD_DISP_AAL 13
57 #define MT8167_MUTEX_MOD_DISP_GAMMA 14
58 #define MT8167_MUTEX_MOD_DISP_DITHER 15
59 #define MT8167_MUTEX_MOD_DISP_UFOE 16
61 #define MT8192_MUTEX_MOD_DISP_OVL0 0
62 #define MT8192_MUTEX_MOD_DISP_OVL0_2L 1
63 #define MT8192_MUTEX_MOD_DISP_RDMA0 2
64 #define MT8192_MUTEX_MOD_DISP_COLOR0 4
65 #define MT8192_MUTEX_MOD_DISP_CCORR0 5
66 #define MT8192_MUTEX_MOD_DISP_AAL0 6
67 #define MT8192_MUTEX_MOD_DISP_GAMMA0 7
68 #define MT8192_MUTEX_MOD_DISP_POSTMASK0 8
69 #define MT8192_MUTEX_MOD_DISP_DITHER0 9
70 #define MT8192_MUTEX_MOD_DISP_OVL2_2L 16
71 #define MT8192_MUTEX_MOD_DISP_RDMA4 17
73 #define MT8183_MUTEX_MOD_DISP_RDMA0 0
74 #define MT8183_MUTEX_MOD_DISP_RDMA1 1
75 #define MT8183_MUTEX_MOD_DISP_OVL0 9
76 #define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
77 #define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
78 #define MT8183_MUTEX_MOD_DISP_WDMA0 12
79 #define MT8183_MUTEX_MOD_DISP_COLOR0 13
80 #define MT8183_MUTEX_MOD_DISP_CCORR0 14
81 #define MT8183_MUTEX_MOD_DISP_AAL0 15
82 #define MT8183_MUTEX_MOD_DISP_GAMMA0 16
83 #define MT8183_MUTEX_MOD_DISP_DITHER0 17
85 #define MT8183_MUTEX_MOD_MDP_RDMA0 2
86 #define MT8183_MUTEX_MOD_MDP_RSZ0 4
87 #define MT8183_MUTEX_MOD_MDP_RSZ1 5
88 #define MT8183_MUTEX_MOD_MDP_TDSHP0 6
89 #define MT8183_MUTEX_MOD_MDP_WROT0 7
90 #define MT8183_MUTEX_MOD_MDP_WDMA 8
91 #define MT8183_MUTEX_MOD_MDP_AAL0 23
92 #define MT8183_MUTEX_MOD_MDP_CCORR0 24
94 #define MT8173_MUTEX_MOD_DISP_OVL0 11
95 #define MT8173_MUTEX_MOD_DISP_OVL1 12
96 #define MT8173_MUTEX_MOD_DISP_RDMA0 13
97 #define MT8173_MUTEX_MOD_DISP_RDMA1 14
98 #define MT8173_MUTEX_MOD_DISP_RDMA2 15
99 #define MT8173_MUTEX_MOD_DISP_WDMA0 16
100 #define MT8173_MUTEX_MOD_DISP_WDMA1 17
101 #define MT8173_MUTEX_MOD_DISP_COLOR0 18
102 #define MT8173_MUTEX_MOD_DISP_COLOR1 19
103 #define MT8173_MUTEX_MOD_DISP_AAL 20
104 #define MT8173_MUTEX_MOD_DISP_GAMMA 21
105 #define MT8173_MUTEX_MOD_DISP_UFOE 22
106 #define MT8173_MUTEX_MOD_DISP_PWM0 23
107 #define MT8173_MUTEX_MOD_DISP_PWM1 24
108 #define MT8173_MUTEX_MOD_DISP_OD 25
110 #define MT8195_MUTEX_MOD_DISP_OVL0 0
111 #define MT8195_MUTEX_MOD_DISP_WDMA0 1
112 #define MT8195_MUTEX_MOD_DISP_RDMA0 2
113 #define MT8195_MUTEX_MOD_DISP_COLOR0 3
114 #define MT8195_MUTEX_MOD_DISP_CCORR0 4
115 #define MT8195_MUTEX_MOD_DISP_AAL0 5
116 #define MT8195_MUTEX_MOD_DISP_GAMMA0 6
117 #define MT8195_MUTEX_MOD_DISP_DITHER0 7
118 #define MT8195_MUTEX_MOD_DISP_DSI0 8
119 #define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
120 #define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
121 #define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
122 #define MT8195_MUTEX_MOD_DISP_PWM0 27
124 #define MT8365_MUTEX_MOD_DISP_OVL0 7
125 #define MT8365_MUTEX_MOD_DISP_OVL0_2L 8
126 #define MT8365_MUTEX_MOD_DISP_RDMA0 9
127 #define MT8365_MUTEX_MOD_DISP_RDMA1 10
128 #define MT8365_MUTEX_MOD_DISP_WDMA0 11
129 #define MT8365_MUTEX_MOD_DISP_COLOR0 12
130 #define MT8365_MUTEX_MOD_DISP_CCORR 13
131 #define MT8365_MUTEX_MOD_DISP_AAL 14
132 #define MT8365_MUTEX_MOD_DISP_GAMMA 15
133 #define MT8365_MUTEX_MOD_DISP_DITHER 16
134 #define MT8365_MUTEX_MOD_DISP_DSI0 17
135 #define MT8365_MUTEX_MOD_DISP_PWM0 20
136 #define MT8365_MUTEX_MOD_DISP_DPI0 22
138 #define MT2712_MUTEX_MOD_DISP_PWM2 10
139 #define MT2712_MUTEX_MOD_DISP_OVL0 11
140 #define MT2712_MUTEX_MOD_DISP_OVL1 12
141 #define MT2712_MUTEX_MOD_DISP_RDMA0 13
142 #define MT2712_MUTEX_MOD_DISP_RDMA1 14
143 #define MT2712_MUTEX_MOD_DISP_RDMA2 15
144 #define MT2712_MUTEX_MOD_DISP_WDMA0 16
145 #define MT2712_MUTEX_MOD_DISP_WDMA1 17
146 #define MT2712_MUTEX_MOD_DISP_COLOR0 18
147 #define MT2712_MUTEX_MOD_DISP_COLOR1 19
148 #define MT2712_MUTEX_MOD_DISP_AAL0 20
149 #define MT2712_MUTEX_MOD_DISP_UFOE 22
150 #define MT2712_MUTEX_MOD_DISP_PWM0 23
151 #define MT2712_MUTEX_MOD_DISP_PWM1 24
152 #define MT2712_MUTEX_MOD_DISP_OD0 25
153 #define MT2712_MUTEX_MOD2_DISP_AAL1 33
154 #define MT2712_MUTEX_MOD2_DISP_OD1 34
156 #define MT2701_MUTEX_MOD_DISP_OVL 3
157 #define MT2701_MUTEX_MOD_DISP_WDMA 6
158 #define MT2701_MUTEX_MOD_DISP_COLOR 7
159 #define MT2701_MUTEX_MOD_DISP_BLS 9
160 #define MT2701_MUTEX_MOD_DISP_RDMA0 10
161 #define MT2701_MUTEX_MOD_DISP_RDMA1 12
163 #define MT2712_MUTEX_SOF_SINGLE_MODE 0
164 #define MT2712_MUTEX_SOF_DSI0 1
165 #define MT2712_MUTEX_SOF_DSI1 2
166 #define MT2712_MUTEX_SOF_DPI0 3
167 #define MT2712_MUTEX_SOF_DPI1 4
168 #define MT2712_MUTEX_SOF_DSI2 5
169 #define MT2712_MUTEX_SOF_DSI3 6
170 #define MT8167_MUTEX_SOF_DPI0 2
171 #define MT8167_MUTEX_SOF_DPI1 3
172 #define MT8183_MUTEX_SOF_DSI0 1
173 #define MT8183_MUTEX_SOF_DPI0 2
174 #define MT8195_MUTEX_SOF_DSI0 1
175 #define MT8195_MUTEX_SOF_DSI1 2
176 #define MT8195_MUTEX_SOF_DP_INTF0 3
177 #define MT8195_MUTEX_SOF_DP_INTF1 4
178 #define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
179 #define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
181 #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
182 #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
183 #define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
184 #define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
185 #define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
186 #define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
187 #define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
188 #define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
195 enum mtk_mutex_sof_id {
196 MUTEX_SOF_SINGLE_MODE,
208 struct mtk_mutex_data {
209 const unsigned int *mutex_mod;
210 const unsigned int *mutex_sof;
211 const unsigned int mutex_mod_reg;
212 const unsigned int mutex_sof_reg;
213 const unsigned int *mutex_table_mod;
217 struct mtk_mutex_ctx {
221 struct mtk_mutex mutex[10];
222 const struct mtk_mutex_data *data;
224 struct cmdq_client_reg cmdq_reg;
227 static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
228 [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
229 [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
230 [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
231 [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0,
232 [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1,
233 [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
236 static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
237 [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
238 [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
239 [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
240 [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1,
241 [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0,
242 [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1,
243 [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0,
244 [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1,
245 [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0,
246 [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1,
247 [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2,
248 [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0,
249 [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1,
250 [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2,
251 [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE,
252 [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0,
253 [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
256 static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
257 [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
258 [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
259 [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
260 [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
261 [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
262 [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
263 [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
264 [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM,
265 [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0,
266 [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1,
267 [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE,
268 [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
271 static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
272 [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
273 [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
274 [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
275 [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
276 [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD,
277 [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0,
278 [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1,
279 [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0,
280 [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1,
281 [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0,
282 [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1,
283 [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2,
284 [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE,
285 [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0,
286 [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
289 static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
290 [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
291 [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
292 [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
293 [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
294 [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
295 [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
296 [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
297 [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
298 [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
299 [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
300 [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
303 static const unsigned int mt8183_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
304 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8183_MUTEX_MOD_MDP_RDMA0,
305 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8183_MUTEX_MOD_MDP_RSZ0,
306 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8183_MUTEX_MOD_MDP_RSZ1,
307 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8183_MUTEX_MOD_MDP_TDSHP0,
308 [MUTEX_MOD_IDX_MDP_WROT0] = MT8183_MUTEX_MOD_MDP_WROT0,
309 [MUTEX_MOD_IDX_MDP_WDMA] = MT8183_MUTEX_MOD_MDP_WDMA,
310 [MUTEX_MOD_IDX_MDP_AAL0] = MT8183_MUTEX_MOD_MDP_AAL0,
311 [MUTEX_MOD_IDX_MDP_CCORR0] = MT8183_MUTEX_MOD_MDP_CCORR0,
314 static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
315 [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
316 [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
317 [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
318 [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
319 [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
320 [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
321 [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
322 [DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0,
323 [DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0,
324 [DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1,
327 static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
328 [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
329 [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
330 [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
331 [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
332 [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
333 [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
334 [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
335 [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L,
336 [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L,
337 [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0,
338 [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
341 static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
342 [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
343 [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
344 [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
345 [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
346 [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
347 [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
348 [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
349 [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
350 [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
351 [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
352 [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
353 [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
354 [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
357 static const unsigned int mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = {
358 [DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL,
359 [DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR,
360 [DDP_COMPONENT_COLOR0] = MT8365_MUTEX_MOD_DISP_COLOR0,
361 [DDP_COMPONENT_DITHER0] = MT8365_MUTEX_MOD_DISP_DITHER,
362 [DDP_COMPONENT_DPI0] = MT8365_MUTEX_MOD_DISP_DPI0,
363 [DDP_COMPONENT_DSI0] = MT8365_MUTEX_MOD_DISP_DSI0,
364 [DDP_COMPONENT_GAMMA] = MT8365_MUTEX_MOD_DISP_GAMMA,
365 [DDP_COMPONENT_OVL0] = MT8365_MUTEX_MOD_DISP_OVL0,
366 [DDP_COMPONENT_OVL_2L0] = MT8365_MUTEX_MOD_DISP_OVL0_2L,
367 [DDP_COMPONENT_PWM0] = MT8365_MUTEX_MOD_DISP_PWM0,
368 [DDP_COMPONENT_RDMA0] = MT8365_MUTEX_MOD_DISP_RDMA0,
369 [DDP_COMPONENT_RDMA1] = MT8365_MUTEX_MOD_DISP_RDMA1,
370 [DDP_COMPONENT_WDMA0] = MT8365_MUTEX_MOD_DISP_WDMA0,
373 static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
374 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
375 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
376 [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
377 [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0,
378 [MUTEX_SOF_DPI1] = MUTEX_SOF_DPI1,
379 [MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2,
380 [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
383 static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
384 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
385 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
386 [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
387 [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
390 /* Add EOF setting so overlay hardware can receive frame done irq */
391 static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
392 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
393 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
394 [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
397 static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
398 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
399 [MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0,
400 [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
404 * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
405 * select the EOF source and configure the EOF plus timing from the
406 * module that provides the timing signal.
407 * So that MUTEX can not only send a STREAM_DONE event to GCE
408 * but also detect the error at end of frame(EAEOF) when EOF signal
411 static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
412 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
413 [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
414 [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
415 [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
416 [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
417 [MUTEX_SOF_DP_INTF0] =
418 MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
419 [MUTEX_SOF_DP_INTF1] =
420 MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
423 static const struct mtk_mutex_data mt2701_mutex_driver_data = {
424 .mutex_mod = mt2701_mutex_mod,
425 .mutex_sof = mt2712_mutex_sof,
426 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
427 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
430 static const struct mtk_mutex_data mt2712_mutex_driver_data = {
431 .mutex_mod = mt2712_mutex_mod,
432 .mutex_sof = mt2712_mutex_sof,
433 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
434 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
437 static const struct mtk_mutex_data mt8167_mutex_driver_data = {
438 .mutex_mod = mt8167_mutex_mod,
439 .mutex_sof = mt8167_mutex_sof,
440 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
441 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
445 static const struct mtk_mutex_data mt8173_mutex_driver_data = {
446 .mutex_mod = mt8173_mutex_mod,
447 .mutex_sof = mt2712_mutex_sof,
448 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
449 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
452 static const struct mtk_mutex_data mt8183_mutex_driver_data = {
453 .mutex_mod = mt8183_mutex_mod,
454 .mutex_sof = mt8183_mutex_sof,
455 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
456 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
457 .mutex_table_mod = mt8183_mutex_table_mod,
461 static const struct mtk_mutex_data mt8186_mutex_driver_data = {
462 .mutex_mod = mt8186_mutex_mod,
463 .mutex_sof = mt8186_mutex_sof,
464 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
465 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
468 static const struct mtk_mutex_data mt8192_mutex_driver_data = {
469 .mutex_mod = mt8192_mutex_mod,
470 .mutex_sof = mt8183_mutex_sof,
471 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
472 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
475 static const struct mtk_mutex_data mt8195_mutex_driver_data = {
476 .mutex_mod = mt8195_mutex_mod,
477 .mutex_sof = mt8195_mutex_sof,
478 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
479 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
482 static const struct mtk_mutex_data mt8365_mutex_driver_data = {
483 .mutex_mod = mt8365_mutex_mod,
484 .mutex_sof = mt8183_mutex_sof,
485 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
486 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
490 struct mtk_mutex *mtk_mutex_get(struct device *dev)
492 struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
495 for (i = 0; i < 10; i++)
496 if (!mtx->mutex[i].claimed) {
497 mtx->mutex[i].claimed = true;
498 return &mtx->mutex[i];
501 return ERR_PTR(-EBUSY);
503 EXPORT_SYMBOL_GPL(mtk_mutex_get);
505 void mtk_mutex_put(struct mtk_mutex *mutex)
507 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
510 WARN_ON(&mtx->mutex[mutex->id] != mutex);
512 mutex->claimed = false;
514 EXPORT_SYMBOL_GPL(mtk_mutex_put);
516 int mtk_mutex_prepare(struct mtk_mutex *mutex)
518 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
520 return clk_prepare_enable(mtx->clk);
522 EXPORT_SYMBOL_GPL(mtk_mutex_prepare);
524 void mtk_mutex_unprepare(struct mtk_mutex *mutex)
526 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
528 clk_disable_unprepare(mtx->clk);
530 EXPORT_SYMBOL_GPL(mtk_mutex_unprepare);
532 void mtk_mutex_add_comp(struct mtk_mutex *mutex,
533 enum mtk_ddp_comp_id id)
535 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
541 WARN_ON(&mtx->mutex[mutex->id] != mutex);
544 case DDP_COMPONENT_DSI0:
545 sof_id = MUTEX_SOF_DSI0;
547 case DDP_COMPONENT_DSI1:
548 sof_id = MUTEX_SOF_DSI0;
550 case DDP_COMPONENT_DSI2:
551 sof_id = MUTEX_SOF_DSI2;
553 case DDP_COMPONENT_DSI3:
554 sof_id = MUTEX_SOF_DSI3;
556 case DDP_COMPONENT_DPI0:
557 sof_id = MUTEX_SOF_DPI0;
559 case DDP_COMPONENT_DPI1:
560 sof_id = MUTEX_SOF_DPI1;
562 case DDP_COMPONENT_DP_INTF0:
563 sof_id = MUTEX_SOF_DP_INTF0;
566 if (mtx->data->mutex_mod[id] < 32) {
567 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
569 reg = readl_relaxed(mtx->regs + offset);
570 reg |= 1 << mtx->data->mutex_mod[id];
571 writel_relaxed(reg, mtx->regs + offset);
573 offset = DISP_REG_MUTEX_MOD2(mutex->id);
574 reg = readl_relaxed(mtx->regs + offset);
575 reg |= 1 << (mtx->data->mutex_mod[id] - 32);
576 writel_relaxed(reg, mtx->regs + offset);
581 writel_relaxed(mtx->data->mutex_sof[sof_id],
583 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id));
585 EXPORT_SYMBOL_GPL(mtk_mutex_add_comp);
587 void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
588 enum mtk_ddp_comp_id id)
590 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
595 WARN_ON(&mtx->mutex[mutex->id] != mutex);
598 case DDP_COMPONENT_DSI0:
599 case DDP_COMPONENT_DSI1:
600 case DDP_COMPONENT_DSI2:
601 case DDP_COMPONENT_DSI3:
602 case DDP_COMPONENT_DPI0:
603 case DDP_COMPONENT_DPI1:
604 case DDP_COMPONENT_DP_INTF0:
605 writel_relaxed(MUTEX_SOF_SINGLE_MODE,
607 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
611 if (mtx->data->mutex_mod[id] < 32) {
612 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
614 reg = readl_relaxed(mtx->regs + offset);
615 reg &= ~(1 << mtx->data->mutex_mod[id]);
616 writel_relaxed(reg, mtx->regs + offset);
618 offset = DISP_REG_MUTEX_MOD2(mutex->id);
619 reg = readl_relaxed(mtx->regs + offset);
620 reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
621 writel_relaxed(reg, mtx->regs + offset);
626 EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
628 void mtk_mutex_enable(struct mtk_mutex *mutex)
630 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
633 WARN_ON(&mtx->mutex[mutex->id] != mutex);
635 writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
637 EXPORT_SYMBOL_GPL(mtk_mutex_enable);
639 int mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex, void *pkt)
641 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
643 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
644 struct cmdq_pkt *cmdq_pkt = (struct cmdq_pkt *)pkt;
646 WARN_ON(&mtx->mutex[mutex->id] != mutex);
648 if (!mtx->cmdq_reg.size) {
649 dev_err(mtx->dev, "mediatek,gce-client-reg hasn't been set");
653 cmdq_pkt_write(cmdq_pkt, mtx->cmdq_reg.subsys,
654 mtx->addr + DISP_REG_MUTEX_EN(mutex->id), 1);
657 dev_err(mtx->dev, "Not support for enable MUTEX by CMDQ");
661 EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
663 void mtk_mutex_disable(struct mtk_mutex *mutex)
665 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
668 WARN_ON(&mtx->mutex[mutex->id] != mutex);
670 writel(0, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
672 EXPORT_SYMBOL_GPL(mtk_mutex_disable);
674 void mtk_mutex_acquire(struct mtk_mutex *mutex)
676 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
680 writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
681 writel(1, mtx->regs + DISP_REG_MUTEX(mutex->id));
682 if (readl_poll_timeout_atomic(mtx->regs + DISP_REG_MUTEX(mutex->id),
683 tmp, tmp & INT_MUTEX, 1, 10000))
684 pr_err("could not acquire mutex %d\n", mutex->id);
686 EXPORT_SYMBOL_GPL(mtk_mutex_acquire);
688 void mtk_mutex_release(struct mtk_mutex *mutex)
690 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
693 writel(0, mtx->regs + DISP_REG_MUTEX(mutex->id));
695 EXPORT_SYMBOL_GPL(mtk_mutex_release);
697 int mtk_mutex_write_mod(struct mtk_mutex *mutex,
698 enum mtk_mutex_mod_index idx, bool clear)
700 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
705 WARN_ON(&mtx->mutex[mutex->id] != mutex);
707 if (idx < MUTEX_MOD_IDX_MDP_RDMA0 ||
708 idx >= MUTEX_MOD_IDX_MAX) {
709 dev_err(mtx->dev, "Not supported MOD table index : %d", idx);
713 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
715 reg = readl_relaxed(mtx->regs + offset);
718 reg &= ~BIT(mtx->data->mutex_table_mod[idx]);
720 reg |= BIT(mtx->data->mutex_table_mod[idx]);
722 writel_relaxed(reg, mtx->regs + offset);
726 EXPORT_SYMBOL_GPL(mtk_mutex_write_mod);
728 int mtk_mutex_write_sof(struct mtk_mutex *mutex,
729 enum mtk_mutex_sof_index idx)
731 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
734 WARN_ON(&mtx->mutex[mutex->id] != mutex);
736 if (idx < MUTEX_SOF_IDX_SINGLE_MODE ||
737 idx >= MUTEX_SOF_IDX_MAX) {
738 dev_err(mtx->dev, "Not supported SOF index : %d", idx);
742 writel_relaxed(idx, mtx->regs +
743 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id));
747 EXPORT_SYMBOL_GPL(mtk_mutex_write_sof);
749 static int mtk_mutex_probe(struct platform_device *pdev)
751 struct device *dev = &pdev->dev;
752 struct mtk_mutex_ctx *mtx;
753 struct resource *regs;
755 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
759 mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
763 for (i = 0; i < 10; i++)
764 mtx->mutex[i].id = i;
766 mtx->data = of_device_get_match_data(dev);
768 if (!mtx->data->no_clk) {
769 mtx->clk = devm_clk_get(dev, NULL);
770 if (IS_ERR(mtx->clk)) {
771 if (PTR_ERR(mtx->clk) != -EPROBE_DEFER)
772 dev_err(dev, "Failed to get clock\n");
773 return PTR_ERR(mtx->clk);
777 mtx->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
778 if (IS_ERR(mtx->regs)) {
779 dev_err(dev, "Failed to map mutex registers\n");
780 return PTR_ERR(mtx->regs);
782 mtx->addr = regs->start;
784 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
785 ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0);
787 dev_dbg(dev, "No mediatek,gce-client-reg!\n");
790 platform_set_drvdata(pdev, mtx);
795 static int mtk_mutex_remove(struct platform_device *pdev)
800 static const struct of_device_id mutex_driver_dt_match[] = {
801 { .compatible = "mediatek,mt2701-disp-mutex",
802 .data = &mt2701_mutex_driver_data},
803 { .compatible = "mediatek,mt2712-disp-mutex",
804 .data = &mt2712_mutex_driver_data},
805 { .compatible = "mediatek,mt8167-disp-mutex",
806 .data = &mt8167_mutex_driver_data},
807 { .compatible = "mediatek,mt8173-disp-mutex",
808 .data = &mt8173_mutex_driver_data},
809 { .compatible = "mediatek,mt8183-disp-mutex",
810 .data = &mt8183_mutex_driver_data},
811 { .compatible = "mediatek,mt8186-disp-mutex",
812 .data = &mt8186_mutex_driver_data},
813 { .compatible = "mediatek,mt8192-disp-mutex",
814 .data = &mt8192_mutex_driver_data},
815 { .compatible = "mediatek,mt8195-disp-mutex",
816 .data = &mt8195_mutex_driver_data},
817 { .compatible = "mediatek,mt8365-disp-mutex",
818 .data = &mt8365_mutex_driver_data},
821 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
823 static struct platform_driver mtk_mutex_driver = {
824 .probe = mtk_mutex_probe,
825 .remove = mtk_mutex_remove,
827 .name = "mediatek-mutex",
828 .owner = THIS_MODULE,
829 .of_match_table = mutex_driver_dt_match,
833 builtin_platform_driver(mtk_mutex_driver);