drivers/soc/imx/gpc.c

   1 /*
   2  * Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
   3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/io.h>
  16 #include <linux/of_device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_domain.h>
  19 #include <linux/regmap.h>
  20 #include <linux/regulator/consumer.h>
  21
  22 #define GPC_CNTR                0x000
  23
  24 #define GPC_PGC_CTRL_OFFS       0x0
  25 #define GPC_PGC_PUPSCR_OFFS     0x4
  26 #define GPC_PGC_PDNSCR_OFFS     0x8
  27 #define GPC_PGC_SW2ISO_SHIFT    0x8
  28 #define GPC_PGC_SW_SHIFT        0x0
  29
  30 #define GPC_PGC_GPU_PDN         0x260
  31 #define GPC_PGC_GPU_PUPSCR      0x264
  32 #define GPC_PGC_GPU_PDNSCR      0x268
  33
  34 #define GPU_VPU_PUP_REQ         BIT(1)
  35 #define GPU_VPU_PDN_REQ         BIT(0)
  36
  37 #define GPC_CLK_MAX             6
  38
  39 struct imx_pm_domain {
  40         struct generic_pm_domain base;
  41         struct regmap *regmap;
  42         struct regulator *supply;
  43         struct clk *clk[GPC_CLK_MAX];
  44         int num_clks;
  45         unsigned int reg_offs;
  46         signed char cntr_pdn_bit;
  47         unsigned int ipg_rate_mhz;
  48 };
  49
  50 static inline struct imx_pm_domain *
  51 to_imx_pm_domain(struct generic_pm_domain *genpd)
  52 {
  53         return container_of(genpd, struct imx_pm_domain, base);
  54 }
  55
  56 static int imx6_pm_domain_power_off(struct generic_pm_domain *genpd)
  57 {
  58         struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
  59         int iso, iso2sw;
  60         u32 val;
  61
  62         /* Read ISO and ISO2SW power down delays */
  63         regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val);
  64         iso = val & 0x3f;
  65         iso2sw = (val >> 8) & 0x3f;
  66
  67         /* Gate off domain when powered down */
  68         regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS,
  69                            0x1, 0x1);
  70
  71         /* Request GPC to power down domain */
  72         val = BIT(pd->cntr_pdn_bit);
  73         regmap_update_bits(pd->regmap, GPC_CNTR, val, val);
  74
  75         /* Wait ISO + ISO2SW IPG clock cycles */
  76         udelay(DIV_ROUND_UP(iso + iso2sw, pd->ipg_rate_mhz));
  77
  78         if (pd->supply)
  79                 regulator_disable(pd->supply);
  80
  81         return 0;
  82 }
  83
  84 static int imx6_pm_domain_power_on(struct generic_pm_domain *genpd)
  85 {
  86         struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
  87         int i, ret, sw, sw2iso;
  88         u32 val;
  89
  90         if (pd->supply) {
  91                 ret = regulator_enable(pd->supply);
  92                 if (ret) {
  93                         pr_err("%s: failed to enable regulator: %d\n",
  94                                __func__, ret);
  95                         return ret;
  96                 }
  97         }
  98
  99         /* Enable reset clocks for all devices in the domain */
 100         for (i = 0; i < pd->num_clks; i++)
 101                 clk_prepare_enable(pd->clk[i]);
 102
 103         /* Gate off domain when powered down */
 104         regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS,
 105                            0x1, 0x1);
 106
 107         /* Read ISO and ISO2SW power up delays */
 108         regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val);
 109         sw = val & 0x3f;
 110         sw2iso = (val >> 8) & 0x3f;
 111
 112         /* Request GPC to power up domain */
 113         val = BIT(pd->cntr_pdn_bit + 1);
 114         regmap_update_bits(pd->regmap, GPC_CNTR, val, val);
 115
 116         /* Wait ISO + ISO2SW IPG clock cycles */
 117         udelay(DIV_ROUND_UP(sw + sw2iso, pd->ipg_rate_mhz));
 118
 119         /* Disable reset clocks for all devices in the domain */
 120         for (i = 0; i < pd->num_clks; i++)
 121                 clk_disable_unprepare(pd->clk[i]);
 122
 123         return 0;
 124 }
 125
 126 static int imx_pgc_get_clocks(struct device *dev, struct imx_pm_domain *domain)
 127 {
 128         int i, ret;
 129
 130         for (i = 0; ; i++) {
 131                 struct clk *clk = of_clk_get(dev->of_node, i);
 132                 if (IS_ERR(clk))
 133                         break;
 134                 if (i >= GPC_CLK_MAX) {
 135                         dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
 136                         ret = -EINVAL;
 137                         goto clk_err;
 138                 }
 139                 domain->clk[i] = clk;
 140         }
 141         domain->num_clks = i;
 142
 143         return 0;
 144
 145 clk_err:
 146         while (i--)
 147                 clk_put(domain->clk[i]);
 148
 149         return ret;
 150 }
 151
 152 static void imx_pgc_put_clocks(struct imx_pm_domain *domain)
 153 {
 154         int i;
 155
 156         for (i = domain->num_clks - 1; i >= 0; i--)
 157                 clk_put(domain->clk[i]);
 158 }
 159
 160 static int imx_pgc_parse_dt(struct device *dev, struct imx_pm_domain *domain)
 161 {
 162         /* try to get the domain supply regulator */
 163         domain->supply = devm_regulator_get_optional(dev, "power");
 164         if (IS_ERR(domain->supply)) {
 165                 if (PTR_ERR(domain->supply) == -ENODEV)
 166                         domain->supply = NULL;
 167                 else
 168                         return PTR_ERR(domain->supply);
 169         }
 170
 171         /* try to get all clocks needed for reset propagation */
 172         return imx_pgc_get_clocks(dev, domain);
 173 }
 174
 175 static int imx_pgc_power_domain_probe(struct platform_device *pdev)
 176 {
 177         struct imx_pm_domain *domain = pdev->dev.platform_data;
 178         struct device *dev = &pdev->dev;
 179         int ret;
 180
 181         /* if this PD is associated with a DT node try to parse it */
 182         if (dev->of_node) {
 183                 ret = imx_pgc_parse_dt(dev, domain);
 184                 if (ret)
 185                         return ret;
 186         }
 187
 188         /* initially power on the domain */
 189         if (domain->base.power_on)
 190                 domain->base.power_on(&domain->base);
 191
 192         if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
 193                 pm_genpd_init(&domain->base, NULL, false);
 194                 ret = of_genpd_add_provider_simple(dev->of_node, &domain->base);
 195                 if (ret)
 196                         goto genpd_err;
 197         }
 198
 199         device_link_add(dev, dev->parent, DL_FLAG_AUTOREMOVE);
 200
 201         return 0;
 202
 203 genpd_err:
 204         pm_genpd_remove(&domain->base);
 205         imx_pgc_put_clocks(domain);
 206
 207         return ret;
 208 }
 209
 210 static int imx_pgc_power_domain_remove(struct platform_device *pdev)
 211 {
 212         struct imx_pm_domain *domain = pdev->dev.platform_data;
 213
 214         if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
 215                 of_genpd_del_provider(pdev->dev.of_node);
 216                 pm_genpd_remove(&domain->base);
 217                 imx_pgc_put_clocks(domain);
 218         }
 219
 220         return 0;
 221 }
 222
 223 static const struct platform_device_id imx_pgc_power_domain_id[] = {
 224         { "imx-pgc-power-domain"},
 225         { },
 226 };
 227
 228 static struct platform_driver imx_pgc_power_domain_driver = {
 229         .driver = {
 230                 .name = "imx-pgc-pd",
 231         },
 232         .probe = imx_pgc_power_domain_probe,
 233         .remove = imx_pgc_power_domain_remove,
 234         .id_table = imx_pgc_power_domain_id,
 235 };
 236 builtin_platform_driver(imx_pgc_power_domain_driver)
 237
 238 #define GPC_PGC_DOMAIN_ARM      0
 239 #define GPC_PGC_DOMAIN_PU       1
 240 #define GPC_PGC_DOMAIN_DISPLAY  2
 241
 242 static struct genpd_power_state imx6_pm_domain_pu_state = {
 243         .power_off_latency_ns = 25000,
 244         .power_on_latency_ns = 2000000,
 245 };
 246
 247 static struct imx_pm_domain imx_gpc_domains[] = {
 248         {
 249                 .base = {
 250                         .name = "ARM",
 251                 },
 252         }, {
 253                 .base = {
 254                         .name = "PU",
 255                         .power_off = imx6_pm_domain_power_off,
 256                         .power_on = imx6_pm_domain_power_on,
 257                         .states = &imx6_pm_domain_pu_state,
 258                         .state_count = 1,
 259                 },
 260                 .reg_offs = 0x260,
 261                 .cntr_pdn_bit = 0,
 262         }, {
 263                 .base = {
 264                         .name = "DISPLAY",
 265                         .power_off = imx6_pm_domain_power_off,
 266                         .power_on = imx6_pm_domain_power_on,
 267                 },
 268                 .reg_offs = 0x240,
 269                 .cntr_pdn_bit = 4,
 270         }
 271 };
 272
 273 struct imx_gpc_dt_data {
 274         int num_domains;
 275 };
 276
 277 static const struct imx_gpc_dt_data imx6q_dt_data = {
 278         .num_domains = 2,
 279 };
 280
 281 static const struct imx_gpc_dt_data imx6sl_dt_data = {
 282         .num_domains = 3,
 283 };
 284
 285 static const struct of_device_id imx_gpc_dt_ids[] = {
 286         { .compatible = "fsl,imx6q-gpc", .data = &imx6q_dt_data },
 287         { .compatible = "fsl,imx6sl-gpc", .data = &imx6sl_dt_data },
 288         { }
 289 };
 290
 291 static const struct regmap_config imx_gpc_regmap_config = {
 292         .reg_bits = 32,
 293         .val_bits = 32,
 294         .reg_stride = 4,
 295         .max_register = 0x2ac,
 296 };
 297
 298 static struct generic_pm_domain *imx_gpc_onecell_domains[] = {
 299         &imx_gpc_domains[0].base,
 300         &imx_gpc_domains[1].base,
 301 };
 302
 303 static struct genpd_onecell_data imx_gpc_onecell_data = {
 304         .domains = imx_gpc_onecell_domains,
 305         .num_domains = 2,
 306 };
 307
 308 static int imx_gpc_old_dt_init(struct device *dev, struct regmap *regmap,
 309                                unsigned int num_domains)
 310 {
 311         struct imx_pm_domain *domain;
 312         int i, ret;
 313
 314         for (i = 0; i < num_domains; i++) {
 315                 domain = &imx_gpc_domains[i];
 316                 domain->regmap = regmap;
 317                 domain->ipg_rate_mhz = 66;
 318
 319                 if (i == 1) {
 320                         domain->supply = devm_regulator_get(dev, "pu");
 321                         if (IS_ERR(domain->supply))
 322                                 return PTR_ERR(domain->supply);;
 323
 324                         ret = imx_pgc_get_clocks(dev, domain);
 325                         if (ret)
 326                                 goto clk_err;
 327
 328                         domain->base.power_on(&domain->base);
 329                 }
 330         }
 331
 332         for (i = 0; i < num_domains; i++)
 333                 pm_genpd_init(&imx_gpc_domains[i].base, NULL, false);
 334
 335         if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
 336                 ret = of_genpd_add_provider_onecell(dev->of_node,
 337                                                     &imx_gpc_onecell_data);
 338                 if (ret)
 339                         goto genpd_err;
 340         }
 341
 342         return 0;
 343
 344 genpd_err:
 345         for (i = 0; i < num_domains; i++)
 346                 pm_genpd_remove(&imx_gpc_domains[i].base);
 347         imx_pgc_put_clocks(&imx_gpc_domains[GPC_PGC_DOMAIN_PU]);
 348 clk_err:
 349         return ret;
 350 }
 351
 352 static int imx_gpc_probe(struct platform_device *pdev)
 353 {
 354         const struct of_device_id *of_id =
 355                         of_match_device(imx_gpc_dt_ids, &pdev->dev);
 356         const struct imx_gpc_dt_data *of_id_data = of_id->data;
 357         struct device_node *pgc_node;
 358         struct regmap *regmap;
 359         struct resource *res;
 360         void __iomem *base;
 361         int ret;
 362
 363         pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");
 364
 365         /* bail out if DT too old and doesn't provide the necessary info */
 366         if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
 367             !pgc_node)
 368                 return 0;
 369
 370         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 371         base = devm_ioremap_resource(&pdev->dev, res);
 372         if (IS_ERR(base))
 373                 return PTR_ERR(base);
 374
 375         regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
 376                                            &imx_gpc_regmap_config);
 377         if (IS_ERR(regmap)) {
 378                 ret = PTR_ERR(regmap);
 379                 dev_err(&pdev->dev, "failed to init regmap: %d\n",
 380                         ret);
 381                 return ret;
 382         }
 383
 384         if (!pgc_node) {
 385                 ret = imx_gpc_old_dt_init(&pdev->dev, regmap,
 386                                           of_id_data->num_domains);
 387                 if (ret)
 388                         return ret;
 389         } else {
 390                 struct imx_pm_domain *domain;
 391                 struct platform_device *pd_pdev;
 392                 struct device_node *np;
 393                 struct clk *ipg_clk;
 394                 unsigned int ipg_rate_mhz;
 395                 int domain_index;
 396
 397                 ipg_clk = devm_clk_get(&pdev->dev, "ipg");
 398                 if (IS_ERR(ipg_clk))
 399                         return PTR_ERR(ipg_clk);
 400                 ipg_rate_mhz = clk_get_rate(ipg_clk) / 1000000;
 401
 402                 for_each_child_of_node(pgc_node, np) {
 403                         ret = of_property_read_u32(np, "reg", &domain_index);
 404                         if (ret) {
 405                                 of_node_put(np);
 406                                 return ret;
 407                         }
 408                         if (domain_index >= of_id_data->num_domains)
 409                                 continue;
 410
 411                         domain = &imx_gpc_domains[domain_index];
 412                         domain->regmap = regmap;
 413                         domain->ipg_rate_mhz = ipg_rate_mhz;
 414
 415                         pd_pdev = platform_device_alloc("imx-pgc-power-domain",
 416                                                         domain_index);
 417                         if (!pd_pdev) {
 418                                 of_node_put(np);
 419                                 return -ENOMEM;
 420                         }
 421                         pd_pdev->dev.platform_data = domain;
 422                         pd_pdev->dev.parent = &pdev->dev;
 423                         pd_pdev->dev.of_node = np;
 424
 425                         ret = platform_device_add(pd_pdev);
 426                         if (ret) {
 427                                 platform_device_put(pd_pdev);
 428                                 of_node_put(np);
 429                                 return ret;
 430                         }
 431                 }
 432         }
 433
 434         return 0;
 435 }
 436
 437 static int imx_gpc_remove(struct platform_device *pdev)
 438 {
 439         int ret;
 440
 441         /*
 442          * If the old DT binding is used the toplevel driver needs to
 443          * de-register the power domains
 444          */
 445         if (!of_get_child_by_name(pdev->dev.of_node, "pgc")) {
 446                 of_genpd_del_provider(pdev->dev.of_node);
 447
 448                 ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_PU].base);
 449                 if (ret)
 450                         return ret;
 451                 imx_pgc_put_clocks(&imx_gpc_domains[GPC_PGC_DOMAIN_PU]);
 452
 453                 ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_ARM].base);
 454                 if (ret)
 455                         return ret;
 456         }
 457
 458         return 0;
 459 }
 460
 461 static struct platform_driver imx_gpc_driver = {
 462         .driver = {
 463                 .name = "imx-gpc",
 464                 .of_match_table = imx_gpc_dt_ids,
 465         },
 466         .probe = imx_gpc_probe,
 467         .remove = imx_gpc_remove,
 468 };
 469 builtin_platform_driver(imx_gpc_driver)