drivers/soc/bcm/bcm2835-power.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Power domain driver for Broadcom BCM2835
   4  *
   5  * Copyright (C) 2018 Broadcom
   6  */
   7
   8 #include <dt-bindings/soc/bcm2835-pm.h>
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/io.h>
  12 #include <linux/mfd/bcm2835-pm.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_domain.h>
  16 #include <linux/reset-controller.h>
  17 #include <linux/types.h>
  18
  19 #define PM_GNRIC                        0x00
  20 #define PM_AUDIO                        0x04
  21 #define PM_STATUS                       0x18
  22 #define PM_RSTC                         0x1c
  23 #define PM_RSTS                         0x20
  24 #define PM_WDOG                         0x24
  25 #define PM_PADS0                        0x28
  26 #define PM_PADS2                        0x2c
  27 #define PM_PADS3                        0x30
  28 #define PM_PADS4                        0x34
  29 #define PM_PADS5                        0x38
  30 #define PM_PADS6                        0x3c
  31 #define PM_CAM0                         0x44
  32 #define PM_CAM0_LDOHPEN                 BIT(2)
  33 #define PM_CAM0_LDOLPEN                 BIT(1)
  34 #define PM_CAM0_CTRLEN                  BIT(0)
  35
  36 #define PM_CAM1                         0x48
  37 #define PM_CAM1_LDOHPEN                 BIT(2)
  38 #define PM_CAM1_LDOLPEN                 BIT(1)
  39 #define PM_CAM1_CTRLEN                  BIT(0)
  40
  41 #define PM_CCP2TX                       0x4c
  42 #define PM_CCP2TX_LDOEN                 BIT(1)
  43 #define PM_CCP2TX_CTRLEN                BIT(0)
  44
  45 #define PM_DSI0                         0x50
  46 #define PM_DSI0_LDOHPEN                 BIT(2)
  47 #define PM_DSI0_LDOLPEN                 BIT(1)
  48 #define PM_DSI0_CTRLEN                  BIT(0)
  49
  50 #define PM_DSI1                         0x54
  51 #define PM_DSI1_LDOHPEN                 BIT(2)
  52 #define PM_DSI1_LDOLPEN                 BIT(1)
  53 #define PM_DSI1_CTRLEN                  BIT(0)
  54
  55 #define PM_HDMI                         0x58
  56 #define PM_HDMI_RSTDR                   BIT(19)
  57 #define PM_HDMI_LDOPD                   BIT(1)
  58 #define PM_HDMI_CTRLEN                  BIT(0)
  59
  60 #define PM_USB                          0x5c
  61 /* The power gates must be enabled with this bit before enabling the LDO in the
  62  * USB block.
  63  */
  64 #define PM_USB_CTRLEN                   BIT(0)
  65
  66 #define PM_PXLDO                        0x60
  67 #define PM_PXBG                         0x64
  68 #define PM_DFT                          0x68
  69 #define PM_SMPS                         0x6c
  70 #define PM_XOSC                         0x70
  71 #define PM_SPAREW                       0x74
  72 #define PM_SPARER                       0x78
  73 #define PM_AVS_RSTDR                    0x7c
  74 #define PM_AVS_STAT                     0x80
  75 #define PM_AVS_EVENT                    0x84
  76 #define PM_AVS_INTEN                    0x88
  77 #define PM_DUMMY                        0xfc
  78
  79 #define PM_IMAGE                        0x108
  80 #define PM_GRAFX                        0x10c
  81 #define PM_PROC                         0x110
  82 #define PM_ENAB                         BIT(12)
  83 #define PM_ISPRSTN                      BIT(8)
  84 #define PM_H264RSTN                     BIT(7)
  85 #define PM_PERIRSTN                     BIT(6)
  86 #define PM_V3DRSTN                      BIT(6)
  87 #define PM_ISFUNC                       BIT(5)
  88 #define PM_MRDONE                       BIT(4)
  89 #define PM_MEMREP                       BIT(3)
  90 #define PM_ISPOW                        BIT(2)
  91 #define PM_POWOK                        BIT(1)
  92 #define PM_POWUP                        BIT(0)
  93 #define PM_INRUSH_SHIFT                 13
  94 #define PM_INRUSH_3_5_MA                0
  95 #define PM_INRUSH_5_MA                  1
  96 #define PM_INRUSH_10_MA                 2
  97 #define PM_INRUSH_20_MA                 3
  98 #define PM_INRUSH_MASK                  (3 << PM_INRUSH_SHIFT)
  99
 100 #define PM_PASSWORD                     0x5a000000
 101
 102 #define PM_WDOG_TIME_SET                0x000fffff
 103 #define PM_RSTC_WRCFG_CLR               0xffffffcf
 104 #define PM_RSTS_HADWRH_SET              0x00000040
 105 #define PM_RSTC_WRCFG_SET               0x00000030
 106 #define PM_RSTC_WRCFG_FULL_RESET        0x00000020
 107 #define PM_RSTC_RESET                   0x00000102
 108
 109 #define PM_READ(reg) readl(power->base + (reg))
 110 #define PM_WRITE(reg, val) writel(PM_PASSWORD | (val), power->base + (reg))
 111
 112 #define ASB_BRDG_VERSION                0x00
 113 #define ASB_CPR_CTRL                    0x04
 114
 115 #define ASB_V3D_S_CTRL                  0x08
 116 #define ASB_V3D_M_CTRL                  0x0c
 117 #define ASB_ISP_S_CTRL                  0x10
 118 #define ASB_ISP_M_CTRL                  0x14
 119 #define ASB_H264_S_CTRL                 0x18
 120 #define ASB_H264_M_CTRL                 0x1c
 121
 122 #define ASB_REQ_STOP                    BIT(0)
 123 #define ASB_ACK                         BIT(1)
 124 #define ASB_EMPTY                       BIT(2)
 125 #define ASB_FULL                        BIT(3)
 126
 127 #define ASB_AXI_BRDG_ID                 0x20
 128
 129 #define ASB_READ(reg) readl(power->asb + (reg))
 130 #define ASB_WRITE(reg, val) writel(PM_PASSWORD | (val), power->asb + (reg))
 131
 132 struct bcm2835_power_domain {
 133         struct generic_pm_domain base;
 134         struct bcm2835_power *power;
 135         u32 domain;
 136         struct clk *clk;
 137 };
 138
 139 struct bcm2835_power {
 140         struct device           *dev;
 141         /* PM registers. */
 142         void __iomem            *base;
 143         /* AXI Async bridge registers. */
 144         void __iomem            *asb;
 145
 146         bool is_2711;
 147
 148         struct genpd_onecell_data pd_xlate;
 149         struct bcm2835_power_domain domains[BCM2835_POWER_DOMAIN_COUNT];
 150         struct reset_controller_dev reset;
 151 };
 152
 153 static int bcm2835_asb_enable(struct bcm2835_power *power, u32 reg)
 154 {
 155         u64 start;
 156
 157         if (!reg)
 158                 return 0;
 159
 160         start = ktime_get_ns();
 161
 162         /* Enable the module's async AXI bridges. */
 163         ASB_WRITE(reg, ASB_READ(reg) & ~ASB_REQ_STOP);
 164         while (ASB_READ(reg) & ASB_ACK) {
 165                 cpu_relax();
 166                 if (ktime_get_ns() - start >= 1000)
 167                         return -ETIMEDOUT;
 168         }
 169
 170         return 0;
 171 }
 172
 173 static int bcm2835_asb_disable(struct bcm2835_power *power, u32 reg)
 174 {
 175         u64 start;
 176
 177         if (!reg)
 178                 return 0;
 179
 180         start = ktime_get_ns();
 181
 182         /* Enable the module's async AXI bridges. */
 183         ASB_WRITE(reg, ASB_READ(reg) | ASB_REQ_STOP);
 184         while (!(ASB_READ(reg) & ASB_ACK)) {
 185                 cpu_relax();
 186                 if (ktime_get_ns() - start >= 1000)
 187                         return -ETIMEDOUT;
 188         }
 189
 190         return 0;
 191 }
 192
 193 static int bcm2835_power_power_off(struct bcm2835_power_domain *pd, u32 pm_reg)
 194 {
 195         struct bcm2835_power *power = pd->power;
 196
 197         /* 2711 has no power domains above the reset controller. */
 198         if (power->is_2711)
 199                 return 0;
 200
 201         /* Enable functional isolation */
 202         PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_ISFUNC);
 203
 204         /* Enable electrical isolation */
 205         PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_ISPOW);
 206
 207         /* Open the power switches. */
 208         PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_POWUP);
 209
 210         return 0;
 211 }
 212
 213 static int bcm2835_power_power_on(struct bcm2835_power_domain *pd, u32 pm_reg)
 214 {
 215         struct bcm2835_power *power = pd->power;
 216         struct device *dev = power->dev;
 217         u64 start;
 218         int ret;
 219         int inrush;
 220         bool powok;
 221
 222         /* 2711 has no power domains above the reset controller. */
 223         if (power->is_2711)
 224                 return 0;
 225
 226         /* If it was already powered on by the fw, leave it that way. */
 227         if (PM_READ(pm_reg) & PM_POWUP)
 228                 return 0;
 229
 230         /* Enable power.  Allowing too much current at once may result
 231          * in POWOK never getting set, so start low and ramp it up as
 232          * necessary to succeed.
 233          */
 234         powok = false;
 235         for (inrush = PM_INRUSH_3_5_MA; inrush <= PM_INRUSH_20_MA; inrush++) {
 236                 PM_WRITE(pm_reg,
 237                          (PM_READ(pm_reg) & ~PM_INRUSH_MASK) |
 238                          (inrush << PM_INRUSH_SHIFT) |
 239                          PM_POWUP);
 240
 241                 start = ktime_get_ns();
 242                 while (!(powok = !!(PM_READ(pm_reg) & PM_POWOK))) {
 243                         cpu_relax();
 244                         if (ktime_get_ns() - start >= 3000)
 245                                 break;
 246                 }
 247         }
 248         if (!powok) {
 249                 dev_err(dev, "Timeout waiting for %s power OK\n",
 250                         pd->base.name);
 251                 ret = -ETIMEDOUT;
 252                 goto err_disable_powup;
 253         }
 254
 255         /* Disable electrical isolation */
 256         PM_WRITE(pm_reg, PM_READ(pm_reg) | PM_ISPOW);
 257
 258         /* Repair memory */
 259         PM_WRITE(pm_reg, PM_READ(pm_reg) | PM_MEMREP);
 260         start = ktime_get_ns();
 261         while (!(PM_READ(pm_reg) & PM_MRDONE)) {
 262                 cpu_relax();
 263                 if (ktime_get_ns() - start >= 1000) {
 264                         dev_err(dev, "Timeout waiting for %s memory repair\n",
 265                                 pd->base.name);
 266                         ret = -ETIMEDOUT;
 267                         goto err_disable_ispow;
 268                 }
 269         }
 270
 271         /* Disable functional isolation */
 272         PM_WRITE(pm_reg, PM_READ(pm_reg) | PM_ISFUNC);
 273
 274         return 0;
 275
 276 err_disable_ispow:
 277         PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_ISPOW);
 278 err_disable_powup:
 279         PM_WRITE(pm_reg, PM_READ(pm_reg) & ~(PM_POWUP | PM_INRUSH_MASK));
 280         return ret;
 281 }
 282
 283 static int bcm2835_asb_power_on(struct bcm2835_power_domain *pd,
 284                                 u32 pm_reg,
 285                                 u32 asb_m_reg,
 286                                 u32 asb_s_reg,
 287                                 u32 reset_flags)
 288 {
 289         struct bcm2835_power *power = pd->power;
 290         int ret;
 291
 292         ret = clk_prepare_enable(pd->clk);
 293         if (ret) {
 294                 dev_err(power->dev, "Failed to enable clock for %s\n",
 295                         pd->base.name);
 296                 return ret;
 297         }
 298
 299         /* Wait 32 clocks for reset to propagate, 1 us will be enough */
 300         udelay(1);
 301
 302         clk_disable_unprepare(pd->clk);
 303
 304         /* Deassert the resets. */
 305         PM_WRITE(pm_reg, PM_READ(pm_reg) | reset_flags);
 306
 307         ret = clk_prepare_enable(pd->clk);
 308         if (ret) {
 309                 dev_err(power->dev, "Failed to enable clock for %s\n",
 310                         pd->base.name);
 311                 goto err_enable_resets;
 312         }
 313
 314         ret = bcm2835_asb_enable(power, asb_m_reg);
 315         if (ret) {
 316                 dev_err(power->dev, "Failed to enable ASB master for %s\n",
 317                         pd->base.name);
 318                 goto err_disable_clk;
 319         }
 320         ret = bcm2835_asb_enable(power, asb_s_reg);
 321         if (ret) {
 322                 dev_err(power->dev, "Failed to enable ASB slave for %s\n",
 323                         pd->base.name);
 324                 goto err_disable_asb_master;
 325         }
 326
 327         return 0;
 328
 329 err_disable_asb_master:
 330         bcm2835_asb_disable(power, asb_m_reg);
 331 err_disable_clk:
 332         clk_disable_unprepare(pd->clk);
 333 err_enable_resets:
 334         PM_WRITE(pm_reg, PM_READ(pm_reg) & ~reset_flags);
 335         return ret;
 336 }
 337
 338 static int bcm2835_asb_power_off(struct bcm2835_power_domain *pd,
 339                                  u32 pm_reg,
 340                                  u32 asb_m_reg,
 341                                  u32 asb_s_reg,
 342                                  u32 reset_flags)
 343 {
 344         struct bcm2835_power *power = pd->power;
 345         int ret;
 346
 347         ret = bcm2835_asb_disable(power, asb_s_reg);
 348         if (ret) {
 349                 dev_warn(power->dev, "Failed to disable ASB slave for %s\n",
 350                          pd->base.name);
 351                 return ret;
 352         }
 353         ret = bcm2835_asb_disable(power, asb_m_reg);
 354         if (ret) {
 355                 dev_warn(power->dev, "Failed to disable ASB master for %s\n",
 356                          pd->base.name);
 357                 bcm2835_asb_enable(power, asb_s_reg);
 358                 return ret;
 359         }
 360
 361         clk_disable_unprepare(pd->clk);
 362
 363         /* Assert the resets. */
 364         PM_WRITE(pm_reg, PM_READ(pm_reg) & ~reset_flags);
 365
 366         return 0;
 367 }
 368
 369 static int bcm2835_power_pd_power_on(struct generic_pm_domain *domain)
 370 {
 371         struct bcm2835_power_domain *pd =
 372                 container_of(domain, struct bcm2835_power_domain, base);
 373         struct bcm2835_power *power = pd->power;
 374
 375         switch (pd->domain) {
 376         case BCM2835_POWER_DOMAIN_GRAFX:
 377                 return bcm2835_power_power_on(pd, PM_GRAFX);
 378
 379         case BCM2835_POWER_DOMAIN_GRAFX_V3D:
 380                 return bcm2835_asb_power_on(pd, PM_GRAFX,
 381                                             ASB_V3D_M_CTRL, ASB_V3D_S_CTRL,
 382                                             PM_V3DRSTN);
 383
 384         case BCM2835_POWER_DOMAIN_IMAGE:
 385                 return bcm2835_power_power_on(pd, PM_IMAGE);
 386
 387         case BCM2835_POWER_DOMAIN_IMAGE_PERI:
 388                 return bcm2835_asb_power_on(pd, PM_IMAGE,
 389                                             0, 0,
 390                                             PM_PERIRSTN);
 391
 392         case BCM2835_POWER_DOMAIN_IMAGE_ISP:
 393                 return bcm2835_asb_power_on(pd, PM_IMAGE,
 394                                             ASB_ISP_M_CTRL, ASB_ISP_S_CTRL,
 395                                             PM_ISPRSTN);
 396
 397         case BCM2835_POWER_DOMAIN_IMAGE_H264:
 398                 return bcm2835_asb_power_on(pd, PM_IMAGE,
 399                                             ASB_H264_M_CTRL, ASB_H264_S_CTRL,
 400                                             PM_H264RSTN);
 401
 402         case BCM2835_POWER_DOMAIN_USB:
 403                 PM_WRITE(PM_USB, PM_USB_CTRLEN);
 404                 return 0;
 405
 406         case BCM2835_POWER_DOMAIN_DSI0:
 407                 PM_WRITE(PM_DSI0, PM_DSI0_CTRLEN);
 408                 PM_WRITE(PM_DSI0, PM_DSI0_CTRLEN | PM_DSI0_LDOHPEN);
 409                 return 0;
 410
 411         case BCM2835_POWER_DOMAIN_DSI1:
 412                 PM_WRITE(PM_DSI1, PM_DSI1_CTRLEN);
 413                 PM_WRITE(PM_DSI1, PM_DSI1_CTRLEN | PM_DSI1_LDOHPEN);
 414                 return 0;
 415
 416         case BCM2835_POWER_DOMAIN_CCP2TX:
 417                 PM_WRITE(PM_CCP2TX, PM_CCP2TX_CTRLEN);
 418                 PM_WRITE(PM_CCP2TX, PM_CCP2TX_CTRLEN | PM_CCP2TX_LDOEN);
 419                 return 0;
 420
 421         case BCM2835_POWER_DOMAIN_HDMI:
 422                 PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) | PM_HDMI_RSTDR);
 423                 PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) | PM_HDMI_CTRLEN);
 424                 PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) & ~PM_HDMI_LDOPD);
 425                 usleep_range(100, 200);
 426                 PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) & ~PM_HDMI_RSTDR);
 427                 return 0;
 428
 429         default:
 430                 dev_err(power->dev, "Invalid domain %d\n", pd->domain);
 431                 return -EINVAL;
 432         }
 433 }
 434
 435 static int bcm2835_power_pd_power_off(struct generic_pm_domain *domain)
 436 {
 437         struct bcm2835_power_domain *pd =
 438                 container_of(domain, struct bcm2835_power_domain, base);
 439         struct bcm2835_power *power = pd->power;
 440
 441         switch (pd->domain) {
 442         case BCM2835_POWER_DOMAIN_GRAFX:
 443                 return bcm2835_power_power_off(pd, PM_GRAFX);
 444
 445         case BCM2835_POWER_DOMAIN_GRAFX_V3D:
 446                 return bcm2835_asb_power_off(pd, PM_GRAFX,
 447                                              ASB_V3D_M_CTRL, ASB_V3D_S_CTRL,
 448                                              PM_V3DRSTN);
 449
 450         case BCM2835_POWER_DOMAIN_IMAGE:
 451                 return bcm2835_power_power_off(pd, PM_IMAGE);
 452
 453         case BCM2835_POWER_DOMAIN_IMAGE_PERI:
 454                 return bcm2835_asb_power_off(pd, PM_IMAGE,
 455                                              0, 0,
 456                                              PM_PERIRSTN);
 457
 458         case BCM2835_POWER_DOMAIN_IMAGE_ISP:
 459                 return bcm2835_asb_power_off(pd, PM_IMAGE,
 460                                              ASB_ISP_M_CTRL, ASB_ISP_S_CTRL,
 461                                              PM_ISPRSTN);
 462
 463         case BCM2835_POWER_DOMAIN_IMAGE_H264:
 464                 return bcm2835_asb_power_off(pd, PM_IMAGE,
 465                                              ASB_H264_M_CTRL, ASB_H264_S_CTRL,
 466                                              PM_H264RSTN);
 467
 468         case BCM2835_POWER_DOMAIN_USB:
 469                 PM_WRITE(PM_USB, 0);
 470                 return 0;
 471
 472         case BCM2835_POWER_DOMAIN_DSI0:
 473                 PM_WRITE(PM_DSI0, PM_DSI0_CTRLEN);
 474                 PM_WRITE(PM_DSI0, 0);
 475                 return 0;
 476
 477         case BCM2835_POWER_DOMAIN_DSI1:
 478                 PM_WRITE(PM_DSI1, PM_DSI1_CTRLEN);
 479                 PM_WRITE(PM_DSI1, 0);
 480                 return 0;
 481
 482         case BCM2835_POWER_DOMAIN_CCP2TX:
 483                 PM_WRITE(PM_CCP2TX, PM_CCP2TX_CTRLEN);
 484                 PM_WRITE(PM_CCP2TX, 0);
 485                 return 0;
 486
 487         case BCM2835_POWER_DOMAIN_HDMI:
 488                 PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) | PM_HDMI_LDOPD);
 489                 PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) & ~PM_HDMI_CTRLEN);
 490                 return 0;
 491
 492         default:
 493                 dev_err(power->dev, "Invalid domain %d\n", pd->domain);
 494                 return -EINVAL;
 495         }
 496 }
 497
 498 static int
 499 bcm2835_init_power_domain(struct bcm2835_power *power,
 500                           int pd_xlate_index, const char *name)
 501 {
 502         struct device *dev = power->dev;
 503         struct bcm2835_power_domain *dom = &power->domains[pd_xlate_index];
 504
 505         dom->clk = devm_clk_get(dev->parent, name);
 506         if (IS_ERR(dom->clk)) {
 507                 int ret = PTR_ERR(dom->clk);
 508
 509                 if (ret == -EPROBE_DEFER)
 510                         return ret;
 511
 512                 /* Some domains don't have a clk, so make sure that we
 513                  * don't deref an error pointer later.
 514                  */
 515                 dom->clk = NULL;
 516         }
 517
 518         dom->base.name = name;
 519         dom->base.power_on = bcm2835_power_pd_power_on;
 520         dom->base.power_off = bcm2835_power_pd_power_off;
 521
 522         dom->domain = pd_xlate_index;
 523         dom->power = power;
 524
 525         /* XXX: on/off at boot? */
 526         pm_genpd_init(&dom->base, NULL, true);
 527
 528         power->pd_xlate.domains[pd_xlate_index] = &dom->base;
 529
 530         return 0;
 531 }
 532
 533 /** bcm2835_reset_reset - Resets a block that has a reset line in the
 534  * PM block.
 535  *
 536  * The consumer of the reset controller must have the power domain up
 537  * -- there's no reset ability with the power domain down.  To reset
 538  * the sub-block, we just disable its access to memory through the
 539  * ASB, reset, and re-enable.
 540  */
 541 static int bcm2835_reset_reset(struct reset_controller_dev *rcdev,
 542                                unsigned long id)
 543 {
 544         struct bcm2835_power *power = container_of(rcdev, struct bcm2835_power,
 545                                                    reset);
 546         struct bcm2835_power_domain *pd;
 547         int ret;
 548
 549         switch (id) {
 550         case BCM2835_RESET_V3D:
 551                 pd = &power->domains[BCM2835_POWER_DOMAIN_GRAFX_V3D];
 552                 break;
 553         case BCM2835_RESET_H264:
 554                 pd = &power->domains[BCM2835_POWER_DOMAIN_IMAGE_H264];
 555                 break;
 556         case BCM2835_RESET_ISP:
 557                 pd = &power->domains[BCM2835_POWER_DOMAIN_IMAGE_ISP];
 558                 break;
 559         default:
 560                 dev_err(power->dev, "Bad reset id %ld\n", id);
 561                 return -EINVAL;
 562         }
 563
 564         ret = bcm2835_power_pd_power_off(&pd->base);
 565         if (ret)
 566                 return ret;
 567
 568         return bcm2835_power_pd_power_on(&pd->base);
 569 }
 570
 571 static int bcm2835_reset_status(struct reset_controller_dev *rcdev,
 572                                 unsigned long id)
 573 {
 574         struct bcm2835_power *power = container_of(rcdev, struct bcm2835_power,
 575                                                    reset);
 576
 577         switch (id) {
 578         case BCM2835_RESET_V3D:
 579                 return !PM_READ(PM_GRAFX & PM_V3DRSTN);
 580         case BCM2835_RESET_H264:
 581                 return !PM_READ(PM_IMAGE & PM_H264RSTN);
 582         case BCM2835_RESET_ISP:
 583                 return !PM_READ(PM_IMAGE & PM_ISPRSTN);
 584         default:
 585                 return -EINVAL;
 586         }
 587 }
 588
 589 static const struct reset_control_ops bcm2835_reset_ops = {
 590         .reset = bcm2835_reset_reset,
 591         .status = bcm2835_reset_status,
 592 };
 593
 594 static const char *const power_domain_names[] = {
 595         [BCM2835_POWER_DOMAIN_GRAFX] = "grafx",
 596         [BCM2835_POWER_DOMAIN_GRAFX_V3D] = "v3d",
 597
 598         [BCM2835_POWER_DOMAIN_IMAGE] = "image",
 599         [BCM2835_POWER_DOMAIN_IMAGE_PERI] = "peri_image",
 600         [BCM2835_POWER_DOMAIN_IMAGE_H264] = "h264",
 601         [BCM2835_POWER_DOMAIN_IMAGE_ISP] = "isp",
 602
 603         [BCM2835_POWER_DOMAIN_USB] = "usb",
 604         [BCM2835_POWER_DOMAIN_DSI0] = "dsi0",
 605         [BCM2835_POWER_DOMAIN_DSI1] = "dsi1",
 606         [BCM2835_POWER_DOMAIN_CAM0] = "cam0",
 607         [BCM2835_POWER_DOMAIN_CAM1] = "cam1",
 608         [BCM2835_POWER_DOMAIN_CCP2TX] = "ccp2tx",
 609         [BCM2835_POWER_DOMAIN_HDMI] = "hdmi",
 610 };
 611
 612 static int bcm2835_power_probe(struct platform_device *pdev)
 613 {
 614         struct bcm2835_pm *pm = dev_get_drvdata(pdev->dev.parent);
 615         struct device *dev = &pdev->dev;
 616         struct bcm2835_power *power;
 617         static const struct {
 618                 int parent, child;
 619         } domain_deps[] = {
 620                 { BCM2835_POWER_DOMAIN_GRAFX, BCM2835_POWER_DOMAIN_GRAFX_V3D },
 621                 { BCM2835_POWER_DOMAIN_IMAGE, BCM2835_POWER_DOMAIN_IMAGE_PERI },
 622                 { BCM2835_POWER_DOMAIN_IMAGE, BCM2835_POWER_DOMAIN_IMAGE_H264 },
 623                 { BCM2835_POWER_DOMAIN_IMAGE, BCM2835_POWER_DOMAIN_IMAGE_ISP },
 624                 { BCM2835_POWER_DOMAIN_IMAGE_PERI, BCM2835_POWER_DOMAIN_USB },
 625                 { BCM2835_POWER_DOMAIN_IMAGE_PERI, BCM2835_POWER_DOMAIN_CAM0 },
 626                 { BCM2835_POWER_DOMAIN_IMAGE_PERI, BCM2835_POWER_DOMAIN_CAM1 },
 627         };
 628         int ret = 0, i;
 629         u32 id;
 630
 631         power = devm_kzalloc(dev, sizeof(*power), GFP_KERNEL);
 632         if (!power)
 633                 return -ENOMEM;
 634         platform_set_drvdata(pdev, power);
 635
 636         power->dev = dev;
 637         power->base = pm->base;
 638         power->asb = pm->asb;
 639
 640         /* 2711 hack: the new ARGON ASB took over V3D, which is our
 641          * only consumer of this driver so far.  The old ASB seems to
 642          * still be present with ISP and H264 bits but no V3D, but I
 643          * don't know if that's real or not.  The V3D is in the same
 644          * place in the new ASB as the old one, so just poke the new
 645          * one for now.
 646          */
 647         if (pm->arg_asb) {
 648                 power->asb = pm->arg_asb;
 649                 power->is_2711 = true;
 650         }
 651
 652         id = ASB_READ(ASB_AXI_BRDG_ID);
 653         if (id != 0x62726467 /* "BRDG" */) {
 654                 dev_err(dev, "ASB register ID returned 0x%08x\n", id);
 655                 return -ENODEV;
 656         }
 657
 658         power->pd_xlate.domains = devm_kcalloc(dev,
 659                                                ARRAY_SIZE(power_domain_names),
 660                                                sizeof(*power->pd_xlate.domains),
 661                                                GFP_KERNEL);
 662         if (!power->pd_xlate.domains)
 663                 return -ENOMEM;
 664
 665         power->pd_xlate.num_domains = ARRAY_SIZE(power_domain_names);
 666
 667         for (i = 0; i < ARRAY_SIZE(power_domain_names); i++) {
 668                 ret = bcm2835_init_power_domain(power, i, power_domain_names[i]);
 669                 if (ret)
 670                         goto fail;
 671         }
 672
 673         for (i = 0; i < ARRAY_SIZE(domain_deps); i++) {
 674                 pm_genpd_add_subdomain(&power->domains[domain_deps[i].parent].base,
 675                                        &power->domains[domain_deps[i].child].base);
 676         }
 677
 678         power->reset.owner = THIS_MODULE;
 679         power->reset.nr_resets = BCM2835_RESET_COUNT;
 680         power->reset.ops = &bcm2835_reset_ops;
 681         power->reset.of_node = dev->parent->of_node;
 682
 683         ret = devm_reset_controller_register(dev, &power->reset);
 684         if (ret)
 685                 goto fail;
 686
 687         of_genpd_add_provider_onecell(dev->parent->of_node, &power->pd_xlate);
 688
 689         dev_info(dev, "Broadcom BCM2835 power domains driver");
 690         return 0;
 691
 692 fail:
 693         for (i = 0; i < ARRAY_SIZE(power_domain_names); i++) {
 694                 struct generic_pm_domain *dom = &power->domains[i].base;
 695
 696                 if (dom->name)
 697                         pm_genpd_remove(dom);
 698         }
 699         return ret;
 700 }
 701
 702 static int bcm2835_power_remove(struct platform_device *pdev)
 703 {
 704         return 0;
 705 }
 706
 707 static struct platform_driver bcm2835_power_driver = {
 708         .probe          = bcm2835_power_probe,
 709         .remove         = bcm2835_power_remove,
 710         .driver = {
 711                 .name = "bcm2835-power",
 712         },
 713 };
 714 module_platform_driver(bcm2835_power_driver);
 715
 716 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
 717 MODULE_DESCRIPTION("Driver for Broadcom BCM2835 PM power domains and reset");
 718 MODULE_LICENSE("GPL");