drivers/soc/bcm/bcm2835-power.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Power domain driver for Broadcom BCM2835
   4  *
   5  * Copyright (C) 2018 Broadcom
   6  */
   7
   8 #include <dt-bindings/soc/bcm2835-pm.h>
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/io.h>
  12 #include <linux/mfd/bcm2835-pm.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_domain.h>
  16 #include <linux/reset-controller.h>
  17 #include <linux/types.h>
  18
  19 #define PM_GNRIC                        0x00
  20 #define PM_AUDIO                        0x04
  21 #define PM_STATUS                       0x18
  22 #define PM_RSTC                         0x1c
  23 #define PM_RSTS                         0x20
  24 #define PM_WDOG                         0x24
  25 #define PM_PADS0                        0x28
  26 #define PM_PADS2                        0x2c
  27 #define PM_PADS3                        0x30
  28 #define PM_PADS4                        0x34
  29 #define PM_PADS5                        0x38
  30 #define PM_PADS6                        0x3c
  31 #define PM_CAM0                         0x44
  32 #define PM_CAM0_LDOHPEN                 BIT(2)
  33 #define PM_CAM0_LDOLPEN                 BIT(1)
  34 #define PM_CAM0_CTRLEN                  BIT(0)
  35
  36 #define PM_CAM1                         0x48
  37 #define PM_CAM1_LDOHPEN                 BIT(2)
  38 #define PM_CAM1_LDOLPEN                 BIT(1)
  39 #define PM_CAM1_CTRLEN                  BIT(0)
  40
  41 #define PM_CCP2TX                       0x4c
  42 #define PM_CCP2TX_LDOEN                 BIT(1)
  43 #define PM_CCP2TX_CTRLEN                BIT(0)
  44
  45 #define PM_DSI0                         0x50
  46 #define PM_DSI0_LDOHPEN                 BIT(2)
  47 #define PM_DSI0_LDOLPEN                 BIT(1)
  48 #define PM_DSI0_CTRLEN                  BIT(0)
  49
  50 #define PM_DSI1                         0x54
  51 #define PM_DSI1_LDOHPEN                 BIT(2)
  52 #define PM_DSI1_LDOLPEN                 BIT(1)
  53 #define PM_DSI1_CTRLEN                  BIT(0)
  54
  55 #define PM_HDMI                         0x58
  56 #define PM_HDMI_RSTDR                   BIT(19)
  57 #define PM_HDMI_LDOPD                   BIT(1)
  58 #define PM_HDMI_CTRLEN                  BIT(0)
  59
  60 #define PM_USB                          0x5c
  61 /* The power gates must be enabled with this bit before enabling the LDO in the
  62  * USB block.
  63  */
  64 #define PM_USB_CTRLEN                   BIT(0)
  65
  66 #define PM_PXLDO                        0x60
  67 #define PM_PXBG                         0x64
  68 #define PM_DFT                          0x68
  69 #define PM_SMPS                         0x6c
  70 #define PM_XOSC                         0x70
  71 #define PM_SPAREW                       0x74
  72 #define PM_SPARER                       0x78
  73 #define PM_AVS_RSTDR                    0x7c
  74 #define PM_AVS_STAT                     0x80
  75 #define PM_AVS_EVENT                    0x84
  76 #define PM_AVS_INTEN                    0x88
  77 #define PM_DUMMY                        0xfc
  78
  79 #define PM_IMAGE                        0x108
  80 #define PM_GRAFX                        0x10c
  81 #define PM_PROC                         0x110
  82 #define PM_ENAB                         BIT(12)
  83 #define PM_ISPRSTN                      BIT(8)
  84 #define PM_H264RSTN                     BIT(7)
  85 #define PM_PERIRSTN                     BIT(6)
  86 #define PM_V3DRSTN                      BIT(6)
  87 #define PM_ISFUNC                       BIT(5)
  88 #define PM_MRDONE                       BIT(4)
  89 #define PM_MEMREP                       BIT(3)
  90 #define PM_ISPOW                        BIT(2)
  91 #define PM_POWOK                        BIT(1)
  92 #define PM_POWUP                        BIT(0)
  93 #define PM_INRUSH_SHIFT                 13
  94 #define PM_INRUSH_3_5_MA                0
  95 #define PM_INRUSH_5_MA                  1
  96 #define PM_INRUSH_10_MA                 2
  97 #define PM_INRUSH_20_MA                 3
  98 #define PM_INRUSH_MASK                  (3 << PM_INRUSH_SHIFT)
  99
 100 #define PM_PASSWORD                     0x5a000000
 101
 102 #define PM_WDOG_TIME_SET                0x000fffff
 103 #define PM_RSTC_WRCFG_CLR               0xffffffcf
 104 #define PM_RSTS_HADWRH_SET              0x00000040
 105 #define PM_RSTC_WRCFG_SET               0x00000030
 106 #define PM_RSTC_WRCFG_FULL_RESET        0x00000020
 107 #define PM_RSTC_RESET                   0x00000102
 108
 109 #define PM_READ(reg) readl(power->base + (reg))
 110 #define PM_WRITE(reg, val) writel(PM_PASSWORD | (val), power->base + (reg))
 111
 112 #define ASB_BRDG_VERSION                0x00
 113 #define ASB_CPR_CTRL                    0x04
 114
 115 #define ASB_V3D_S_CTRL                  0x08
 116 #define ASB_V3D_M_CTRL                  0x0c
 117 #define ASB_ISP_S_CTRL                  0x10
 118 #define ASB_ISP_M_CTRL                  0x14
 119 #define ASB_H264_S_CTRL                 0x18
 120 #define ASB_H264_M_CTRL                 0x1c
 121
 122 #define ASB_REQ_STOP                    BIT(0)
 123 #define ASB_ACK                         BIT(1)
 124 #define ASB_EMPTY                       BIT(2)
 125 #define ASB_FULL                        BIT(3)
 126
 127 #define ASB_AXI_BRDG_ID                 0x20
 128
 129 #define ASB_READ(reg) readl(power->asb + (reg))
 130 #define ASB_WRITE(reg, val) writel(PM_PASSWORD | (val), power->asb + (reg))
 131
 132 struct bcm2835_power_domain {
 133         struct generic_pm_domain base;
 134         struct bcm2835_power *power;
 135         u32 domain;
 136         struct clk *clk;
 137 };
 138
 139 struct bcm2835_power {
 140         struct device           *dev;
 141         /* PM registers. */
 142         void __iomem            *base;
 143         /* AXI Async bridge registers. */
 144         void __iomem            *asb;
 145
 146         struct genpd_onecell_data pd_xlate;
 147         struct bcm2835_power_domain domains[BCM2835_POWER_DOMAIN_COUNT];
 148         struct reset_controller_dev reset;
 149 };
 150
 151 static int bcm2835_asb_control(struct bcm2835_power *power, u32 reg, bool enable)
 152 {
 153         u64 start;
 154
 155         if (!reg)
 156                 return 0;
 157
 158         start = ktime_get_ns();
 159
 160         /* Enable the module's async AXI bridges. */
 161         if (enable) {
 162                 ASB_WRITE(reg, ASB_READ(reg) & ~ASB_REQ_STOP);
 163         } else {
 164                 ASB_WRITE(reg, ASB_READ(reg) | ASB_REQ_STOP);
 165         }
 166
 167         while (ASB_READ(reg) & ASB_ACK) {
 168                 cpu_relax();
 169                 if (ktime_get_ns() - start >= 1000)
 170                         return -ETIMEDOUT;
 171         }
 172
 173         return 0;
 174 }
 175
 176 static int bcm2835_asb_enable(struct bcm2835_power *power, u32 reg)
 177 {
 178         return bcm2835_asb_control(power, reg, true);
 179 }
 180
 181 static int bcm2835_asb_disable(struct bcm2835_power *power, u32 reg)
 182 {
 183         return bcm2835_asb_control(power, reg, false);
 184 }
 185
 186 static int bcm2835_power_power_off(struct bcm2835_power_domain *pd, u32 pm_reg)
 187 {
 188         struct bcm2835_power *power = pd->power;
 189
 190         /* Enable functional isolation */
 191         PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_ISFUNC);
 192
 193         /* Enable electrical isolation */
 194         PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_ISPOW);
 195
 196         /* Open the power switches. */
 197         PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_POWUP);
 198
 199         return 0;
 200 }
 201
 202 static int bcm2835_power_power_on(struct bcm2835_power_domain *pd, u32 pm_reg)
 203 {
 204         struct bcm2835_power *power = pd->power;
 205         struct device *dev = power->dev;
 206         u64 start;
 207         int ret;
 208         int inrush;
 209         bool powok;
 210
 211         /* If it was already powered on by the fw, leave it that way. */
 212         if (PM_READ(pm_reg) & PM_POWUP)
 213                 return 0;
 214
 215         /* Enable power.  Allowing too much current at once may result
 216          * in POWOK never getting set, so start low and ramp it up as
 217          * necessary to succeed.
 218          */
 219         powok = false;
 220         for (inrush = PM_INRUSH_3_5_MA; inrush <= PM_INRUSH_20_MA; inrush++) {
 221                 PM_WRITE(pm_reg,
 222                          (PM_READ(pm_reg) & ~PM_INRUSH_MASK) |
 223                          (inrush << PM_INRUSH_SHIFT) |
 224                          PM_POWUP);
 225
 226                 start = ktime_get_ns();
 227                 while (!(powok = !!(PM_READ(pm_reg) & PM_POWOK))) {
 228                         cpu_relax();
 229                         if (ktime_get_ns() - start >= 3000)
 230                                 break;
 231                 }
 232         }
 233         if (!powok) {
 234                 dev_err(dev, "Timeout waiting for %s power OK\n",
 235                         pd->base.name);
 236                 ret = -ETIMEDOUT;
 237                 goto err_disable_powup;
 238         }
 239
 240         /* Disable electrical isolation */
 241         PM_WRITE(pm_reg, PM_READ(pm_reg) | PM_ISPOW);
 242
 243         /* Repair memory */
 244         PM_WRITE(pm_reg, PM_READ(pm_reg) | PM_MEMREP);
 245         start = ktime_get_ns();
 246         while (!(PM_READ(pm_reg) & PM_MRDONE)) {
 247                 cpu_relax();
 248                 if (ktime_get_ns() - start >= 1000) {
 249                         dev_err(dev, "Timeout waiting for %s memory repair\n",
 250                                 pd->base.name);
 251                         ret = -ETIMEDOUT;
 252                         goto err_disable_ispow;
 253                 }
 254         }
 255
 256         /* Disable functional isolation */
 257         PM_WRITE(pm_reg, PM_READ(pm_reg) | PM_ISFUNC);
 258
 259         return 0;
 260
 261 err_disable_ispow:
 262         PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_ISPOW);
 263 err_disable_powup:
 264         PM_WRITE(pm_reg, PM_READ(pm_reg) & ~(PM_POWUP | PM_INRUSH_MASK));
 265         return ret;
 266 }
 267
 268 static int bcm2835_asb_power_on(struct bcm2835_power_domain *pd,
 269                                 u32 pm_reg,
 270                                 u32 asb_m_reg,
 271                                 u32 asb_s_reg,
 272                                 u32 reset_flags)
 273 {
 274         struct bcm2835_power *power = pd->power;
 275         int ret;
 276
 277         ret = clk_prepare_enable(pd->clk);
 278         if (ret) {
 279                 dev_err(power->dev, "Failed to enable clock for %s\n",
 280                         pd->base.name);
 281                 return ret;
 282         }
 283
 284         /* Wait 32 clocks for reset to propagate, 1 us will be enough */
 285         udelay(1);
 286
 287         clk_disable_unprepare(pd->clk);
 288
 289         /* Deassert the resets. */
 290         PM_WRITE(pm_reg, PM_READ(pm_reg) | reset_flags);
 291
 292         ret = clk_prepare_enable(pd->clk);
 293         if (ret) {
 294                 dev_err(power->dev, "Failed to enable clock for %s\n",
 295                         pd->base.name);
 296                 goto err_enable_resets;
 297         }
 298
 299         ret = bcm2835_asb_enable(power, asb_m_reg);
 300         if (ret) {
 301                 dev_err(power->dev, "Failed to enable ASB master for %s\n",
 302                         pd->base.name);
 303                 goto err_disable_clk;
 304         }
 305         ret = bcm2835_asb_enable(power, asb_s_reg);
 306         if (ret) {
 307                 dev_err(power->dev, "Failed to enable ASB slave for %s\n",
 308                         pd->base.name);
 309                 goto err_disable_asb_master;
 310         }
 311
 312         return 0;
 313
 314 err_disable_asb_master:
 315         bcm2835_asb_disable(power, asb_m_reg);
 316 err_disable_clk:
 317         clk_disable_unprepare(pd->clk);
 318 err_enable_resets:
 319         PM_WRITE(pm_reg, PM_READ(pm_reg) & ~reset_flags);
 320         return ret;
 321 }
 322
 323 static int bcm2835_asb_power_off(struct bcm2835_power_domain *pd,
 324                                  u32 pm_reg,
 325                                  u32 asb_m_reg,
 326                                  u32 asb_s_reg,
 327                                  u32 reset_flags)
 328 {
 329         struct bcm2835_power *power = pd->power;
 330         int ret;
 331
 332         ret = bcm2835_asb_disable(power, asb_s_reg);
 333         if (ret) {
 334                 dev_warn(power->dev, "Failed to disable ASB slave for %s\n",
 335                          pd->base.name);
 336                 return ret;
 337         }
 338         ret = bcm2835_asb_disable(power, asb_m_reg);
 339         if (ret) {
 340                 dev_warn(power->dev, "Failed to disable ASB master for %s\n",
 341                          pd->base.name);
 342                 bcm2835_asb_enable(power, asb_s_reg);
 343                 return ret;
 344         }
 345
 346         clk_disable_unprepare(pd->clk);
 347
 348         /* Assert the resets. */
 349         PM_WRITE(pm_reg, PM_READ(pm_reg) & ~reset_flags);
 350
 351         return 0;
 352 }
 353
 354 static int bcm2835_power_pd_power_on(struct generic_pm_domain *domain)
 355 {
 356         struct bcm2835_power_domain *pd =
 357                 container_of(domain, struct bcm2835_power_domain, base);
 358         struct bcm2835_power *power = pd->power;
 359
 360         switch (pd->domain) {
 361         case BCM2835_POWER_DOMAIN_GRAFX:
 362                 return bcm2835_power_power_on(pd, PM_GRAFX);
 363
 364         case BCM2835_POWER_DOMAIN_GRAFX_V3D:
 365                 return bcm2835_asb_power_on(pd, PM_GRAFX,
 366                                             ASB_V3D_M_CTRL, ASB_V3D_S_CTRL,
 367                                             PM_V3DRSTN);
 368
 369         case BCM2835_POWER_DOMAIN_IMAGE:
 370                 return bcm2835_power_power_on(pd, PM_IMAGE);
 371
 372         case BCM2835_POWER_DOMAIN_IMAGE_PERI:
 373                 return bcm2835_asb_power_on(pd, PM_IMAGE,
 374                                             0, 0,
 375                                             PM_PERIRSTN);
 376
 377         case BCM2835_POWER_DOMAIN_IMAGE_ISP:
 378                 return bcm2835_asb_power_on(pd, PM_IMAGE,
 379                                             ASB_ISP_M_CTRL, ASB_ISP_S_CTRL,
 380                                             PM_ISPRSTN);
 381
 382         case BCM2835_POWER_DOMAIN_IMAGE_H264:
 383                 return bcm2835_asb_power_on(pd, PM_IMAGE,
 384                                             ASB_H264_M_CTRL, ASB_H264_S_CTRL,
 385                                             PM_H264RSTN);
 386
 387         case BCM2835_POWER_DOMAIN_USB:
 388                 PM_WRITE(PM_USB, PM_USB_CTRLEN);
 389                 return 0;
 390
 391         case BCM2835_POWER_DOMAIN_DSI0:
 392                 PM_WRITE(PM_DSI0, PM_DSI0_CTRLEN);
 393                 PM_WRITE(PM_DSI0, PM_DSI0_CTRLEN | PM_DSI0_LDOHPEN);
 394                 return 0;
 395
 396         case BCM2835_POWER_DOMAIN_DSI1:
 397                 PM_WRITE(PM_DSI1, PM_DSI1_CTRLEN);
 398                 PM_WRITE(PM_DSI1, PM_DSI1_CTRLEN | PM_DSI1_LDOHPEN);
 399                 return 0;
 400
 401         case BCM2835_POWER_DOMAIN_CCP2TX:
 402                 PM_WRITE(PM_CCP2TX, PM_CCP2TX_CTRLEN);
 403                 PM_WRITE(PM_CCP2TX, PM_CCP2TX_CTRLEN | PM_CCP2TX_LDOEN);
 404                 return 0;
 405
 406         case BCM2835_POWER_DOMAIN_HDMI:
 407                 PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) | PM_HDMI_RSTDR);
 408                 PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) | PM_HDMI_CTRLEN);
 409                 PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) & ~PM_HDMI_LDOPD);
 410                 usleep_range(100, 200);
 411                 PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) & ~PM_HDMI_RSTDR);
 412                 return 0;
 413
 414         default:
 415                 dev_err(power->dev, "Invalid domain %d\n", pd->domain);
 416                 return -EINVAL;
 417         }
 418 }
 419
 420 static int bcm2835_power_pd_power_off(struct generic_pm_domain *domain)
 421 {
 422         struct bcm2835_power_domain *pd =
 423                 container_of(domain, struct bcm2835_power_domain, base);
 424         struct bcm2835_power *power = pd->power;
 425
 426         switch (pd->domain) {
 427         case BCM2835_POWER_DOMAIN_GRAFX:
 428                 return bcm2835_power_power_off(pd, PM_GRAFX);
 429
 430         case BCM2835_POWER_DOMAIN_GRAFX_V3D:
 431                 return bcm2835_asb_power_off(pd, PM_GRAFX,
 432                                              ASB_V3D_M_CTRL, ASB_V3D_S_CTRL,
 433                                              PM_V3DRSTN);
 434
 435         case BCM2835_POWER_DOMAIN_IMAGE:
 436                 return bcm2835_power_power_off(pd, PM_IMAGE);
 437
 438         case BCM2835_POWER_DOMAIN_IMAGE_PERI:
 439                 return bcm2835_asb_power_off(pd, PM_IMAGE,
 440                                              0, 0,
 441                                              PM_PERIRSTN);
 442
 443         case BCM2835_POWER_DOMAIN_IMAGE_ISP:
 444                 return bcm2835_asb_power_off(pd, PM_IMAGE,
 445                                              ASB_ISP_M_CTRL, ASB_ISP_S_CTRL,
 446                                              PM_ISPRSTN);
 447
 448         case BCM2835_POWER_DOMAIN_IMAGE_H264:
 449                 return bcm2835_asb_power_off(pd, PM_IMAGE,
 450                                              ASB_H264_M_CTRL, ASB_H264_S_CTRL,
 451                                              PM_H264RSTN);
 452
 453         case BCM2835_POWER_DOMAIN_USB:
 454                 PM_WRITE(PM_USB, 0);
 455                 return 0;
 456
 457         case BCM2835_POWER_DOMAIN_DSI0:
 458                 PM_WRITE(PM_DSI0, PM_DSI0_CTRLEN);
 459                 PM_WRITE(PM_DSI0, 0);
 460                 return 0;
 461
 462         case BCM2835_POWER_DOMAIN_DSI1:
 463                 PM_WRITE(PM_DSI1, PM_DSI1_CTRLEN);
 464                 PM_WRITE(PM_DSI1, 0);
 465                 return 0;
 466
 467         case BCM2835_POWER_DOMAIN_CCP2TX:
 468                 PM_WRITE(PM_CCP2TX, PM_CCP2TX_CTRLEN);
 469                 PM_WRITE(PM_CCP2TX, 0);
 470                 return 0;
 471
 472         case BCM2835_POWER_DOMAIN_HDMI:
 473                 PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) | PM_HDMI_LDOPD);
 474                 PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) & ~PM_HDMI_CTRLEN);
 475                 return 0;
 476
 477         default:
 478                 dev_err(power->dev, "Invalid domain %d\n", pd->domain);
 479                 return -EINVAL;
 480         }
 481 }
 482
 483 static int
 484 bcm2835_init_power_domain(struct bcm2835_power *power,
 485                           int pd_xlate_index, const char *name)
 486 {
 487         struct device *dev = power->dev;
 488         struct bcm2835_power_domain *dom = &power->domains[pd_xlate_index];
 489
 490         dom->clk = devm_clk_get(dev->parent, name);
 491         if (IS_ERR(dom->clk)) {
 492                 int ret = PTR_ERR(dom->clk);
 493
 494                 if (ret == -EPROBE_DEFER)
 495                         return ret;
 496
 497                 /* Some domains don't have a clk, so make sure that we
 498                  * don't deref an error pointer later.
 499                  */
 500                 dom->clk = NULL;
 501         }
 502
 503         dom->base.name = name;
 504         dom->base.power_on = bcm2835_power_pd_power_on;
 505         dom->base.power_off = bcm2835_power_pd_power_off;
 506
 507         dom->domain = pd_xlate_index;
 508         dom->power = power;
 509
 510         /* XXX: on/off at boot? */
 511         pm_genpd_init(&dom->base, NULL, true);
 512
 513         power->pd_xlate.domains[pd_xlate_index] = &dom->base;
 514
 515         return 0;
 516 }
 517
 518 /** bcm2835_reset_reset - Resets a block that has a reset line in the
 519  * PM block.
 520  *
 521  * The consumer of the reset controller must have the power domain up
 522  * -- there's no reset ability with the power domain down.  To reset
 523  * the sub-block, we just disable its access to memory through the
 524  * ASB, reset, and re-enable.
 525  */
 526 static int bcm2835_reset_reset(struct reset_controller_dev *rcdev,
 527                                unsigned long id)
 528 {
 529         struct bcm2835_power *power = container_of(rcdev, struct bcm2835_power,
 530                                                    reset);
 531         struct bcm2835_power_domain *pd;
 532         int ret;
 533
 534         switch (id) {
 535         case BCM2835_RESET_V3D:
 536                 pd = &power->domains[BCM2835_POWER_DOMAIN_GRAFX_V3D];
 537                 break;
 538         case BCM2835_RESET_H264:
 539                 pd = &power->domains[BCM2835_POWER_DOMAIN_IMAGE_H264];
 540                 break;
 541         case BCM2835_RESET_ISP:
 542                 pd = &power->domains[BCM2835_POWER_DOMAIN_IMAGE_ISP];
 543                 break;
 544         default:
 545                 dev_err(power->dev, "Bad reset id %ld\n", id);
 546                 return -EINVAL;
 547         }
 548
 549         ret = bcm2835_power_pd_power_off(&pd->base);
 550         if (ret)
 551                 return ret;
 552
 553         return bcm2835_power_pd_power_on(&pd->base);
 554 }
 555
 556 static int bcm2835_reset_status(struct reset_controller_dev *rcdev,
 557                                 unsigned long id)
 558 {
 559         struct bcm2835_power *power = container_of(rcdev, struct bcm2835_power,
 560                                                    reset);
 561
 562         switch (id) {
 563         case BCM2835_RESET_V3D:
 564                 return !PM_READ(PM_GRAFX & PM_V3DRSTN);
 565         case BCM2835_RESET_H264:
 566                 return !PM_READ(PM_IMAGE & PM_H264RSTN);
 567         case BCM2835_RESET_ISP:
 568                 return !PM_READ(PM_IMAGE & PM_ISPRSTN);
 569         default:
 570                 return -EINVAL;
 571         }
 572 }
 573
 574 static const struct reset_control_ops bcm2835_reset_ops = {
 575         .reset = bcm2835_reset_reset,
 576         .status = bcm2835_reset_status,
 577 };
 578
 579 static const char *const power_domain_names[] = {
 580         [BCM2835_POWER_DOMAIN_GRAFX] = "grafx",
 581         [BCM2835_POWER_DOMAIN_GRAFX_V3D] = "v3d",
 582
 583         [BCM2835_POWER_DOMAIN_IMAGE] = "image",
 584         [BCM2835_POWER_DOMAIN_IMAGE_PERI] = "peri_image",
 585         [BCM2835_POWER_DOMAIN_IMAGE_H264] = "h264",
 586         [BCM2835_POWER_DOMAIN_IMAGE_ISP] = "isp",
 587
 588         [BCM2835_POWER_DOMAIN_USB] = "usb",
 589         [BCM2835_POWER_DOMAIN_DSI0] = "dsi0",
 590         [BCM2835_POWER_DOMAIN_DSI1] = "dsi1",
 591         [BCM2835_POWER_DOMAIN_CAM0] = "cam0",
 592         [BCM2835_POWER_DOMAIN_CAM1] = "cam1",
 593         [BCM2835_POWER_DOMAIN_CCP2TX] = "ccp2tx",
 594         [BCM2835_POWER_DOMAIN_HDMI] = "hdmi",
 595 };
 596
 597 static int bcm2835_power_probe(struct platform_device *pdev)
 598 {
 599         struct bcm2835_pm *pm = dev_get_drvdata(pdev->dev.parent);
 600         struct device *dev = &pdev->dev;
 601         struct bcm2835_power *power;
 602         static const struct {
 603                 int parent, child;
 604         } domain_deps[] = {
 605                 { BCM2835_POWER_DOMAIN_GRAFX, BCM2835_POWER_DOMAIN_GRAFX_V3D },
 606                 { BCM2835_POWER_DOMAIN_IMAGE, BCM2835_POWER_DOMAIN_IMAGE_PERI },
 607                 { BCM2835_POWER_DOMAIN_IMAGE, BCM2835_POWER_DOMAIN_IMAGE_H264 },
 608                 { BCM2835_POWER_DOMAIN_IMAGE, BCM2835_POWER_DOMAIN_IMAGE_ISP },
 609                 { BCM2835_POWER_DOMAIN_IMAGE_PERI, BCM2835_POWER_DOMAIN_USB },
 610                 { BCM2835_POWER_DOMAIN_IMAGE_PERI, BCM2835_POWER_DOMAIN_CAM0 },
 611                 { BCM2835_POWER_DOMAIN_IMAGE_PERI, BCM2835_POWER_DOMAIN_CAM1 },
 612         };
 613         int ret = 0, i;
 614         u32 id;
 615
 616         power = devm_kzalloc(dev, sizeof(*power), GFP_KERNEL);
 617         if (!power)
 618                 return -ENOMEM;
 619         platform_set_drvdata(pdev, power);
 620
 621         power->dev = dev;
 622         power->base = pm->base;
 623         power->asb = pm->asb;
 624
 625         id = ASB_READ(ASB_AXI_BRDG_ID);
 626         if (id != 0x62726467 /* "BRDG" */) {
 627                 dev_err(dev, "ASB register ID returned 0x%08x\n", id);
 628                 return -ENODEV;
 629         }
 630
 631         power->pd_xlate.domains = devm_kcalloc(dev,
 632                                                ARRAY_SIZE(power_domain_names),
 633                                                sizeof(*power->pd_xlate.domains),
 634                                                GFP_KERNEL);
 635         if (!power->pd_xlate.domains)
 636                 return -ENOMEM;
 637
 638         power->pd_xlate.num_domains = ARRAY_SIZE(power_domain_names);
 639
 640         for (i = 0; i < ARRAY_SIZE(power_domain_names); i++) {
 641                 ret = bcm2835_init_power_domain(power, i, power_domain_names[i]);
 642                 if (ret)
 643                         goto fail;
 644         }
 645
 646         for (i = 0; i < ARRAY_SIZE(domain_deps); i++) {
 647                 pm_genpd_add_subdomain(&power->domains[domain_deps[i].parent].base,
 648                                        &power->domains[domain_deps[i].child].base);
 649         }
 650
 651         power->reset.owner = THIS_MODULE;
 652         power->reset.nr_resets = BCM2835_RESET_COUNT;
 653         power->reset.ops = &bcm2835_reset_ops;
 654         power->reset.of_node = dev->parent->of_node;
 655
 656         ret = devm_reset_controller_register(dev, &power->reset);
 657         if (ret)
 658                 goto fail;
 659
 660         of_genpd_add_provider_onecell(dev->parent->of_node, &power->pd_xlate);
 661
 662         dev_info(dev, "Broadcom BCM2835 power domains driver");
 663         return 0;
 664
 665 fail:
 666         for (i = 0; i < ARRAY_SIZE(power_domain_names); i++) {
 667                 struct generic_pm_domain *dom = &power->domains[i].base;
 668
 669                 if (dom->name)
 670                         pm_genpd_remove(dom);
 671         }
 672         return ret;
 673 }
 674
 675 static int bcm2835_power_remove(struct platform_device *pdev)
 676 {
 677         return 0;
 678 }
 679
 680 static struct platform_driver bcm2835_power_driver = {
 681         .probe          = bcm2835_power_probe,
 682         .remove         = bcm2835_power_remove,
 683         .driver = {
 684                 .name = "bcm2835-power",
 685         },
 686 };
 687 module_platform_driver(bcm2835_power_driver);
 688
 689 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
 690 MODULE_DESCRIPTION("Driver for Broadcom BCM2835 PM power domains and reset");
 691 MODULE_LICENSE("GPL");