1 /*------------------------------------------------------------------------
2 . smc91111.h - macros for the LAN91C111 Ethernet Driver
5 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 . Rolf Offermanns <rof@sysgo.de>
7 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
8 . Developed by Simple Network Magic Corporation (SNMC)
9 . Copyright (C) 1996 by Erik Stahlman (ES)
11 . This program is free software; you can redistribute it and/or modify
12 . it under the terms of the GNU General Public License as published by
13 . the Free Software Foundation; either version 2 of the License, or
14 . (at your option) any later version.
16 . This program is distributed in the hope that it will be useful,
17 . but WITHOUT ANY WARRANTY; without even the implied warranty of
18 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 . GNU General Public License for more details.
21 . You should have received a copy of the GNU General Public License
22 . along with this program; if not, write to the Free Software
23 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 . This file contains register information and access macros for
26 . the LAN91C111 single chip ethernet controller. It is a modified
27 . version of the smc9194.h file.
29 . Information contained in this file was obtained from the LAN91C111
30 . manual from SMC. To get a copy, if you really want one, you can find
31 . information under www.smsc.com.
34 . Erik Stahlman ( erik@vt.edu )
35 . Daris A Nevil ( dnevil@snmc.com )
38 . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device
40 ---------------------------------------------------------------------------*/
44 #include <asm/types.h>
48 * This function may be called by the board specific initialisation code
49 * in order to override the default mac address.
52 void smc_set_mac_addr(const char *addr);
55 /* I want some simple types */
57 typedef unsigned char byte;
58 typedef unsigned short word;
59 typedef unsigned long int dword;
64 . 0 for normal operation
65 . 1 for slightly more details
66 . >2 for various levels of increasingly useless information
67 . 2 for interrupt tracking, status flags
69 . 4 for complete packet dumps
71 /*#define SMC_DEBUG 0 */
73 /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
75 #define SMC_IO_EXTENT 16
79 #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
80 #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
81 #define SMC_inb(p) ({ \
82 unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p)); \
83 unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \
84 if (__p & 1) __v >>= 8; \
88 #define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d)
89 #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
90 #define SMC_outb(d,r) ({ word __d = (byte)(d); \
91 word __w = SMC_inw((r)&~1); \
92 __w &= ((r)&1) ? 0x00FF : 0xFF00; \
93 __w |= ((r)&1) ? __d<<8 : __d; \
94 SMC_outw(__w,(r)&~1); \
97 #define SMC_outsl(r,b,l) ({ int __i; \
100 for (__i = 0; __i < l; __i++) { \
101 SMC_outl( *(__b2 + __i), r); \
105 #define SMC_outsw(r,b,l) ({ int __i; \
108 for (__i = 0; __i < l; __i++) { \
109 SMC_outw( *(__b2 + __i), r); \
113 #define SMC_insl(r,b,l) ({ int __i ; \
115 __b2 = (dword *) b; \
116 for (__i = 0; __i < l; __i++) { \
117 *(__b2 + __i) = SMC_inl(r); \
122 #define SMC_insw(r,b,l) ({ int __i ; \
125 for (__i = 0; __i < l; __i++) { \
126 *(__b2 + __i) = SMC_inw(r); \
131 #define SMC_insb(r,b,l) ({ int __i ; \
134 for (__i = 0; __i < l; __i++) { \
135 *(__b2 + __i) = SMC_inb(r); \
140 #else /* if not CONFIG_PXA250 */
143 * We have only 16 Bit PCMCIA access on Socket 0
146 #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
147 #define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF)
149 #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
150 #define SMC_outb(d,r) ({ word __d = (byte)(d); \
151 word __w = SMC_inw((r)&~1); \
152 __w &= ((r)&1) ? 0x00FF : 0xFF00; \
153 __w |= ((r)&1) ? __d<<8 : __d; \
154 SMC_outw(__w,(r)&~1); \
157 #define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l))
159 #define SMC_outsw(r,b,l) ({ int __i; \
162 for (__i = 0; __i < l; __i++) { \
163 SMC_outw( *(__b2 + __i), r); \
169 #define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l))
171 #define SMC_insw(r,b,l) ({ int __i ; \
174 for (__i = 0; __i < l; __i++) { \
175 *(__b2 + __i) = SMC_inw(r); \
183 /*---------------------------------------------------------------
185 . A description of the SMSC registers is probably in order here,
186 . although for details, the SMC datasheet is invaluable.
188 . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
189 . are accessed by writing a number into the BANK_SELECT register
190 . ( I also use a SMC_SELECT_BANK macro for this ).
192 . The banks are configured so that for most purposes, bank 2 is all
193 . that is needed for simple run time tasks.
194 -----------------------------------------------------------------------*/
197 . Bank Select Register:
199 . yyyy yyyy 0000 00xx
201 . yyyy yyyy = 0x33, for identification purposes.
203 #define BANK_SELECT 14
205 /* Transmit Control Register */
207 #define TCR_REG 0x0000 /* transmit control register */
208 #define TCR_ENABLE 0x0001 /* When 1 we can transmit */
209 #define TCR_LOOP 0x0002 /* Controls output pin LBK */
210 #define TCR_FORCOL 0x0004 /* When 1 will force a collision */
211 #define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */
212 #define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */
213 #define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */
214 #define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */
215 #define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */
216 #define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */
217 #define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */
219 #define TCR_CLEAR 0 /* do NOTHING */
220 /* the default settings for the TCR register : */
221 /* QUESTION: do I want to enable padding of short packets ? */
222 #define TCR_DEFAULT TCR_ENABLE
225 /* EPH Status Register */
227 #define EPH_STATUS_REG 0x0002
228 #define ES_TX_SUC 0x0001 /* Last TX was successful */
229 #define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */
230 #define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */
231 #define ES_LTX_MULT 0x0008 /* Last tx was a multicast */
232 #define ES_16COL 0x0010 /* 16 Collisions Reached */
233 #define ES_SQET 0x0020 /* Signal Quality Error Test */
234 #define ES_LTXBRD 0x0040 /* Last tx was a broadcast */
235 #define ES_TXDEFR 0x0080 /* Transmit Deferred */
236 #define ES_LATCOL 0x0200 /* Late collision detected on last tx */
237 #define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */
238 #define ES_EXC_DEF 0x0800 /* Excessive Deferral */
239 #define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */
240 #define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */
241 #define ES_TXUNRN 0x8000 /* Tx Underrun */
244 /* Receive Control Register */
246 #define RCR_REG 0x0004
247 #define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */
248 #define RCR_PRMS 0x0002 /* Enable promiscuous mode */
249 #define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */
250 #define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */
251 #define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */
252 #define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */
253 #define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */
254 #define RCR_SOFTRST 0x8000 /* resets the chip */
256 /* the normal settings for the RCR register : */
257 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
258 #define RCR_CLEAR 0x0 /* set it to a base state */
260 /* Counter Register */
262 #define COUNTER_REG 0x0006
264 /* Memory Information Register */
266 #define MIR_REG 0x0008
268 /* Receive/Phy Control Register */
270 #define RPC_REG 0x000A
271 #define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */
272 #define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */
273 #define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */
274 #define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */
275 #define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */
276 #define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */
277 #define RPC_LED_RES (0x01) /* LED = Reserved */
278 #define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */
279 #define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */
280 #define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */
281 #define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */
282 #define RPC_LED_TX (0x06) /* LED = TX packet occurred */
283 #define RPC_LED_RX (0x07) /* LED = RX packet occurred */
284 #define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
286 /* Bank 0 0x000C is reserved */
288 /* Bank Select Register */
290 #define BSR_REG 0x000E
293 /* Configuration Reg */
295 #define CONFIG_REG 0x0000
296 #define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */
297 #define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */
298 #define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */
299 #define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */
301 /* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */
302 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
305 /* Base Address Register */
307 #define BASE_REG 0x0002
310 /* Individual Address Registers */
312 #define ADDR0_REG 0x0004
313 #define ADDR1_REG 0x0006
314 #define ADDR2_REG 0x0008
317 /* General Purpose Register */
319 #define GP_REG 0x000A
322 /* Control Register */
324 #define CTL_REG 0x000C
325 #define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */
326 #define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */
327 #define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */
328 #define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */
329 #define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */
330 #define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */
331 #define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */
332 #define CTL_STORE 0x0001 /* When set stores registers into EEPROM */
333 #define CTL_DEFAULT (0x1210)
335 /* MMU Command Register */
337 #define MMU_CMD_REG 0x0000
338 #define MC_BUSY 1 /* When 1 the last release has not completed */
339 #define MC_NOP (0<<5) /* No Op */
340 #define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */
341 #define MC_RESET (2<<5) /* Reset MMU to initial state */
342 #define MC_REMOVE (3<<5) /* Remove the current rx packet */
343 #define MC_RELEASE (4<<5) /* Remove and release the current rx packet */
344 #define MC_FREEPKT (5<<5) /* Release packet in PNR register */
345 #define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */
346 #define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */
349 /* Packet Number Register */
351 #define PN_REG 0x0002
354 /* Allocation Result Register */
356 #define AR_REG 0x0003
357 #define AR_FAILED 0x80 /* Alocation Failed */
360 /* RX FIFO Ports Register */
362 #define RXFIFO_REG 0x0004 /* Must be read as a word */
363 #define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */
366 /* TX FIFO Ports Register */
368 #define TXFIFO_REG RXFIFO_REG /* Must be read as a word */
369 #define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */
372 /* Pointer Register */
374 #define PTR_REG 0x0006
375 #define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */
376 #define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */
377 #define PTR_READ 0x2000 /* When 1 the operation is a read */
382 #define SMC91111_DATA_REG 0x0008
385 /* Interrupt Status/Acknowledge Register */
387 #define SMC91111_INT_REG 0x000C
390 /* Interrupt Mask Register */
392 #define IM_REG 0x000D
393 #define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */
394 #define IM_ERCV_INT 0x40 /* Early Receive Interrupt */
395 #define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */
396 #define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */
397 #define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */
398 #define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */
399 #define IM_TX_INT 0x02 /* Transmit Interrrupt */
400 #define IM_RCV_INT 0x01 /* Receive Interrupt */
403 /* Multicast Table Registers */
405 #define MCAST_REG1 0x0000
406 #define MCAST_REG2 0x0002
407 #define MCAST_REG3 0x0004
408 #define MCAST_REG4 0x0006
411 /* Management Interface Register (MII) */
413 #define MII_REG 0x0008
414 #define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */
415 #define MII_MDOE 0x0008 /* MII Output Enable */
416 #define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */
417 #define MII_MDI 0x0002 /* MII Input, pin MDI */
418 #define MII_MDO 0x0001 /* MII Output, pin MDO */
421 /* Revision Register */
423 #define REV_REG 0x000A /* ( hi: chip id low: rev # ) */
426 /* Early RCV Register */
428 /* this is NOT on SMC9192 */
429 #define ERCV_REG 0x000C
430 #define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */
431 #define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */
433 /* External Register */
435 #define EXT_REG 0x0000
443 #define CHIP_91100FD 8
444 #define CHIP_91111FD 9
447 static const char * chip_ids[ 15 ] = {
449 /* 3 */ "SMC91C90/91C92",
454 /* 8 */ "SMC91C100FD",
461 . Transmit status bits
463 #define TS_SUCCESS 0x0001
464 #define TS_LOSTCAR 0x0400
465 #define TS_LATCOL 0x0200
466 #define TS_16COL 0x0010
469 . Receive status bits
471 #define RS_ALGNERR 0x8000
472 #define RS_BRODCAST 0x4000
473 #define RS_BADCRC 0x2000
474 #define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */
475 #define RS_TOOLONG 0x0800
476 #define RS_TOOSHORT 0x0400
477 #define RS_MULTICAST 0x0001
478 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
483 PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */
488 /* PHY Register Addresses (LAN91C111 Internal PHY) */
490 /* PHY Control Register */
491 #define PHY_CNTL_REG 0x00
492 #define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */
493 #define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */
494 #define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */
495 #define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */
496 #define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */
497 #define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */
498 #define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */
499 #define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */
500 #define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */
502 /* PHY Status Register */
503 #define PHY_STAT_REG 0x01
504 #define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */
505 #define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */
506 #define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */
507 #define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */
508 #define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */
509 #define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */
510 #define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */
511 #define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */
512 #define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */
513 #define PHY_STAT_LINK 0x0004 /* 1=valid link */
514 #define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */
515 #define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */
517 /* PHY Identifier Registers */
518 #define PHY_ID1_REG 0x02 /* PHY Identifier 1 */
519 #define PHY_ID2_REG 0x03 /* PHY Identifier 2 */
521 /* PHY Auto-Negotiation Advertisement Register */
522 #define PHY_AD_REG 0x04
523 #define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */
524 #define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */
525 #define PHY_AD_RF 0x2000 /* 1=advertise remote fault */
526 #define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */
527 #define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */
528 #define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */
529 #define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */
530 #define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */
531 #define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */
533 /* PHY Auto-negotiation Remote End Capability Register */
534 #define PHY_RMT_REG 0x05
535 /* Uses same bit definitions as PHY_AD_REG */
537 /* PHY Configuration Register 1 */
538 #define PHY_CFG1_REG 0x10
539 #define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */
540 #define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */
541 #define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */
542 #define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */
543 #define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */
544 #define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */
545 #define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */
546 #define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */
547 #define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */
548 #define PHY_CFG1_TLVL_MASK 0x003C
549 #define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */
552 /* PHY Configuration Register 2 */
553 #define PHY_CFG2_REG 0x11
554 #define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */
555 #define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */
556 #define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */
557 #define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */
559 /* PHY Status Output (and Interrupt status) Register */
560 #define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */
561 #define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */
562 #define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */
563 #define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */
564 #define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */
565 #define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */
566 #define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */
567 #define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */
568 #define PHY_INT_JAB 0x0100 /* 1=Jabber detected */
569 #define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */
570 #define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */
572 /* PHY Interrupt/Status Mask Register */
573 #define PHY_MASK_REG 0x13 /* Interrupt Mask */
574 /* Uses the same bit definitions as PHY_INT_REG */
577 /*-------------------------------------------------------------------------
578 . I define some macros to make it easier to do somewhat common
579 . or slightly complicated, repeated tasks.
580 --------------------------------------------------------------------------*/
582 /* select a register bank, 0 to 3 */
584 #define SMC_SELECT_BANK(x) { SMC_outw( x, BANK_SELECT ); }
586 /* this enables an interrupt in the interrupt mask register */
587 #define SMC_ENABLE_INT(x) {\
590 mask = SMC_inb( IM_REG );\
592 SMC_outb( mask, IM_REG ); \
595 /* this disables an interrupt from the interrupt mask register */
597 #define SMC_DISABLE_INT(x) {\
600 mask = SMC_inb( IM_REG );\
602 SMC_outb( mask, IM_REG ); \
605 /*----------------------------------------------------------------------
606 . Define the interrupts that I want to receive from the card
609 . IM_EPH_INT, for nasty errors
610 . IM_RCV_INT, for happy received packets
611 . IM_RX_OVRN_INT, because I have to kick the receiver
612 . IM_MDINT, for PHY Register 18 Status Changes
613 --------------------------------------------------------------------------*/
614 #define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \
617 #endif /* _SMC_91111_H_ */