1 /*------------------------------------------------------------------------
3 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 . Rolf Offermanns <rof@sysgo.de>
9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
10 . Developed by Simple Network Magic Corporation (SNMC)
11 . Copyright (C) 1996 by Erik Stahlman (ES)
13 . This program is free software; you can redistribute it and/or modify
14 . it under the terms of the GNU General Public License as published by
15 . the Free Software Foundation; either version 2 of the License, or
16 . (at your option) any later version.
18 . This program is distributed in the hope that it will be useful,
19 . but WITHOUT ANY WARRANTY; without even the implied warranty of
20 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 . GNU General Public License for more details.
23 . You should have received a copy of the GNU General Public License
24 . along with this program; if not, write to the Free Software
25 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 . Information contained in this file was obtained from the LAN91C111
28 . manual from SMC. To get a copy, if you really want one, you can find
29 . information under www.smsc.com.
32 . "Features" of the SMC chip:
33 . Integrated PHY/MAC for 10/100BaseT Operation
34 . Supports internal and external MII
35 . Integrated 8K packet memory
36 . EEPROM interface for configuration
39 . io = for the base address
43 . Erik Stahlman ( erik@vt.edu )
44 . Daris A Nevil ( dnevil@snmc.com )
47 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
50 . o SMSC LAN91C111 databook (www.smsc.com)
51 . o smc9194.c by Erik Stahlman
52 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
55 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
56 . 10/17/01 Marco Hasewinkel Modify for DNP/1110
57 . 07/25/01 Woojung Huh Modify for ADS Bitsy
58 . 04/25/01 Daris A Nevil Initial public release through SMSC
59 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
60 ----------------------------------------------------------------------------*/
67 #ifdef CONFIG_DRIVER_SMC91111
69 /* Use power-down feature of the chip */
74 static const char version[] =
75 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
79 /*------------------------------------------------------------------------
81 . Configuration options, for the experienced user to change.
83 -------------------------------------------------------------------------*/
86 . Wait time for memory to be free. This probably shouldn't be
87 . tuned that much, as waiting for this means nothing else happens
90 #define MEMORY_WAIT_TIME 16
94 #define PRINTK3(args...) printf(args)
96 #define PRINTK3(args...)
100 #define PRINTK2(args...) printf(args)
102 #define PRINTK2(args...)
106 #define PRINTK(args...) printf(args)
108 #define PRINTK(args...)
112 /*------------------------------------------------------------------------
114 . The internal workings of the driver. If you are changing anything
115 . here with the SMC stuff, you should have the datasheet and know
116 . what you are doing.
118 -------------------------------------------------------------------------*/
119 #define CARDNAME "LAN91C111"
121 /* Memory sizing constant */
122 #define LAN91C111_MEMORY_MULTIPLIER (1024*2)
124 #ifndef CONFIG_SMC91111_BASE
125 #define CONFIG_SMC91111_BASE 0x20000300
128 #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
130 #define SMC_DEV_NAME "SMC91111"
131 #define SMC_PHY_ADDR 0x0000
132 #define SMC_ALLOC_MAX_TRY 5
133 #define SMC_TX_TIMEOUT 30
135 #define SMC_PHY_CLOCK_DELAY 1000
139 #ifdef CONFIG_SMC_USE_32_BIT
144 /*-----------------------------------------------------------------
146 . The driver can be entered at any of the following entry points.
148 .------------------------------------------------------------------ */
150 extern int eth_init(bd_t *bd);
151 extern void eth_halt(void);
152 extern int eth_rx(void);
153 extern int eth_send(volatile void *packet, int length);
160 . This is called by register_netdev(). It is responsible for
161 . checking the portlist for the SMC9000 series chipset. If it finds
162 . one, then it will initialize the device, find the hardware information,
163 . and sets up the appropriate device parameters.
164 . NOTE: Interrupts are *OFF* when this procedure is called.
166 . NB:This shouldn't be static since it is referred to externally.
171 . This is called by unregister_netdev(). It is responsible for
172 . cleaning up before the driver is finally unregistered and discarded.
174 void smc_destructor(void);
177 . The kernel calls this function when someone wants to use the device,
178 . typically 'ifconfig ethX up'.
180 static int smc_open(bd_t *bd);
184 . This is called by the kernel in response to 'ifconfig ethX down'. It
185 . is responsible for cleaning up everything that the open routine
186 . does, and maybe putting the card into a powerdown state.
188 static int smc_close(void);
191 . Configures the PHY through the MII Management interface
193 #ifndef CONFIG_SMC91111_EXT_PHY
194 static void smc_phy_configure(void);
195 #endif /* !CONFIG_SMC91111_EXT_PHY */
198 . This is a separate procedure to handle the receipt of a packet, to
199 . leave the interrupt code looking slightly cleaner
201 static int smc_rcv(void);
203 /* See if a MAC address is defined in the current environment. If so use it. If not
204 . print a warning and set the environment and other globals with the default.
205 . If an EEPROM is present it really should be consulted.
207 int smc_get_ethaddr(bd_t *bd);
208 int get_rom_mac(char *v_rom_mac);
211 ------------------------------------------------------------
215 ------------------------------------------------------------
218 static char smc_mac_addr[] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
221 * This function must be called before smc_open() if you want to override
222 * the default mac address.
225 void smc_set_mac_addr(const char *addr) {
228 for (i=0; i < sizeof(smc_mac_addr); i++){
229 smc_mac_addr[i] = addr[i];
234 * smc_get_macaddr is no longer used. If you want to override the default
235 * mac address, call smc_get_mac_addr as a part of the board initialization.
239 void smc_get_macaddr( byte *addr ) {
240 /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */
241 unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010);
245 for (i=0; i<6; i++) {
246 addr[0] = *(dnp1110_mac+0);
247 addr[1] = *(dnp1110_mac+1);
248 addr[2] = *(dnp1110_mac+2);
249 addr[3] = *(dnp1110_mac+3);
250 addr[4] = *(dnp1110_mac+4);
251 addr[5] = *(dnp1110_mac+5);
256 /***********************************************
257 * Show available memory *
258 ***********************************************/
259 void dump_memory_info(void)
264 old_bank = SMC_inw(BANK_SELECT)&0xF;
267 mem_info = SMC_inw( MIR_REG );
268 PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048);
270 SMC_SELECT_BANK(old_bank);
273 . A rather simple routine to print out a packet for debugging purposes.
276 static void print_packet( byte *, int );
279 #define tx_done(dev) 1
283 /* this does a soft reset on the device */
284 static void smc_reset( void );
286 /* Enable Interrupts, Receive, and Transmit */
287 static void smc_enable( void );
289 /* this puts the device in an inactive state */
290 static void smc_shutdown( void );
292 /* Routines to Read and Write the PHY Registers across the
293 MII Management Interface
296 #ifndef CONFIG_SMC91111_EXT_PHY
297 static word smc_read_phy_register(byte phyreg);
298 static void smc_write_phy_register(byte phyreg, word phydata);
299 #endif /* !CONFIG_SMC91111_EXT_PHY */
302 static int poll4int( byte mask, int timeout ) {
303 int tmo = get_timer(0) + timeout * CFG_HZ;
305 word old_bank = SMC_inw(BSR_REG);
307 PRINTK2("Polling...\n");
309 while((SMC_inw(SMC91111_INT_REG) & mask) == 0)
311 if (get_timer(0) >= tmo) {
317 /* restore old bank selection */
318 SMC_SELECT_BANK(old_bank);
326 /* Only one release command at a time, please */
327 static inline void smc_wait_mmu_release_complete(void)
330 /* assume bank 2 selected */
331 while ( SMC_inw(MMU_CMD_REG) & MC_BUSY ) {
332 udelay(1); // Wait until not busy
333 if( ++count > 200) break;
338 . Function: smc_reset( void )
340 . This sets the SMC91111 chip to its normal state, hopefully from whatever
341 . mess that any other DOS driver has put it in.
343 . Maybe I should reset more registers to defaults in here? SOFTRST should
347 . 1. send a SOFT RESET
348 . 2. wait for it to finish
349 . 3. enable autorelease mode
350 . 4. reset the memory management unit
351 . 5. clear all interrupts
354 static void smc_reset( void )
356 PRINTK2("%s:smc_reset\n", SMC_DEV_NAME);
358 /* This resets the registers mostly to defaults, but doesn't
359 affect EEPROM. That seems unnecessary */
360 SMC_SELECT_BANK( 0 );
361 SMC_outw( RCR_SOFTRST, RCR_REG );
363 /* Setup the Configuration Register */
364 /* This is necessary because the CONFIG_REG is not affected */
365 /* by a soft reset */
367 SMC_SELECT_BANK( 1 );
368 #if defined(CONFIG_SMC91111_EXT_PHY)
369 SMC_outw( CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
371 SMC_outw( CONFIG_DEFAULT, CONFIG_REG);
375 /* Release from possible power-down state */
376 /* Configuration register is not affected by Soft Reset */
377 SMC_outw( SMC_inw( CONFIG_REG ) | CONFIG_EPH_POWER_EN, CONFIG_REG );
379 SMC_SELECT_BANK( 0 );
381 /* this should pause enough for the chip to be happy */
384 /* Disable transmit and receive functionality */
385 SMC_outw( RCR_CLEAR, RCR_REG );
386 SMC_outw( TCR_CLEAR, TCR_REG );
388 /* set the control register */
389 SMC_SELECT_BANK( 1 );
390 SMC_outw( CTL_DEFAULT, CTL_REG );
393 SMC_SELECT_BANK( 2 );
394 smc_wait_mmu_release_complete();
395 SMC_outw( MC_RESET, MMU_CMD_REG );
396 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
397 udelay(1); /* Wait until not busy */
399 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
400 but this is a place where future chipsets _COULD_ break. Be wary
401 of issuing another MMU command right after this */
403 /* Disable all interrupts */
404 SMC_outb( 0, IM_REG );
408 . Function: smc_enable
409 . Purpose: let the chip talk to the outside work
411 . 1. Enable the transmitter
412 . 2. Enable the receiver
413 . 3. Enable interrupts
415 static void smc_enable()
417 PRINTK2("%s:smc_enable\n", SMC_DEV_NAME);
418 SMC_SELECT_BANK( 0 );
419 /* see the header file for options in TCR/RCR DEFAULT*/
420 SMC_outw( TCR_DEFAULT, TCR_REG );
421 SMC_outw( RCR_DEFAULT, RCR_REG );
424 /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
428 . Function: smc_shutdown
429 . Purpose: closes down the SMC91xxx chip.
431 . 1. zero the interrupt mask
432 . 2. clear the enable receive flag
433 . 3. clear the enable xmit flags
436 . (1) maybe utilize power down mode.
437 . Why not yet? Because while the chip will go into power down mode,
438 . the manual says that it will wake up in response to any I/O requests
439 . in the register space. Empirical results do not show this working.
441 static void smc_shutdown()
443 PRINTK2(CARDNAME ":smc_shutdown\n");
445 /* no more interrupts for me */
446 SMC_SELECT_BANK( 2 );
447 SMC_outb( 0, IM_REG );
449 /* and tell the card to stay away from that nasty outside world */
450 SMC_SELECT_BANK( 0 );
451 SMC_outb( RCR_CLEAR, RCR_REG );
452 SMC_outb( TCR_CLEAR, TCR_REG );
457 . Function: smc_hardware_send_packet(struct net_device * )
459 . This sends the actual packet to the SMC9xxx chip.
462 . First, see if a saved_skb is available.
463 . ( this should NOT be called if there is no 'saved_skb'
464 . Now, find the packet number that the chip allocated
465 . Point the data pointers at it in memory
466 . Set the length word in the chip's memory
467 . Dump the packet to chip memory
468 . Check if a last byte is needed ( odd length packet )
469 . if so, set the control flag right
470 . Tell the card to send it
471 . Enable the transmit interrupt, so I know if it failed
472 . Free the kernel data if I actually sent it.
474 static int smc_send_packet(volatile void *packet, int packet_length)
477 unsigned long ioaddr;
486 PRINTK3("%s:smc_hardware_send_packet\n", SMC_DEV_NAME);
488 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
491 ** The MMU wants the number of pages to be the number of 256 bytes
492 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
494 ** The 91C111 ignores the size bits, but the code is left intact
495 ** for backwards and future compatibility.
497 ** Pkt size for allocating is data length +6 (for additional status
498 ** words, length and ctl!)
500 ** If odd size then last byte is included in this header.
502 numPages = ((length & 0xfffe) + 6);
503 numPages >>= 8; /* Divide by 256 */
506 printf("%s: Far too big packet error. \n", SMC_DEV_NAME);
510 /* now, try to allocate the memory */
511 SMC_SELECT_BANK( 2 );
512 SMC_outw( MC_ALLOC | numPages, MMU_CMD_REG );
514 /* FIXME: the ALLOC_INT bit never gets set *
515 * so the following will always give a *
516 * memory allocation error. *
517 * same code works in armboot though *
523 time_out = MEMORY_WAIT_TIME;
525 status = SMC_inb( SMC91111_INT_REG );
526 if ( status & IM_ALLOC_INT ) {
527 /* acknowledge the interrupt */
528 SMC_outb( IM_ALLOC_INT, SMC91111_INT_REG );
531 } while ( -- time_out );
534 PRINTK2("%s: memory allocation, try %d failed ...\n",
536 if (try < SMC_ALLOC_MAX_TRY)
542 PRINTK2("%s: memory allocation, try %d succeeded ...\n",
546 /* I can send the packet now.. */
548 ioaddr = SMC_BASE_ADDRESS;
550 buf = (byte *)packet;
552 /* If I get here, I _know_ there is a packet slot waiting for me */
553 packet_no = SMC_inb( AR_REG );
554 if ( packet_no & AR_FAILED ) {
555 /* or isn't there? BAD CHIP! */
556 printf("%s: Memory allocation failed. \n",
561 /* we have a packet address, so tell the card to use it */
562 SMC_outb( packet_no, PN_REG );
564 /* point to the beginning of the packet */
565 SMC_outw( PTR_AUTOINC , PTR_REG );
567 PRINTK3("%s: Trying to xmit packet of length %x\n",
568 SMC_DEV_NAME, length);
571 printf("Transmitting Packet\n");
572 print_packet( buf, length );
575 /* send the packet length ( +6 for status, length and ctl byte )
576 and the status word ( set to zeros ) */
578 SMC_outl( (length +6 ) << 16 , SMC91111_DATA_REG );
580 SMC_outw( 0, SMC91111_DATA_REG );
581 /* send the packet length ( +6 for status words, length, and ctl*/
582 SMC_outw( (length+6), SMC91111_DATA_REG );
585 /* send the actual data
586 . I _think_ it's faster to send the longs first, and then
587 . mop up by sending the last word. It depends heavily
588 . on alignment, at least on the 486. Maybe it would be
589 . a good idea to check which is optimal? But that could take
590 . almost as much time as is saved?
593 SMC_outsl(SMC91111_DATA_REG, buf, length >> 2 );
595 SMC_outw(*((word *)(buf + (length & 0xFFFFFFFC))), SMC91111_DATA_REG);
597 SMC_outsw(SMC91111_DATA_REG , buf, (length ) >> 1);
598 #endif /* USE_32_BIT */
600 /* Send the last byte, if there is one. */
601 if ( (length & 1) == 0 ) {
602 SMC_outw( 0, SMC91111_DATA_REG );
604 SMC_outw( buf[length -1 ] | 0x2000, SMC91111_DATA_REG );
607 /* and let the chipset deal with it */
608 SMC_outw( MC_ENQUEUE , MMU_CMD_REG );
610 /* poll for TX INT */
611 if (poll4int(IM_TX_INT, SMC_TX_TIMEOUT)) {
613 PRINTK2("%s: TX timeout, sending failed...\n",
617 SMC_outw(MC_FREEPKT, MMU_CMD_REG);
619 /* wait for MMU getting ready (low) */
620 while (SMC_inw(MMU_CMD_REG) & MC_BUSY)
625 PRINTK2("MMU ready\n");
631 SMC_outw(IM_TX_INT, SMC91111_INT_REG);
632 PRINTK2("%s: Sent packet of length %d \n", SMC_DEV_NAME, length);
635 SMC_outw(MC_FREEPKT, MMU_CMD_REG);
637 /* wait for MMU getting ready (low) */
638 while (SMC_inw(MMU_CMD_REG) & MC_BUSY)
643 PRINTK2("MMU ready\n");
651 /*-------------------------------------------------------------------------
653 | smc_destructor( struct net_device * dev )
655 | dev, pointer to the device structure
660 ---------------------------------------------------------------------------
662 void smc_destructor()
664 PRINTK2(CARDNAME ":smc_destructor\n");
669 * Open and Initialize the board
671 * Set up everything, reset the card, etc ..
674 static int smc_open(bd_t *bd)
678 PRINTK2("%s:smc_open\n", SMC_DEV_NAME);
680 /* reset the hardware */
684 /* Configure the PHY */
685 #ifndef CONFIG_SMC91111_EXT_PHY
689 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
690 /* SMC_SELECT_BANK(0); */
691 /* SMC_outw(0, RPC_REG); */
694 err = smc_get_ethaddr(bd); /* set smc_mac_addr, and sync it with u-boot globals */
696 memset(bd->bi_enetaddr, 0, 6); /* hack to make error stick! upper code will abort if not set*/
697 return(-1); /* upper code ignores this, but NOT bi_enetaddr */
701 for ( i = 0; i < 6; i += 2 ) {
704 address = smc_mac_addr[ i + 1 ] << 8 ;
705 address |= smc_mac_addr[ i ];
706 SMC_outw( address, ADDR0_REG + i );
709 for ( i = 0; i < 6; i ++ )
710 SMC_outb( smc_mac_addr[i], ADDR0_REG + i );
716 #if 0 /* dead code? -- wd */
725 for (__i = 0; __i < l; __i++) {
726 *(__b2 + __i) = *(dword *)(r+0x10000300);
732 /*-------------------------------------------------------------
734 . smc_rcv - receive a packet from the card
736 . There is ( at least ) a packet waiting to be read from
740 . o If an error, record it
741 . o otherwise, read in the packet
742 --------------------------------------------------------------
756 packet_number = SMC_inw( RXFIFO_REG );
758 if ( packet_number & RXFIFO_REMPTY ) {
763 PRINTK3("%s:smc_rcv\n", SMC_DEV_NAME);
764 /* start reading from the start of the packet */
765 SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
767 /* First two words are status and packet_length */
769 stat_len = SMC_inl(SMC91111_DATA_REG);
770 status = stat_len & 0xffff;
771 packet_length = stat_len >> 16;
773 status = SMC_inw( SMC91111_DATA_REG );
774 packet_length = SMC_inw( SMC91111_DATA_REG );
777 packet_length &= 0x07ff; /* mask off top bits */
779 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
781 if ( !(status & RS_ERRORS ) ){
782 /* Adjust for having already read the first two words */
783 packet_length -= 4; /*4; */
787 /* set odd length for bug in LAN91C111, */
788 /* which never sets RS_ODDFRAME */
793 PRINTK3(" Reading %d dwords (and %d bytes) \n",
794 packet_length >> 2, packet_length & 3 );
795 /* QUESTION: Like in the TX routine, do I want
796 to send the DWORDs or the bytes first, or some
797 mixture. A mixture might improve already slow PIO
799 SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 );
800 /* read the left over bytes */
801 if (packet_length & 3) {
804 byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3));
805 dword leftover = SMC_inl(SMC91111_DATA_REG);
806 for (i=0; i<(packet_length & 3); i++)
807 *tail++ = (byte) (leftover >> (8*i)) & 0xff;
810 PRINTK3(" Reading %d words and %d byte(s) \n",
811 (packet_length >> 1 ), packet_length & 1 );
812 SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1);
814 #endif /* USE_32_BIT */
817 printf("Receiving Packet\n");
818 print_packet( NetRxPackets[0], packet_length );
826 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
827 udelay(1); /* Wait until not busy */
829 /* error or good, tell the card to get rid of this packet */
830 SMC_outw( MC_RELEASE, MMU_CMD_REG );
832 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
833 udelay(1); /* Wait until not busy */
836 /* Pass the packet up to the protocol layers. */
837 NetReceive(NetRxPackets[0], packet_length);
838 return packet_length;
847 /*----------------------------------------------------
850 . this makes the board clean up everything that it can
851 . and not talk to the outside world. Caused by
852 . an 'ifconfig ethX down'
854 -----------------------------------------------------*/
855 static int smc_close()
857 PRINTK2("%s:smc_close\n", SMC_DEV_NAME);
859 /* clear everything */
867 /*------------------------------------------------------------
868 . Modify a bit in the LAN91C111 register set
869 .-------------------------------------------------------------*/
870 static word smc_modify_regbit(int bank, int ioaddr, int reg,
871 unsigned int bit, int val)
875 SMC_SELECT_BANK( bank );
877 regval = SMC_inw( reg );
883 SMC_outw( regval, 0 );
888 /*------------------------------------------------------------
889 . Retrieve a bit in the LAN91C111 register set
890 .-------------------------------------------------------------*/
891 static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit)
893 SMC_SELECT_BANK( bank );
894 if ( SMC_inw( reg ) & bit)
901 /*------------------------------------------------------------
902 . Modify a LAN91C111 register (word access only)
903 .-------------------------------------------------------------*/
904 static void smc_modify_reg(int bank, int ioaddr, int reg, word val)
906 SMC_SELECT_BANK( bank );
907 SMC_outw( val, reg );
911 /*------------------------------------------------------------
912 . Retrieve a LAN91C111 register (word access only)
913 .-------------------------------------------------------------*/
914 static int smc_get_reg(int bank, int ioaddr, int reg)
916 SMC_SELECT_BANK( bank );
917 return(SMC_inw( reg ));
922 /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
926 /*------------------------------------------------------------
927 . Debugging function for viewing MII Management serial bitstream
928 .-------------------------------------------------------------*/
929 static void smc_dump_mii_stream(byte* bits, int size)
934 for (i = 0; i < size; ++i)
940 for (i = 0; i < size; ++i)
942 if (bits[i] & MII_MDOE)
949 for (i = 0; i < size; ++i)
951 if (bits[i] & MII_MDO)
958 for (i = 0; i < size; ++i)
960 if (bits[i] & MII_MDI)
970 /*------------------------------------------------------------
971 . Reads a register from the MII Management serial interface
972 .-------------------------------------------------------------*/
973 #ifndef CONFIG_SMC91111_EXT_PHY
974 static word smc_read_phy_register(byte phyreg)
984 byte phyaddr = SMC_PHY_ADDR;
986 /* 32 consecutive ones on MDO to establish sync */
987 for (i = 0; i < 32; ++i)
988 bits[clk_idx++] = MII_MDOE | MII_MDO;
990 /* Start code <01> */
991 bits[clk_idx++] = MII_MDOE;
992 bits[clk_idx++] = MII_MDOE | MII_MDO;
994 /* Read command <10> */
995 bits[clk_idx++] = MII_MDOE | MII_MDO;
996 bits[clk_idx++] = MII_MDOE;
998 /* Output the PHY address, msb first */
1000 for (i = 0; i < 5; ++i)
1003 bits[clk_idx++] = MII_MDOE | MII_MDO;
1005 bits[clk_idx++] = MII_MDOE;
1007 /* Shift to next lowest bit */
1011 /* Output the phy register number, msb first */
1013 for (i = 0; i < 5; ++i)
1016 bits[clk_idx++] = MII_MDOE | MII_MDO;
1018 bits[clk_idx++] = MII_MDOE;
1020 /* Shift to next lowest bit */
1024 /* Tristate and turnaround (2 bit times) */
1025 bits[clk_idx++] = 0;
1026 /*bits[clk_idx++] = 0; */
1028 /* Input starts at this bit time */
1029 input_idx = clk_idx;
1031 /* Will input 16 bits */
1032 for (i = 0; i < 16; ++i)
1033 bits[clk_idx++] = 0;
1035 /* Final clock bit */
1036 bits[clk_idx++] = 0;
1038 /* Save the current bank */
1039 oldBank = SMC_inw( BANK_SELECT );
1042 SMC_SELECT_BANK( 3 );
1044 /* Get the current MII register value */
1045 mii_reg = SMC_inw( MII_REG );
1047 /* Turn off all MII Interface bits */
1048 mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
1050 /* Clock all 64 cycles */
1051 for (i = 0; i < sizeof bits; ++i)
1053 /* Clock Low - output data */
1054 SMC_outw( mii_reg | bits[i], MII_REG );
1055 udelay(SMC_PHY_CLOCK_DELAY);
1058 /* Clock Hi - input data */
1059 SMC_outw( mii_reg | bits[i] | MII_MCLK, MII_REG );
1060 udelay(SMC_PHY_CLOCK_DELAY);
1061 bits[i] |= SMC_inw( MII_REG ) & MII_MDI;
1064 /* Return to idle state */
1065 /* Set clock to low, data to low, and output tristated */
1066 SMC_outw( mii_reg, MII_REG );
1067 udelay(SMC_PHY_CLOCK_DELAY);
1069 /* Restore original bank select */
1070 SMC_SELECT_BANK( oldBank );
1072 /* Recover input data */
1074 for (i = 0; i < 16; ++i)
1078 if (bits[input_idx++] & MII_MDI)
1082 #if (SMC_DEBUG > 2 )
1083 printf("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1084 phyaddr, phyreg, phydata);
1085 smc_dump_mii_stream(bits, sizeof bits);
1092 /*------------------------------------------------------------
1093 . Writes a register to the MII Management serial interface
1094 .-------------------------------------------------------------*/
1095 static void smc_write_phy_register(byte phyreg, word phydata)
1103 byte phyaddr = SMC_PHY_ADDR;
1105 /* 32 consecutive ones on MDO to establish sync */
1106 for (i = 0; i < 32; ++i)
1107 bits[clk_idx++] = MII_MDOE | MII_MDO;
1109 /* Start code <01> */
1110 bits[clk_idx++] = MII_MDOE;
1111 bits[clk_idx++] = MII_MDOE | MII_MDO;
1113 /* Write command <01> */
1114 bits[clk_idx++] = MII_MDOE;
1115 bits[clk_idx++] = MII_MDOE | MII_MDO;
1117 /* Output the PHY address, msb first */
1119 for (i = 0; i < 5; ++i)
1122 bits[clk_idx++] = MII_MDOE | MII_MDO;
1124 bits[clk_idx++] = MII_MDOE;
1126 /* Shift to next lowest bit */
1130 /* Output the phy register number, msb first */
1132 for (i = 0; i < 5; ++i)
1135 bits[clk_idx++] = MII_MDOE | MII_MDO;
1137 bits[clk_idx++] = MII_MDOE;
1139 /* Shift to next lowest bit */
1143 /* Tristate and turnaround (2 bit times) */
1144 bits[clk_idx++] = 0;
1145 bits[clk_idx++] = 0;
1147 /* Write out 16 bits of data, msb first */
1149 for (i = 0; i < 16; ++i)
1152 bits[clk_idx++] = MII_MDOE | MII_MDO;
1154 bits[clk_idx++] = MII_MDOE;
1156 /* Shift to next lowest bit */
1160 /* Final clock bit (tristate) */
1161 bits[clk_idx++] = 0;
1163 /* Save the current bank */
1164 oldBank = SMC_inw( BANK_SELECT );
1167 SMC_SELECT_BANK( 3 );
1169 /* Get the current MII register value */
1170 mii_reg = SMC_inw( MII_REG );
1172 /* Turn off all MII Interface bits */
1173 mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
1175 /* Clock all cycles */
1176 for (i = 0; i < sizeof bits; ++i)
1178 /* Clock Low - output data */
1179 SMC_outw( mii_reg | bits[i], MII_REG );
1180 udelay(SMC_PHY_CLOCK_DELAY);
1183 /* Clock Hi - input data */
1184 SMC_outw( mii_reg | bits[i] | MII_MCLK, MII_REG );
1185 udelay(SMC_PHY_CLOCK_DELAY);
1186 bits[i] |= SMC_inw( MII_REG ) & MII_MDI;
1189 /* Return to idle state */
1190 /* Set clock to low, data to low, and output tristated */
1191 SMC_outw( mii_reg, MII_REG );
1192 udelay(SMC_PHY_CLOCK_DELAY);
1194 /* Restore original bank select */
1195 SMC_SELECT_BANK( oldBank );
1197 #if (SMC_DEBUG > 2 )
1198 printf("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1199 phyaddr, phyreg, phydata);
1200 smc_dump_mii_stream(bits, sizeof bits);
1203 #endif /* !CONFIG_SMC91111_EXT_PHY */
1207 /*------------------------------------------------------------
1208 . Waits the specified number of milliseconds - kernel friendly
1209 .-------------------------------------------------------------*/
1210 #ifndef CONFIG_SMC91111_EXT_PHY
1211 static void smc_wait_ms(unsigned int ms)
1215 #endif /* !CONFIG_SMC91111_EXT_PHY */
1219 /*------------------------------------------------------------
1220 . Configures the specified PHY using Autonegotiation. Calls
1221 . smc_phy_fixed() if the user has requested a certain config.
1222 .-------------------------------------------------------------*/
1223 #ifndef CONFIG_SMC91111_EXT_PHY
1224 static void smc_phy_configure()
1228 word my_phy_caps; /* My PHY capabilities */
1229 word my_ad_caps; /* My Advertised capabilities */
1230 word status = 0; /*;my status = 0 */
1233 PRINTK3("%s:smc_program_phy()\n", SMC_DEV_NAME);
1237 /* Get the detected phy address */
1238 phyaddr = SMC_PHY_ADDR;
1240 /* Reset the PHY, setting all other bits to zero */
1241 smc_write_phy_register(PHY_CNTL_REG, PHY_CNTL_RST);
1243 /* Wait for the reset to complete, or time out */
1244 timeout = 6; /* Wait up to 3 seconds */
1247 if (!(smc_read_phy_register(PHY_CNTL_REG)
1250 /* reset complete */
1254 smc_wait_ms(500); /* wait 500 millisecs */
1259 printf("%s:PHY reset timed out\n", SMC_DEV_NAME);
1260 goto smc_phy_configure_exit;
1263 /* Read PHY Register 18, Status Output */
1264 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1266 /* Enable PHY Interrupts (for register 18) */
1267 /* Interrupts listed here are disabled */
1268 smc_write_phy_register(PHY_INT_REG, 0xffff);
1270 /* Configure the Receive/Phy Control register */
1271 SMC_SELECT_BANK( 0 );
1272 SMC_outw( RPC_DEFAULT, RPC_REG );
1274 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
1275 my_phy_caps = smc_read_phy_register(PHY_STAT_REG);
1276 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
1278 if (my_phy_caps & PHY_STAT_CAP_T4)
1279 my_ad_caps |= PHY_AD_T4;
1281 if (my_phy_caps & PHY_STAT_CAP_TXF)
1282 my_ad_caps |= PHY_AD_TX_FDX;
1284 if (my_phy_caps & PHY_STAT_CAP_TXH)
1285 my_ad_caps |= PHY_AD_TX_HDX;
1287 if (my_phy_caps & PHY_STAT_CAP_TF)
1288 my_ad_caps |= PHY_AD_10_FDX;
1290 if (my_phy_caps & PHY_STAT_CAP_TH)
1291 my_ad_caps |= PHY_AD_10_HDX;
1293 /* Update our Auto-Neg Advertisement Register */
1294 smc_write_phy_register( PHY_AD_REG, my_ad_caps);
1296 PRINTK2("%s:phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
1297 PRINTK2("%s:phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
1299 /* Restart auto-negotiation process in order to advertise my caps */
1300 smc_write_phy_register( PHY_CNTL_REG,
1301 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST );
1303 /* Wait for the auto-negotiation to complete. This may take from */
1304 /* 2 to 3 seconds. */
1305 /* Wait for the reset to complete, or time out */
1306 timeout = 20; /* Wait up to 10 seconds */
1309 status = smc_read_phy_register( PHY_STAT_REG);
1310 if (status & PHY_STAT_ANEG_ACK)
1312 /* auto-negotiate complete */
1316 smc_wait_ms(500); /* wait 500 millisecs */
1318 /* Restart auto-negotiation if remote fault */
1319 if (status & PHY_STAT_REM_FLT)
1321 printf("%s:PHY remote fault detected\n", SMC_DEV_NAME);
1323 /* Restart auto-negotiation */
1324 printf("%s:PHY restarting auto-negotiation\n",
1326 smc_write_phy_register( PHY_CNTL_REG,
1327 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST |
1328 PHY_CNTL_SPEED | PHY_CNTL_DPLX);
1334 printf("%s:PHY auto-negotiate timed out\n",
1336 printf("%s:PHY auto-negotiate timed out\n", SMC_DEV_NAME);
1340 /* Fail if we detected an auto-negotiate remote fault */
1341 if (status & PHY_STAT_REM_FLT)
1343 printf( "%s:PHY remote fault detected\n", SMC_DEV_NAME);
1344 printf("%s:PHY remote fault detected\n", SMC_DEV_NAME);
1348 /* Re-Configure the Receive/Phy Control register */
1349 SMC_outw( RPC_DEFAULT, RPC_REG );
1351 smc_phy_configure_exit:
1354 #endif /* !CONFIG_SMC91111_EXT_PHY */
1358 static void print_packet( byte * buf, int length )
1365 printf("Packet of length %d \n", length );
1368 lines = length / 16;
1369 remainder = length % 16;
1371 for ( i = 0; i < lines ; i ++ ) {
1374 for ( cur = 0; cur < 8; cur ++ ) {
1379 printf("%02x%02x ", a, b );
1383 for ( i = 0; i < remainder/2 ; i++ ) {
1388 printf("%02x%02x ", a, b );
1396 int eth_init(bd_t *bd) {
1397 return (smc_open(bd));
1408 int eth_send(volatile void *packet, int length) {
1409 return smc_send_packet(packet, length);
1412 int smc_get_ethaddr(bd_t *bd)
1414 int env_size, rom_valid, env_present = 0, reg;
1415 char *s = NULL, *e, *v_mac, es[] = "11:22:33:44:55:66";
1416 uchar s_env_mac[64], v_env_mac[6], v_rom_mac[6];
1418 env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac));
1419 if ((env_size > 0) && (env_size < sizeof(es))) { /* exit if env is bad */
1420 printf("\n*** ERROR: ethaddr is not set properly!!\n");
1429 for (reg = 0; reg < 6; ++reg) { /* turn string into mac value */
1430 v_env_mac[reg] = s ? simple_strtoul (s, &e, 16) : 0;
1432 s = (*e) ? e + 1 : e;
1435 rom_valid = get_rom_mac(v_rom_mac); /* get ROM mac value if any */
1437 if(!env_present){ /* if NO env */
1438 if(rom_valid){ /* but ROM is valid */
1440 sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", v_mac[0],
1441 v_mac[1] ,v_mac[2], v_mac[3],v_mac[4], v_mac[5]) ;
1442 setenv ("ethaddr", s_env_mac);
1443 }else{ /* no env, bad ROM */
1444 printf("\n*** ERROR: ethaddr is NOT set !!\n");
1447 }else /* good env, don't care ROM */
1448 v_mac = v_env_mac; /* always use a good env over a ROM */
1450 if(env_present && rom_valid) /* if both env and ROM are good */
1451 if(memcmp(v_env_mac, v_rom_mac, 6) != 0){
1452 printf("\n*** Warning: Environment and ROM MAC addresses don't match\n");
1453 printf("*** Using Environment MAC\n");
1455 memcpy (bd->bi_enetaddr, v_mac, 6); /* update global address to match env (allows env changing) */
1456 smc_set_mac_addr(v_mac); /* use old function to update smc default */
1460 int get_rom_mac(char *v_rom_mac)
1462 int is_rom_present = 0;
1463 #ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */
1464 char hw_mac_addr[] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
1466 memcpy (v_rom_mac, hw_mac_addr, 6);
1471 /* if eeprom contents are valid
1472 * extract mac address into hw_mac_addr, 8 or 16 bit accesses
1473 * memcpy (v_rom_mac, hc_mac_addr, 6);
1477 memset(v_rom_mac, 0, 6);
1482 #endif /* CONFIG_DRIVER_SMC91111 */