2 * Pinmuxed GPIO support for SuperH.
4 * Copyright (C) 2008 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/errno.h>
13 #include <linux/kernel.h>
14 #include <linux/list.h>
15 #include <linux/module.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
19 #include <linux/irq.h>
20 #include <linux/bitops.h>
21 #include <linux/gpio.h>
22 #include <linux/slab.h>
23 #include <linux/ioport.h>
25 static void pfc_iounmap(struct pinmux_info *pip)
29 for (k = 0; k < pip->num_resources; k++)
30 if (pip->window[k].virt)
31 iounmap(pip->window[k].virt);
37 static int pfc_ioremap(struct pinmux_info *pip)
42 if (!pip->num_resources)
45 pip->window = kzalloc(pip->num_resources * sizeof(*pip->window),
50 for (k = 0; k < pip->num_resources; k++) {
51 res = pip->resource + k;
52 WARN_ON(resource_type(res) != IORESOURCE_MEM);
53 pip->window[k].phys = res->start;
54 pip->window[k].size = resource_size(res);
55 pip->window[k].virt = ioremap_nocache(res->start,
57 if (!pip->window[k].virt)
69 static void __iomem *pfc_phys_to_virt(struct pinmux_info *pip,
70 unsigned long address)
72 struct pfc_window *window;
75 /* scan through physical windows and convert address */
76 for (k = 0; k < pip->num_resources; k++) {
77 window = pip->window + k;
79 if (address < window->phys)
82 if (address >= (window->phys + window->size))
85 return window->virt + (address - window->phys);
88 /* no windows defined, register must be 1:1 mapped virt:phys */
89 return (void __iomem *)address;
92 static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
94 if (enum_id < r->begin)
103 static unsigned long gpio_read_raw_reg(void __iomem *mapped_reg,
104 unsigned long reg_width)
108 return ioread8(mapped_reg);
110 return ioread16(mapped_reg);
112 return ioread32(mapped_reg);
119 static void gpio_write_raw_reg(void __iomem *mapped_reg,
120 unsigned long reg_width,
125 iowrite8(data, mapped_reg);
128 iowrite16(data, mapped_reg);
131 iowrite32(data, mapped_reg);
138 static void gpio_write_bit(struct pinmux_data_reg *dr,
139 unsigned long in_pos, unsigned long value)
143 pos = dr->reg_width - (in_pos + 1);
145 pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
147 dr->reg, !!value, pos, dr->reg_width);
150 set_bit(pos, &dr->reg_shadow);
152 clear_bit(pos, &dr->reg_shadow);
154 gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
157 static int gpio_read_reg(void __iomem *mapped_reg, unsigned long reg_width,
158 unsigned long field_width, unsigned long in_pos,
161 unsigned long data, mask, pos;
164 mask = (1 << field_width) - 1;
165 pos = reg_width - ((in_pos + 1) * field_width);
167 pr_debug("read_reg: addr = %lx, pos = %ld, "
168 "r_width = %ld, f_width = %ld\n",
169 reg, pos, reg_width, field_width);
171 data = gpio_read_raw_reg(mapped_reg, reg_width);
172 return (data >> pos) & mask;
175 static void gpio_write_reg(void __iomem *mapped_reg, unsigned long reg_width,
176 unsigned long field_width, unsigned long in_pos,
177 unsigned long value, unsigned long reg)
179 unsigned long mask, pos;
181 mask = (1 << field_width) - 1;
182 pos = reg_width - ((in_pos + 1) * field_width);
184 pr_debug("write_reg addr = %lx, value = %ld, pos = %ld, "
185 "r_width = %ld, f_width = %ld\n",
186 reg, value, pos, reg_width, field_width);
188 mask = ~(mask << pos);
189 value = value << pos;
193 iowrite8((ioread8(mapped_reg) & mask) | value, mapped_reg);
196 iowrite16((ioread16(mapped_reg) & mask) | value, mapped_reg);
199 iowrite32((ioread32(mapped_reg) & mask) | value, mapped_reg);
204 static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
206 struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
207 struct pinmux_data_reg *data_reg;
210 if (!enum_in_range(gpiop->enum_id, &gpioc->data))
215 data_reg = gpioc->data_regs + k;
217 if (!data_reg->reg_width)
220 data_reg->mapped_reg = pfc_phys_to_virt(gpioc, data_reg->reg);
222 for (n = 0; n < data_reg->reg_width; n++) {
223 if (data_reg->enum_ids[n] == gpiop->enum_id) {
224 gpiop->flags &= ~PINMUX_FLAG_DREG;
225 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
226 gpiop->flags &= ~PINMUX_FLAG_DBIT;
227 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
239 static void setup_data_regs(struct pinmux_info *gpioc)
241 struct pinmux_data_reg *drp;
244 for (k = gpioc->first_gpio; k <= gpioc->last_gpio; k++)
245 setup_data_reg(gpioc, k);
249 drp = gpioc->data_regs + k;
254 drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg,
260 static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
261 struct pinmux_data_reg **drp, int *bitp)
263 struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
266 if (!enum_in_range(gpiop->enum_id, &gpioc->data))
269 k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
270 n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
271 *drp = gpioc->data_regs + k;
276 static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
277 struct pinmux_cfg_reg **crp, int *indexp,
278 unsigned long **cntp)
280 struct pinmux_cfg_reg *config_reg;
281 unsigned long r_width, f_width;
286 config_reg = gpioc->cfg_regs + k;
288 r_width = config_reg->reg_width;
289 f_width = config_reg->field_width;
293 for (n = 0; n < (r_width / f_width) * (1 << f_width); n++) {
294 if (config_reg->enum_ids[n] == enum_id) {
297 *cntp = &config_reg->cnt[n / (1 << f_width)];
307 static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
308 int pos, pinmux_enum_t *enum_idp)
310 pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
311 pinmux_enum_t *data = gpioc->gpio_data;
314 if (!enum_in_range(enum_id, &gpioc->data)) {
315 if (!enum_in_range(enum_id, &gpioc->mark)) {
316 pr_err("non data/mark enum_id for gpio %d\n", gpio);
322 *enum_idp = data[pos + 1];
326 for (k = 0; k < gpioc->gpio_data_size; k++) {
327 if (data[k] == enum_id) {
328 *enum_idp = data[k + 1];
333 pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
337 static void write_config_reg(struct pinmux_info *gpioc,
338 struct pinmux_cfg_reg *crp,
341 unsigned long ncomb, pos, value;
342 void __iomem *mapped_reg;
344 ncomb = 1 << crp->field_width;
346 value = index % ncomb;
348 mapped_reg = pfc_phys_to_virt(gpioc, crp->reg);
350 gpio_write_reg(mapped_reg, crp->reg_width, crp->field_width,
351 pos, value, crp->reg);
354 static int check_config_reg(struct pinmux_info *gpioc,
355 struct pinmux_cfg_reg *crp,
358 unsigned long ncomb, pos, value;
359 void __iomem *mapped_reg;
361 ncomb = 1 << crp->field_width;
363 value = index % ncomb;
365 mapped_reg = pfc_phys_to_virt(gpioc, crp->reg);
367 if (gpio_read_reg(mapped_reg, crp->reg_width,
368 crp->field_width, pos, crp->reg) == value)
374 enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
376 static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
377 int pinmux_type, int cfg_mode)
379 struct pinmux_cfg_reg *cr = NULL;
380 pinmux_enum_t enum_id;
381 struct pinmux_range *range;
382 int in_range, pos, index;
385 switch (pinmux_type) {
387 case PINMUX_TYPE_FUNCTION:
391 case PINMUX_TYPE_OUTPUT:
392 range = &gpioc->output;
395 case PINMUX_TYPE_INPUT:
396 range = &gpioc->input;
399 case PINMUX_TYPE_INPUT_PULLUP:
400 range = &gpioc->input_pu;
403 case PINMUX_TYPE_INPUT_PULLDOWN:
404 range = &gpioc->input_pd;
415 pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
422 /* first check if this is a function enum */
423 in_range = enum_in_range(enum_id, &gpioc->function);
425 /* not a function enum */
428 * other range exists, so this pin is
429 * a regular GPIO pin that now is being
430 * bound to a specific direction.
432 * for this case we only allow function enums
433 * and the enums that match the other range.
435 in_range = enum_in_range(enum_id, range);
438 * special case pass through for fixed
439 * input-only or output-only pins without
440 * function enum register association.
442 if (in_range && enum_id == range->force)
446 * no other range exists, so this pin
447 * must then be of the function type.
449 * allow function type pins to select
450 * any combination of function/in/out
451 * in their MARK lists.
460 if (get_config_reg(gpioc, enum_id, &cr, &index, &cntp) != 0)
464 case GPIO_CFG_DRYRUN:
465 if (!*cntp || !check_config_reg(gpioc, cr, index))
470 write_config_reg(gpioc, cr, index);
485 static DEFINE_SPINLOCK(gpio_lock);
487 static struct pinmux_info *chip_to_pinmux(struct gpio_chip *chip)
489 return container_of(chip, struct pinmux_info, chip);
492 static int sh_gpio_request(struct gpio_chip *chip, unsigned offset)
494 struct pinmux_info *gpioc = chip_to_pinmux(chip);
495 struct pinmux_data_reg *dummy;
497 int i, ret, pinmux_type;
504 spin_lock_irqsave(&gpio_lock, flags);
506 if ((gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
509 /* setup pin function here if no data is associated with pin */
511 if (get_data_reg(gpioc, offset, &dummy, &i) != 0)
512 pinmux_type = PINMUX_TYPE_FUNCTION;
514 pinmux_type = PINMUX_TYPE_GPIO;
516 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
517 if (pinmux_config_gpio(gpioc, offset,
519 GPIO_CFG_DRYRUN) != 0)
522 if (pinmux_config_gpio(gpioc, offset,
528 gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
529 gpioc->gpios[offset].flags |= pinmux_type;
533 spin_unlock_irqrestore(&gpio_lock, flags);
538 static void sh_gpio_free(struct gpio_chip *chip, unsigned offset)
540 struct pinmux_info *gpioc = chip_to_pinmux(chip);
547 spin_lock_irqsave(&gpio_lock, flags);
549 pinmux_type = gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE;
550 pinmux_config_gpio(gpioc, offset, pinmux_type, GPIO_CFG_FREE);
551 gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
552 gpioc->gpios[offset].flags |= PINMUX_TYPE_NONE;
554 spin_unlock_irqrestore(&gpio_lock, flags);
557 static int pinmux_direction(struct pinmux_info *gpioc,
558 unsigned gpio, int new_pinmux_type)
566 pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
568 switch (pinmux_type) {
569 case PINMUX_TYPE_GPIO:
571 case PINMUX_TYPE_OUTPUT:
572 case PINMUX_TYPE_INPUT:
573 case PINMUX_TYPE_INPUT_PULLUP:
574 case PINMUX_TYPE_INPUT_PULLDOWN:
575 pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
581 if (pinmux_config_gpio(gpioc, gpio,
583 GPIO_CFG_DRYRUN) != 0)
586 if (pinmux_config_gpio(gpioc, gpio,
591 gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
592 gpioc->gpios[gpio].flags |= new_pinmux_type;
599 static int sh_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
601 struct pinmux_info *gpioc = chip_to_pinmux(chip);
605 spin_lock_irqsave(&gpio_lock, flags);
606 ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_INPUT);
607 spin_unlock_irqrestore(&gpio_lock, flags);
612 static void sh_gpio_set_value(struct pinmux_info *gpioc,
613 unsigned gpio, int value)
615 struct pinmux_data_reg *dr = NULL;
618 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
621 gpio_write_bit(dr, bit, value);
624 static int sh_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
627 struct pinmux_info *gpioc = chip_to_pinmux(chip);
631 sh_gpio_set_value(gpioc, offset, value);
632 spin_lock_irqsave(&gpio_lock, flags);
633 ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_OUTPUT);
634 spin_unlock_irqrestore(&gpio_lock, flags);
639 static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
641 struct pinmux_data_reg *dr = NULL;
644 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
647 return gpio_read_reg(dr->mapped_reg, dr->reg_width, 1, bit, dr->reg);
650 static int sh_gpio_get(struct gpio_chip *chip, unsigned offset)
652 return sh_gpio_get_value(chip_to_pinmux(chip), offset);
655 static void sh_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
657 sh_gpio_set_value(chip_to_pinmux(chip), offset, value);
660 static int sh_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
662 struct pinmux_info *gpioc = chip_to_pinmux(chip);
663 pinmux_enum_t enum_id;
664 pinmux_enum_t *enum_ids;
670 pos = get_gpio_enum_id(gpioc, offset, pos, &enum_id);
671 if (pos <= 0 || !enum_id)
674 for (i = 0; i < gpioc->gpio_irq_size; i++) {
675 enum_ids = gpioc->gpio_irq[i].enum_ids;
676 for (k = 0; enum_ids[k]; k++) {
677 if (enum_ids[k] == enum_id)
678 return gpioc->gpio_irq[i].irq;
686 int register_pinmux(struct pinmux_info *pip)
688 struct gpio_chip *chip = &pip->chip;
691 pr_info("%s handling gpio %d -> %d\n",
692 pip->name, pip->first_gpio, pip->last_gpio);
694 ret = pfc_ioremap(pip);
698 setup_data_regs(pip);
700 chip->request = sh_gpio_request;
701 chip->free = sh_gpio_free;
702 chip->direction_input = sh_gpio_direction_input;
703 chip->get = sh_gpio_get;
704 chip->direction_output = sh_gpio_direction_output;
705 chip->set = sh_gpio_set;
706 chip->to_irq = sh_gpio_to_irq;
708 WARN_ON(pip->first_gpio != 0); /* needs testing */
710 chip->label = pip->name;
711 chip->owner = THIS_MODULE;
712 chip->base = pip->first_gpio;
713 chip->ngpio = (pip->last_gpio - pip->first_gpio) + 1;
715 ret = gpiochip_add(chip);
722 int unregister_pinmux(struct pinmux_info *pip)
724 pr_info("%s deregistering\n", pip->name);
726 return gpiochip_remove(&pip->chip);