4 * Pantelis Antoniou <panto@intracom.gr>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #ifdef CONFIG_MAX3100_SERIAL
31 /**************************************************************/
33 /* convienient macros */
34 #define MAX3100_SPI_RXD() (MAX3100_SPI_RXD_PORT & MAX3100_SPI_RXD_BIT)
36 #define MAX3100_SPI_TXD(x) \
39 MAX3100_SPI_TXD_PORT |= MAX3100_SPI_TXD_BIT; \
41 MAX3100_SPI_TXD_PORT &= ~MAX3100_SPI_TXD_BIT; \
44 #define MAX3100_SPI_CLK(x) \
47 MAX3100_SPI_CLK_PORT |= MAX3100_SPI_CLK_BIT; \
49 MAX3100_SPI_CLK_PORT &= ~MAX3100_SPI_CLK_BIT; \
52 #define MAX3100_SPI_CLK_TOGGLE() (MAX3100_SPI_CLK_PORT ^= MAX3100_SPI_CLK_BIT)
54 #define MAX3100_CS(x) \
57 MAX3100_CS_PORT |= MAX3100_CS_BIT; \
59 MAX3100_CS_PORT &= ~MAX3100_CS_BIT; \
62 /**************************************************************/
64 /* MAX3100 definitions */
66 #define MAX3100_WC (3 << 14) /* write configuration */
67 #define MAX3100_RC (1 << 14) /* read configuration */
68 #define MAX3100_WD (2 << 14) /* write data */
69 #define MAX3100_RD (0 << 14) /* read data */
71 /* configuration register bits */
72 #define MAX3100_FEN (1 << 13) /* FIFO enable */
73 #define MAX3100_SHDN (1 << 12) /* shutdown bit */
74 #define MAX3100_TM (1 << 11) /* T bit irq mask */
75 #define MAX3100_RM (1 << 10) /* R bit irq mask */
76 #define MAX3100_PM (1 << 9) /* P bit irq mask */
77 #define MAX3100_RAM (1 << 8) /* mask for RA/FE bit */
78 #define MAX3100_IR (1 << 7) /* IRDA timing mode */
79 #define MAX3100_ST (1 << 6) /* transmit stop bit */
80 #define MAX3100_PE (1 << 5) /* parity enable bit */
81 #define MAX3100_L (1 << 4) /* Length bit */
82 #define MAX3100_B_MASK (0x000F) /* baud rate bits mask */
83 #define MAX3100_B(x) ((x) & 0x000F) /* baud rate select bits */
85 /* data register bits (write) */
86 #define MAX3100_TE (1 << 10) /* transmit enable bit (active low) */
87 #define MAX3100_RTS (1 << 9) /* request-to-send bit (inverted ~RTS pin) */
89 /* data register bits (read) */
90 #define MAX3100_RA (1 << 10) /* receiver activity when in shutdown mode */
91 #define MAX3100_FE (1 << 10) /* framing error when in normal mode */
92 #define MAX3100_CTS (1 << 9) /* clear-to-send bit (inverted ~CTS pin) */
94 /* data register bits (both directions) */
95 #define MAX3100_R (1 << 15) /* receive bit */
96 #define MAX3100_T (1 << 14) /* transmit bit */
97 #define MAX3100_P (1 << 8) /* parity bit */
98 #define MAX3100_D_MASK 0x00FF /* data bits mask */
99 #define MAX3100_D(x) ((x) & 0x00FF) /* data bits */
101 /* these definitions are valid only for fOSC = 3.6864MHz */
102 #define MAX3100_B_230400 MAX3100_B(0)
103 #define MAX3100_B_115200 MAX3100_B(1)
104 #define MAX3100_B_57600 MAX3100_B(2)
105 #define MAX3100_B_38400 MAX3100_B(9)
106 #define MAX3100_B_19200 MAX3100_B(10)
107 #define MAX3100_B_9600 MAX3100_B(11)
108 #define MAX3100_B_4800 MAX3100_B(12)
109 #define MAX3100_B_2400 MAX3100_B(13)
110 #define MAX3100_B_1200 MAX3100_B(14)
111 #define MAX3100_B_600 MAX3100_B(15)
113 /**************************************************************/
115 static inline unsigned int max3100_transfer(unsigned int val)
125 MAX3100_SPI_TXD(val & 0x8000);
127 MAX3100_SPI_CLK_TOGGLE();
130 if (MAX3100_SPI_RXD())
132 MAX3100_SPI_CLK_TOGGLE();
142 /**************************************************************/
144 /* must be power of 2 */
147 static int rxfifo_cnt;
148 static int rxfifo_in;
149 static int rxfifo_out;
150 static unsigned char rxfifo_buf[16];
152 static void max3100_putc(int c)
156 while (((rx = max3100_transfer(MAX3100_RC)) & MAX3100_T) == 0)
159 rx = max3100_transfer(MAX3100_WD | (c & 0xff));
160 if ((rx & MAX3100_RD) != 0 && rxfifo_cnt < RXFIFO_SZ) {
162 rxfifo_buf[rxfifo_in++] = rx & 0xff;
163 rxfifo_in &= RXFIFO_SZ - 1;
167 static int max3100_getc(void)
172 while (rxfifo_cnt == 0) {
173 rx = max3100_transfer(MAX3100_RD);
174 if ((rx & MAX3100_R) != 0) {
177 rxfifo_buf[rxfifo_in++] = rx & 0xff;
178 rxfifo_in &= RXFIFO_SZ - 1;
180 if (rxfifo_cnt >= RXFIFO_SZ)
182 } while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0);
188 c = rxfifo_buf[rxfifo_out++];
189 rxfifo_out &= RXFIFO_SZ - 1;
193 static int max3100_tstc(void)
200 rx = max3100_transfer(MAX3100_RD);
201 if ((rx & MAX3100_R) == 0)
206 rxfifo_buf[rxfifo_in++] = rx & 0xff;
207 rxfifo_in &= RXFIFO_SZ - 1;
209 if (rxfifo_cnt >= RXFIFO_SZ)
211 } while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0);
216 int serial_init(void)
218 unsigned int wconf, rconf;
220 DECLARE_GLOBAL_DATA_PTR;
225 switch (gd->baudrate) {
227 wconf = MAX3100_B_1200;
230 wconf = MAX3100_B_2400;
233 wconf = MAX3100_B_4800;
236 wconf = MAX3100_B_9600;
239 wconf = MAX3100_B_19200;
242 wconf = MAX3100_B_38400;
245 wconf = MAX3100_B_57600;
249 wconf = MAX3100_B_115200;
252 wconf = MAX3100_B_230400;
256 /* try for 10ms, with a 100us gap */
257 for (i = 0; i < 10000; i += 100) {
259 max3100_transfer(MAX3100_WC | wconf);
260 rconf = max3100_transfer(MAX3100_RC) & 0x3fff;
267 rxfifo_in = rxfifo_out = rxfifo_cnt = 0;
272 void serial_putc(const char c)
280 void serial_puts(const char *s)
286 int serial_getc(void)
288 return max3100_getc();
291 int serial_tstc(void)
293 return max3100_tstc();
297 void serial_setbrg(void)