1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
9 #include <debug_uart.h>
16 #include <dm/device_compat.h>
17 #include <linux/compiler.h>
19 #include <linux/err.h>
21 #define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */
22 #define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */
23 #define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */
25 #define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */
26 #define ZYNQ_UART_CR_RX_EN BIT(2) /* RX enabled */
27 #define ZYNQ_UART_CR_TXRST BIT(1) /* TX logic reset */
28 #define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */
30 #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
33 u32 control; /* 0x0 - Control Register [8:0] */
34 u32 mode; /* 0x4 - Mode Register [10:0] */
36 u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
38 u32 channel_sts; /* 0x2c - Channel Status [11:0] */
39 u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
40 u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
43 struct zynq_uart_platdata {
44 struct uart_zynq *regs;
47 /* Set up the baud rate */
48 static void _uart_zynq_serial_setbrg(struct uart_zynq *regs,
49 unsigned long clock, unsigned long baud)
51 /* Calculation results. */
52 unsigned int calc_bauderror, bdiv, bgen;
53 unsigned long calc_baud = 0;
55 /* Covering case where input clock is so slow */
56 if (clock < 1000000 && baud > 4800)
60 * Baud rate = ------------------
63 * Find acceptable values for baud generation.
65 for (bdiv = 4; bdiv < 255; bdiv++) {
66 bgen = clock / (baud * (bdiv + 1));
67 if (bgen < 2 || bgen > 65535)
70 calc_baud = clock / (bgen * (bdiv + 1));
73 * Use first calculated baudrate with
74 * an acceptable (<3%) error
77 calc_bauderror = baud - calc_baud;
79 calc_bauderror = calc_baud - baud;
80 if (((calc_bauderror * 100) / baud) < 3)
84 writel(bdiv, ®s->baud_rate_divider);
85 writel(bgen, ®s->baud_rate_gen);
88 /* Initialize the UART, with...some settings. */
89 static void _uart_zynq_serial_init(struct uart_zynq *regs)
91 /* RX/TX enabled & reset */
92 writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
93 ZYNQ_UART_CR_RXRST, ®s->control);
94 writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */
97 static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
99 if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL)
102 writel(c, ®s->tx_rx_fifo);
107 static int zynq_serial_setbrg(struct udevice *dev, int baudrate)
109 struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
115 ret = clk_get_by_index(dev, 0, &clk);
117 dev_err(dev, "failed to get clock\n");
121 clock = clk_get_rate(&clk);
122 if (IS_ERR_VALUE(clock)) {
123 dev_err(dev, "failed to get rate\n");
126 debug("%s: CLK %ld\n", __func__, clock);
128 ret = clk_enable(&clk);
129 if (ret && ret != -ENOSYS) {
130 dev_err(dev, "failed to enable clock\n");
134 _uart_zynq_serial_setbrg(platdata->regs, clock, baudrate);
139 static int zynq_serial_probe(struct udevice *dev)
141 struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
142 struct uart_zynq *regs = platdata->regs;
145 /* No need to reinitialize the UART if TX already enabled */
146 val = readl(®s->control);
147 if (val & ZYNQ_UART_CR_TX_EN)
150 _uart_zynq_serial_init(platdata->regs);
155 static int zynq_serial_getc(struct udevice *dev)
157 struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
158 struct uart_zynq *regs = platdata->regs;
160 if (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY)
163 return readl(®s->tx_rx_fifo);
166 static int zynq_serial_putc(struct udevice *dev, const char ch)
168 struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
170 return _uart_zynq_serial_putc(platdata->regs, ch);
173 static int zynq_serial_pending(struct udevice *dev, bool input)
175 struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
176 struct uart_zynq *regs = platdata->regs;
179 return !(readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY);
181 return !!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXACTIVE);
184 static int zynq_serial_ofdata_to_platdata(struct udevice *dev)
186 struct zynq_uart_platdata *platdata = dev_get_platdata(dev);
188 platdata->regs = (struct uart_zynq *)dev_read_addr(dev);
189 if (IS_ERR(platdata->regs))
190 return PTR_ERR(platdata->regs);
195 static const struct dm_serial_ops zynq_serial_ops = {
196 .putc = zynq_serial_putc,
197 .pending = zynq_serial_pending,
198 .getc = zynq_serial_getc,
199 .setbrg = zynq_serial_setbrg,
202 static const struct udevice_id zynq_serial_ids[] = {
203 { .compatible = "xlnx,xuartps" },
204 { .compatible = "cdns,uart-r1p8" },
205 { .compatible = "cdns,uart-r1p12" },
209 U_BOOT_DRIVER(serial_zynq) = {
210 .name = "serial_zynq",
212 .of_match = zynq_serial_ids,
213 .ofdata_to_platdata = zynq_serial_ofdata_to_platdata,
214 .platdata_auto_alloc_size = sizeof(struct zynq_uart_platdata),
215 .probe = zynq_serial_probe,
216 .ops = &zynq_serial_ops,
219 #ifdef CONFIG_DEBUG_UART_ZYNQ
220 static inline void _debug_uart_init(void)
222 struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
224 _uart_zynq_serial_init(regs);
225 _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
229 static inline void _debug_uart_putc(int ch)
231 struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
233 while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)