drivers/serial/serial_stm32.c

   1 /*
   2  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
   3  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <asm/io.h>
  12 #include <serial.h>
  13 #include <asm/arch/stm32.h>
  14 #include "serial_stm32.h"
  15
  16 static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
  17 {
  18         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  19         bool stm32f4 = plat->uart_info->stm32f4;
  20         fdt_addr_t base = plat->base;
  21         u32 int_div, mantissa, fraction, oversampling;
  22
  23         int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
  24
  25         if (int_div < 16) {
  26                 oversampling = 8;
  27                 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
  28         } else {
  29                 oversampling = 16;
  30                 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
  31         }
  32
  33         mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
  34         fraction = int_div % oversampling;
  35
  36         writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
  37
  38         return 0;
  39 }
  40
  41 static int stm32_serial_getc(struct udevice *dev)
  42 {
  43         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  44         bool stm32f4 = plat->uart_info->stm32f4;
  45         fdt_addr_t base = plat->base;
  46
  47         if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)
  48                 return -EAGAIN;
  49
  50         return readl(base + RDR_OFFSET(stm32f4));
  51 }
  52
  53 static int stm32_serial_putc(struct udevice *dev, const char c)
  54 {
  55         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  56         bool stm32f4 = plat->uart_info->stm32f4;
  57         fdt_addr_t base = plat->base;
  58
  59         if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)
  60                 return -EAGAIN;
  61
  62         writel(c, base + TDR_OFFSET(stm32f4));
  63
  64         return 0;
  65 }
  66
  67 static int stm32_serial_pending(struct udevice *dev, bool input)
  68 {
  69         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  70         bool stm32f4 = plat->uart_info->stm32f4;
  71         fdt_addr_t base = plat->base;
  72
  73         if (input)
  74                 return readl(base + ISR_OFFSET(stm32f4)) &
  75                         USART_SR_FLAG_RXNE ? 1 : 0;
  76         else
  77                 return readl(base + ISR_OFFSET(stm32f4)) &
  78                         USART_SR_FLAG_TXE ? 0 : 1;
  79 }
  80
  81 static int stm32_serial_probe(struct udevice *dev)
  82 {
  83         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  84         struct clk clk;
  85         fdt_addr_t base = plat->base;
  86         int ret;
  87         bool stm32f4;
  88         u8 uart_enable_bit;
  89
  90         plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
  91         stm32f4 = plat->uart_info->stm32f4;
  92         uart_enable_bit = plat->uart_info->uart_enable_bit;
  93
  94         ret = clk_get_by_index(dev, 0, &clk);
  95         if (ret < 0)
  96                 return ret;
  97
  98         ret = clk_enable(&clk);
  99         if (ret) {
 100                 dev_err(dev, "failed to enable clock\n");
 101                 return ret;
 102         }
 103
 104         plat->clock_rate = clk_get_rate(&clk);
 105         if (plat->clock_rate < 0) {
 106                 clk_disable(&clk);
 107                 return plat->clock_rate;
 108         };
 109
 110         /* Disable uart-> disable overrun-> enable uart */
 111         clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
 112                      BIT(uart_enable_bit));
 113         if (plat->uart_info->has_overrun_disable)
 114                 setbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);
 115         if (plat->uart_info->has_fifo)
 116                 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
 117         setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
 118                      BIT(uart_enable_bit));
 119
 120         return 0;
 121 }
 122
 123 static const struct udevice_id stm32_serial_id[] = {
 124         { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
 125         { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
 126         { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
 127         {}
 128 };
 129
 130 static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
 131 {
 132         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
 133
 134         plat->base = devfdt_get_addr(dev);
 135         if (plat->base == FDT_ADDR_T_NONE)
 136                 return -EINVAL;
 137
 138         return 0;
 139 }
 140
 141 static const struct dm_serial_ops stm32_serial_ops = {
 142         .putc = stm32_serial_putc,
 143         .pending = stm32_serial_pending,
 144         .getc = stm32_serial_getc,
 145         .setbrg = stm32_serial_setbrg,
 146 };
 147
 148 U_BOOT_DRIVER(serial_stm32) = {
 149         .name = "serial_stm32",
 150         .id = UCLASS_SERIAL,
 151         .of_match = of_match_ptr(stm32_serial_id),
 152         .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
 153         .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
 154         .ops = &stm32_serial_ops,
 155         .probe = stm32_serial_probe,
 156         .flags = DM_FLAG_PRE_RELOC,
 157 };