2 * Copy and modify from linux/drivers/serial/sh-sci.h
5 #include <dm/platform_data/serial_sh.h>
8 unsigned long iobase; /* in/out[bwl] */
9 unsigned char *membase; /* read/write[bwl] */
10 unsigned long mapbase; /* for ioremap */
11 enum sh_serial_type type; /* port type */
12 enum sh_clk_mode clk_mode; /* clock mode */
15 #if defined(CONFIG_CPU_SH7721) || \
16 defined(CONFIG_R8A7740)
17 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
18 # define PORT_PTCR 0xA405011EUL
19 # define PORT_PVCR 0xA4050122UL
20 # define SCIF_ORER 0x0200 /* overrun error bit */
21 #elif defined(CONFIG_CPU_SH7750) || \
22 defined(CONFIG_CPU_SH7750R) || \
23 defined(CONFIG_CPU_SH7750S) || \
24 defined(CONFIG_CPU_SH7751) || \
25 defined(CONFIG_CPU_SH7751R)
26 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
27 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
28 # define SCIF_ORER 0x0001 /* overrun error bit */
29 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
30 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
31 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
32 #elif defined(CONFIG_CPU_SH7722)
33 # define PADR 0xA4050120
35 # define PSDR 0xA405013e
36 # define PWDR 0xA4050166
37 # define PSCR 0xA405011E
38 # define SCIF_ORER 0x0001 /* overrun error bit */
39 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
40 #elif defined(CONFIG_CPU_SH7723)
41 # define SCSPTR0 0xa4050160
42 # define SCSPTR1 0xa405013e
43 # define SCSPTR2 0xa4050160
44 # define SCSPTR3 0xa405013e
45 # define SCSPTR4 0xa4050128
46 # define SCSPTR5 0xa4050128
47 # define SCIF_ORER 0x0001 /* overrun error bit */
48 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
49 #elif defined(CONFIG_CPU_SH7734)
50 # define SCSPTR0 0xFFE40020
51 # define SCSPTR1 0xFFE41020
52 # define SCSPTR2 0xFFE42020
53 # define SCSPTR3 0xFFE43020
54 # define SCSPTR4 0xFFE44020
55 # define SCSPTR5 0xFFE45020
56 # define SCIF_ORER 0x0001 /* overrun error bit */
57 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
58 #elif defined(CONFIG_CPU_SH7757) || \
59 defined(CONFIG_CPU_SH7752) || \
60 defined(CONFIG_CPU_SH7753)
61 # define SCSPTR0 0xfe4b0020
62 # define SCSPTR1 0xfe4b0020
63 # define SCSPTR2 0xfe4b0020
64 # define SCIF_ORER 0x0001
65 # define SCSCR_INIT(port) 0x38
67 #elif defined(CONFIG_CPU_SH7763)
68 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
69 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */
70 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
71 # define SCIF_ORER 0x0001 /* overrun error bit */
72 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
73 #elif defined(CONFIG_CPU_SH7780)
74 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
75 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */
76 # define SCIF_ORER 0x0001 /* Overrun error bit */
78 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
79 # define SCSCR_INIT(port) 0x3a
81 #elif defined(CONFIG_RZA1)
82 # define SCSPTR0 0xe8007020 /* 16 bit SCIF */
83 # define SCSPTR1 0xe8007820 /* 16 bit SCIF */
84 # define SCSPTR2 0xe8008020 /* 16 bit SCIF */
85 # define SCSPTR3 0xe8008820 /* 16 bit SCIF */
86 # define SCSPTR4 0xe8009020 /* 16 bit SCIF */
87 # define SCSPTR5 0xe8009820 /* 16 bit SCIF */
88 # define SCSPTR6 0xe800a020 /* 16 bit SCIF */
89 # define SCSPTR7 0xe800a820 /* 16 bit SCIF */
90 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
91 # define SCIF_ORER 0x0001 /* overrun error bit */
92 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_64) || \
93 defined(CONFIG_R7S72100)
94 # if defined(CFG_SCIF_A)
95 # define SCIF_ORER 0x0200
97 # define SCIF_ORER 0x0001
99 # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
100 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
102 # error CPU subtype not defined
106 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
107 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
108 #define SCI_CTRL_FLAGS_TE 0x20 /* all */
109 #define SCI_CTRL_FLAGS_RE 0x10 /* all */
110 #if defined(CONFIG_CPU_SH7750) || \
111 defined(CONFIG_CPU_SH7750R) || \
112 defined(CONFIG_CPU_SH7722) || \
113 defined(CONFIG_CPU_SH7734) || \
114 defined(CONFIG_CPU_SH7750S) || \
115 defined(CONFIG_CPU_SH7751) || \
116 defined(CONFIG_CPU_SH7751R) || \
117 defined(CONFIG_CPU_SH7763) || \
118 defined(CONFIG_CPU_SH7780)
119 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
121 #define SCI_CTRL_FLAGS_REIE 0
123 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
124 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
125 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
126 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
129 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
130 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
131 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
132 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
133 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
134 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
135 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
136 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
138 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
141 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
142 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
143 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
144 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
145 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
146 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
147 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
148 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
150 #if defined(CONFIG_CPU_SH7721) || \
151 defined(CONFIG_R8A7740)
152 # define SCIF_ORER 0x0200
153 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
154 # define SCIF_RFDC_MASK 0x007f
155 # define SCIF_TXROOM_MAX 64
156 #elif defined(CONFIG_CPU_SH7763)
157 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
158 # define SCIF_RFDC_MASK 0x007f
159 # define SCIF_TXROOM_MAX 64
160 /* SH7763 SCIF2 support */
161 # define SCIF2_RFDC_MASK 0x001f
162 # define SCIF2_TXROOM_MAX 16
163 #elif defined(CONFIG_RCAR_GEN2)
164 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
165 # if defined(CFG_SCIF_A)
166 # define SCIF_RFDC_MASK 0x007f
168 # define SCIF_RFDC_MASK 0x001f
171 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
172 # define SCIF_RFDC_MASK 0x001f
173 # define SCIF_TXROOM_MAX 16
177 #define SCIF_ORER 0x0000
180 #define SCxSR_TEND(port)\
181 (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
182 #define SCxSR_ERRORS(port)\
183 (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
184 #define SCxSR_RDxF(port)\
185 (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
186 #define SCxSR_TDxE(port)\
187 (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
188 #define SCxSR_FER(port)\
189 (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
190 #define SCxSR_PER(port)\
191 (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
192 #define SCxSR_BRK(port)\
193 ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
194 #define SCxSR_ORER(port)\
195 (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
197 #if defined(CONFIG_CPU_SH7721) || \
198 defined(CONFIG_R8A7740)
199 # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
200 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
201 # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
202 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
204 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
205 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
206 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
207 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
211 #define SCFCR_RFRST 0x0002
212 #define SCFCR_TFRST 0x0004
213 #define SCFCR_TCRST 0x4000
214 #define SCFCR_MCE 0x0008
217 #define HSSRR_SRE BIT(15)
218 #define HSSRR_SRCYC8 0x0007
220 #define SCI_MAJOR 204
221 #define SCI_MINOR_START 8
223 /* Generic serial flags */
224 #define SCI_RX_THROTTLE 0x0000001
226 #define SCI_MAGIC 0xbabeface
229 * Events are used to schedule things to happen at timer-interrupt
230 * time, instead of at rs interrupt time.
232 #define SCI_EVENT_WRITE_WAKEUP 0
234 #define SCI_IN(size, offset)\
236 return readb(port->membase + (offset));\
238 return readw(port->membase + (offset));\
240 #define SCI_OUT(size, offset, value)\
242 writeb(value, port->membase + (offset));\
243 } else if ((size) == 16) {\
244 writew(value, port->membase + (offset));\
247 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
248 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
249 if (port->type == PORT_SCIF || port->type == PORT_SCIFB ||\
250 port->type == PORT_HSCIF) {\
251 SCI_IN(scif_size, scif_offset)\
252 } else { /* PORT_SCI or PORT_SCIFA */\
253 SCI_IN(sci_size, sci_offset);\
256 static inline void sci_##name##_out(struct uart_port *port,\
257 unsigned int value) {\
258 if (port->type == PORT_SCIF || port->type == PORT_SCIFB ||\
259 port->type == PORT_HSCIF) {\
260 SCI_OUT(scif_size, scif_offset, value)\
261 } else { /* PORT_SCI or PORT_SCIFA */\
262 SCI_OUT(sci_size, sci_offset, value);\
266 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
267 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
268 SCI_IN(scif_size, scif_offset);\
270 static inline void sci_##name##_out(struct uart_port *port,\
271 unsigned int value) {\
272 SCI_OUT(scif_size, scif_offset, value);\
275 #define CPU_SCI_FNS(name, sci_offset, sci_size)\
276 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
277 SCI_IN(sci_size, sci_offset);\
279 static inline void sci_##name##_out(struct uart_port *port,\
280 unsigned int value) {\
281 SCI_OUT(sci_size, sci_offset, value);\
284 #if defined(CONFIG_R8A7740)
285 #if defined(CONFIG_CPU_SH7721) || \
286 defined(CONFIG_SH73A0)
287 #define SCIF_FNS(name, scif_offset, scif_size) \
288 CPU_SCIF_FNS(name, scif_offset, scif_size)
289 #elif defined(CONFIG_R8A7740)
290 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
291 sh4_scifb_offset, sh4_scifb_size) \
292 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
293 sh4_scifb_offset, sh4_scifb_size)
294 #define SCIF_FNS(name, scif_offset, scif_size) \
295 CPU_SCIF_FNS(name, scif_offset, scif_size)
297 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
298 sh4_sci_offset, sh4_sci_size, \
299 sh3_scif_offset, sh3_scif_size,\
300 sh4_scif_offset, sh4_scif_size, \
301 h8_sci_offset, h8_sci_size) \
302 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
303 sh3_scif_offset, sh3_scif_size)
304 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
305 sh4_scif_offset, sh4_scif_size) \
306 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
308 #elif defined(CONFIG_CPU_SH7723)
309 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
310 sh4_scif_offset, sh4_scif_size) \
311 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
312 sh4_scif_offset, sh4_scif_size)
313 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
314 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
316 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
317 sh4_sci_offset, sh4_sci_size, \
318 sh3_scif_offset, sh3_scif_size,\
319 sh4_scif_offset, sh4_scif_size, \
320 h8_sci_offset, h8_sci_size) \
321 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
322 sh4_scif_offset, sh4_scif_size)
323 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \
324 sh4_scif_offset, sh4_scif_size) \
325 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
328 #if defined(CONFIG_CPU_SH7721)
330 SCIF_FNS(SCSMR, 0x00, 16)
331 SCIF_FNS(SCBRR, 0x04, 8)
332 SCIF_FNS(SCSCR, 0x08, 16)
333 SCIF_FNS(SCTDSR, 0x0c, 8)
334 SCIF_FNS(SCFER, 0x10, 16)
335 SCIF_FNS(SCxSR, 0x14, 16)
336 SCIF_FNS(SCFCR, 0x18, 16)
337 SCIF_FNS(SCFDR, 0x1c, 16)
338 SCIF_FNS(SCxTDR, 0x20, 8)
339 SCIF_FNS(SCxRDR, 0x24, 8)
340 SCIF_FNS(SCLSR, 0x00, 0)
341 SCIF_FNS(DL, 0x00, 0) /* dummy */
342 #elif defined(CONFIG_R8A7740)
343 SCIF_FNS(SCSMR, 0x00, 16)
344 SCIF_FNS(SCBRR, 0x04, 8)
345 SCIF_FNS(SCSCR, 0x08, 16)
346 SCIF_FNS(SCTDSR, 0x0c, 16)
347 SCIF_FNS(SCFER, 0x10, 16)
348 SCIF_FNS(SCxSR, 0x14, 16)
349 SCIF_FNS(SCFCR, 0x18, 16)
350 SCIF_FNS(SCFDR, 0x1c, 16)
351 SCIF_FNS(SCTFDR, 0x38, 16)
352 SCIF_FNS(SCRFDR, 0x3c, 16)
353 SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
354 SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
355 SCIF_FNS(SCLSR, 0x00, 0)
356 SCIF_FNS(DL, 0x00, 0) /* dummy */
357 #elif defined(CONFIG_CPU_SH7723)
358 SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
359 SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
360 SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
361 SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
362 SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
363 SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
364 SCIx_FNS(SCSPTR, 0, 0, 0, 0)
365 SCIF_FNS(SCTDSR, 0x0c, 8)
366 SCIF_FNS(SCFER, 0x10, 16)
367 SCIF_FNS(SCFCR, 0x18, 16)
368 SCIF_FNS(SCFDR, 0x1c, 16)
369 SCIF_FNS(SCLSR, 0x24, 16)
370 SCIF_FNS(DL, 0x00, 0) /* dummy */
371 #elif defined(CONFIG_RCAR_GEN2)
372 /* SCIFA and SCIF register offsets and size */
373 SCIx_FNS(SCSMR, 0, 0, 0x00, 16, 0, 0, 0x00, 16, 0, 0)
374 SCIx_FNS(SCBRR, 0, 0, 0x04, 8, 0, 0, 0x04, 8, 0, 0)
375 SCIx_FNS(SCSCR, 0, 0, 0x08, 16, 0, 0, 0x08, 16, 0, 0)
376 SCIx_FNS(SCxTDR, 0, 0, 0x20, 8, 0, 0, 0x0C, 8, 0, 0)
377 SCIx_FNS(SCxSR, 0, 0, 0x14, 16, 0, 0, 0x10, 16, 0, 0)
378 SCIx_FNS(SCxRDR, 0, 0, 0x24, 8, 0, 0, 0x14, 8, 0, 0)
379 SCIF_FNS(SCFCR, 0, 0, 0x18, 16)
380 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
381 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
382 SCIF_FNS(DL, 0, 0, 0x30, 16)
383 SCIF_FNS(CKS, 0, 0, 0x34, 16)
384 SCIF_FNS(HSSRR, 0, 0, 0x40, 16) /* HSCIF only */
385 #if defined(CFG_SCIF_A)
386 SCIF_FNS(SCLSR, 0, 0, 0x14, 16)
388 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
391 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
392 /* name off sz off sz off sz off sz off sz*/
393 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
394 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
395 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
396 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
397 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
398 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
399 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
400 #if defined(CONFIG_CPU_SH7780)
401 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
402 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
403 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
404 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
405 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
406 #elif defined(CONFIG_CPU_SH7763)
407 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
408 SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
409 SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
410 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
411 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
412 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
413 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
416 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
417 #if defined(CONFIG_CPU_SH7722)
418 SCIF_FNS(SCSPTR, 0, 0, 0, 0)
420 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
422 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
424 SCIF_FNS(DL, 0, 0, 0x30, 16)
425 SCIF_FNS(CKS, 0, 0, 0x34, 16)
426 SCIF_FNS(HSSRR, 0, 0, 0x40, 16) /* HSCIF only */
428 #define sci_in(port, reg) sci_##reg##_in(port)
429 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
431 #if defined(CONFIG_CPU_SH7750) || \
432 defined(CONFIG_CPU_SH7751) || \
433 defined(CONFIG_CPU_SH7751R) || \
434 defined(CONFIG_CPU_SH7750R) || \
435 defined(CONFIG_CPU_SH7750S)
436 static inline int sci_rxd_in(struct uart_port *port)
438 if (port->mapbase == 0xffe00000)
439 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
442 #else /* default case for non-SCI processors */
443 static inline int sci_rxd_in(struct uart_port *port)
450 * Values for the BitRate Register (SCBRR)
452 * The values are actually divisors for a frequency which can
453 * be internal to the SH3 (14.7456MHz) or derived from an external
454 * clock source. This driver assumes the internal clock is used;
455 * to support using an external clock source, config options or
456 * possibly command-line options would need to be added.
458 * Also, to support speeds below 2400 (why?) the lower 2 bits of
459 * the SCSMR register would also need to be set to non-zero values.
461 * -- Greg Banks 27Feb2000
463 * Answer: The SCBRR register is only eight bits, and the value in
464 * it gets larger with lower baud rates. At around 2400 (depending on
465 * the peripherial module clock) you run out of bits. However the
466 * lower two bits of SCSMR allow the module clock to be divided down,
467 * scaling the value which is needed in SCBRR.
469 * -- Stuart Menefy - 23 May 2000
471 * I meant, why would anyone bother with bitrates below 2400.
473 * -- Greg Banks - 7Jul2000
475 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
476 * tape reader as a console!
478 * -- Mitch Davis - 15 Jul 2000
481 #if defined(CONFIG_CPU_SH7780)
482 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
483 #elif defined(CONFIG_CPU_SH7721) || \
484 defined(CONFIG_R8A7740)
485 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
486 #elif defined(CONFIG_CPU_SH7723)
487 static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
489 if (port->type == PORT_SCIF)
490 return (clk+16*bps)/(32*bps)-1;
492 return ((clk*2)+16*bps)/(16*bps)-1;
494 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
495 #elif defined(CONFIG_RCAR_GEN2)
496 #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
497 #if defined(CFG_SCIF_A) || defined(CFG_HSCIF)
498 #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */
500 #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
502 #elif defined(CONFIG_RCAR_64)
503 static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
505 if (port->type == PORT_SCIF)
506 return (clk + 16 * bps) / (32 * bps) - 1;
507 else /* PORT_HSCIF */
508 return clk / bps / 8 / 2 - 1; /* Internal Clock, Sampling rate = 8 */
510 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
511 #else /* Generic SH */
512 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
516 #define DL_VALUE(bps, clk) 0