2 * Copy and modify from linux/drivers/serial/sh-sci.h
5 #include <dm/platform_data/serial_sh.h>
8 unsigned long iobase; /* in/out[bwl] */
9 unsigned char *membase; /* read/write[bwl] */
10 unsigned long mapbase; /* for ioremap */
11 enum sh_serial_type type; /* port type */
12 enum sh_clk_mode clk_mode; /* clock mode */
15 #if defined(CONFIG_CPU_SH7706) || \
16 defined(CONFIG_CPU_SH7707) || \
17 defined(CONFIG_CPU_SH7708) || \
18 defined(CONFIG_CPU_SH7709)
19 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
20 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
21 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
22 #elif defined(CONFIG_CPU_SH7705)
23 # define SCIF0 0xA4400000
24 # define SCIF2 0xA4410000
25 # define SCSMR_Ir 0xA44A0000
26 # define IRDA_SCIF SCIF0
27 # define SCPCR 0xA4000116
28 # define SCPDR 0xA4000136
30 /* Set the clock source,
31 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
32 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
34 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
35 #elif defined(CONFIG_CPU_SH7720) || \
36 defined(CONFIG_CPU_SH7721) || \
37 defined(CONFIG_SH73A0) || \
38 defined(CONFIG_R8A7740)
39 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
40 # define PORT_PTCR 0xA405011EUL
41 # define PORT_PVCR 0xA4050122UL
42 # define SCIF_ORER 0x0200 /* overrun error bit */
43 #elif defined(CONFIG_CPU_SH7750) || \
44 defined(CONFIG_CPU_SH7750R) || \
45 defined(CONFIG_CPU_SH7750S) || \
46 defined(CONFIG_CPU_SH7751) || \
47 defined(CONFIG_CPU_SH7751R)
48 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
49 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
50 # define SCIF_ORER 0x0001 /* overrun error bit */
51 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
52 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
53 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
54 #elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
55 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */
56 # define SCIF_ORER 0x0001 /* overrun error bit */
57 # define PACR 0xa4050100
58 # define PBCR 0xa4050102
59 # define SCSCR_INIT(port) 0x3B
60 #elif defined(CONFIG_CPU_SH7722)
61 # define PADR 0xA4050120
63 # define PSDR 0xA405013e
64 # define PWDR 0xA4050166
65 # define PSCR 0xA405011E
66 # define SCIF_ORER 0x0001 /* overrun error bit */
67 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
68 #elif defined(CONFIG_CPU_SH7723)
69 # define SCSPTR0 0xa4050160
70 # define SCSPTR1 0xa405013e
71 # define SCSPTR2 0xa4050160
72 # define SCSPTR3 0xa405013e
73 # define SCSPTR4 0xa4050128
74 # define SCSPTR5 0xa4050128
75 # define SCIF_ORER 0x0001 /* overrun error bit */
76 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
77 #elif defined(CONFIG_CPU_SH7734)
78 # define SCSPTR0 0xFFE40020
79 # define SCSPTR1 0xFFE41020
80 # define SCSPTR2 0xFFE42020
81 # define SCSPTR3 0xFFE43020
82 # define SCSPTR4 0xFFE44020
83 # define SCSPTR5 0xFFE45020
84 # define SCIF_ORER 0x0001 /* overrun error bit */
85 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
86 #elif defined(CONFIG_CPU_SH7757) || \
87 defined(CONFIG_CPU_SH7752) || \
88 defined(CONFIG_CPU_SH7753)
89 # define SCSPTR0 0xfe4b0020
90 # define SCSPTR1 0xfe4b0020
91 # define SCSPTR2 0xfe4b0020
92 # define SCIF_ORER 0x0001
93 # define SCSCR_INIT(port) 0x38
95 #elif defined(CONFIG_CPU_SH7763)
96 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
97 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */
98 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
99 # define SCIF_ORER 0x0001 /* overrun error bit */
100 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
101 #elif defined(CONFIG_CPU_SH7780)
102 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
103 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */
104 # define SCIF_ORER 0x0001 /* Overrun error bit */
106 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
107 # define SCSCR_INIT(port) 0x3a
109 #elif defined(CONFIG_CPU_SH7203) || \
110 defined(CONFIG_CPU_SH7264)
111 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
112 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
113 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
114 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
115 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
116 #elif defined(CONFIG_CPU_SH7269) || defined(CONFIG_RZA1)
117 # define SCSPTR0 0xe8007020 /* 16 bit SCIF */
118 # define SCSPTR1 0xe8007820 /* 16 bit SCIF */
119 # define SCSPTR2 0xe8008020 /* 16 bit SCIF */
120 # define SCSPTR3 0xe8008820 /* 16 bit SCIF */
121 # define SCSPTR4 0xe8009020 /* 16 bit SCIF */
122 # define SCSPTR5 0xe8009820 /* 16 bit SCIF */
123 # define SCSPTR6 0xe800a020 /* 16 bit SCIF */
124 # define SCSPTR7 0xe800a820 /* 16 bit SCIF */
125 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
126 # define SCIF_ORER 0x0001 /* overrun error bit */
127 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || \
128 defined(CONFIG_R7S72100)
129 # if defined(CONFIG_SCIF_A)
130 # define SCIF_ORER 0x0200
132 # define SCIF_ORER 0x0001
134 # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
135 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
137 # error CPU subtype not defined
141 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
142 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
143 #define SCI_CTRL_FLAGS_TE 0x20 /* all */
144 #define SCI_CTRL_FLAGS_RE 0x10 /* all */
145 #if defined(CONFIG_CPU_SH7750) || \
146 defined(CONFIG_CPU_SH7750R) || \
147 defined(CONFIG_CPU_SH7722) || \
148 defined(CONFIG_CPU_SH7734) || \
149 defined(CONFIG_CPU_SH7750S) || \
150 defined(CONFIG_CPU_SH7751) || \
151 defined(CONFIG_CPU_SH7751R) || \
152 defined(CONFIG_CPU_SH7763) || \
153 defined(CONFIG_CPU_SH7780)
154 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
156 #define SCI_CTRL_FLAGS_REIE 0
158 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
159 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
160 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
161 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
164 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
165 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
166 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
167 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
168 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
169 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
170 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
171 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
173 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
176 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
177 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
178 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
179 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
180 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
181 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
182 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
183 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
185 #if defined(CONFIG_CPU_SH7705) || \
186 defined(CONFIG_CPU_SH7720) || \
187 defined(CONFIG_CPU_SH7721) || \
188 defined(CONFIG_SH73A0) || \
189 defined(CONFIG_R8A7740)
190 # define SCIF_ORER 0x0200
191 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
192 # define SCIF_RFDC_MASK 0x007f
193 # define SCIF_TXROOM_MAX 64
194 #elif defined(CONFIG_CPU_SH7763)
195 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
196 # define SCIF_RFDC_MASK 0x007f
197 # define SCIF_TXROOM_MAX 64
198 /* SH7763 SCIF2 support */
199 # define SCIF2_RFDC_MASK 0x001f
200 # define SCIF2_TXROOM_MAX 16
201 #elif defined(CONFIG_RCAR_GEN2)
202 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
203 # if defined(CONFIG_SCIF_A)
204 # define SCIF_RFDC_MASK 0x007f
206 # define SCIF_RFDC_MASK 0x001f
209 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
210 # define SCIF_RFDC_MASK 0x001f
211 # define SCIF_TXROOM_MAX 16
215 #define SCIF_ORER 0x0000
218 #define SCxSR_TEND(port)\
219 (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
220 #define SCxSR_ERRORS(port)\
221 (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
222 #define SCxSR_RDxF(port)\
223 (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
224 #define SCxSR_TDxE(port)\
225 (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
226 #define SCxSR_FER(port)\
227 (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
228 #define SCxSR_PER(port)\
229 (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
230 #define SCxSR_BRK(port)\
231 ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
232 #define SCxSR_ORER(port)\
233 (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
235 #if defined(CONFIG_CPU_SH7705) || \
236 defined(CONFIG_CPU_SH7720) || \
237 defined(CONFIG_CPU_SH7721) || \
238 defined(CONFIG_SH73A0) || \
239 defined(CONFIG_R8A7740)
240 # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
241 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
242 # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
243 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
245 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
246 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
247 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
248 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
252 #define SCFCR_RFRST 0x0002
253 #define SCFCR_TFRST 0x0004
254 #define SCFCR_TCRST 0x4000
255 #define SCFCR_MCE 0x0008
257 #define SCI_MAJOR 204
258 #define SCI_MINOR_START 8
260 /* Generic serial flags */
261 #define SCI_RX_THROTTLE 0x0000001
263 #define SCI_MAGIC 0xbabeface
266 * Events are used to schedule things to happen at timer-interrupt
267 * time, instead of at rs interrupt time.
269 #define SCI_EVENT_WRITE_WAKEUP 0
271 #define SCI_IN(size, offset)\
273 return readb(port->membase + (offset));\
275 return readw(port->membase + (offset));\
277 #define SCI_OUT(size, offset, value)\
279 writeb(value, port->membase + (offset));\
280 } else if ((size) == 16) {\
281 writew(value, port->membase + (offset));\
284 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
285 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
286 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
287 SCI_IN(scif_size, scif_offset)\
288 } else { /* PORT_SCI or PORT_SCIFA */\
289 SCI_IN(sci_size, sci_offset);\
292 static inline void sci_##name##_out(struct uart_port *port,\
293 unsigned int value) {\
294 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
295 SCI_OUT(scif_size, scif_offset, value)\
296 } else { /* PORT_SCI or PORT_SCIFA */\
297 SCI_OUT(sci_size, sci_offset, value);\
301 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
302 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
303 SCI_IN(scif_size, scif_offset);\
305 static inline void sci_##name##_out(struct uart_port *port,\
306 unsigned int value) {\
307 SCI_OUT(scif_size, scif_offset, value);\
310 #define CPU_SCI_FNS(name, sci_offset, sci_size)\
311 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
312 SCI_IN(sci_size, sci_offset);\
314 static inline void sci_##name##_out(struct uart_port *port,\
315 unsigned int value) {\
316 SCI_OUT(sci_size, sci_offset, value);\
319 #if defined(CONFIG_CPU_SH3) || \
320 defined(CONFIG_SH73A0) || \
321 defined(CONFIG_R8A7740)
322 #if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
323 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
324 sh4_sci_offset, sh4_sci_size, \
325 sh3_scif_offset, sh3_scif_size, \
326 sh4_scif_offset, sh4_scif_size, \
327 h8_sci_offset, h8_sci_size) \
328 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
329 sh4_scif_offset, sh4_scif_size)
330 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
331 sh4_scif_offset, sh4_scif_size) \
332 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
333 #elif defined(CONFIG_CPU_SH7705) || \
334 defined(CONFIG_CPU_SH7720) || \
335 defined(CONFIG_CPU_SH7721) || \
336 defined(CONFIG_SH73A0)
337 #define SCIF_FNS(name, scif_offset, scif_size) \
338 CPU_SCIF_FNS(name, scif_offset, scif_size)
339 #elif defined(CONFIG_R8A7740)
340 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
341 sh4_scifb_offset, sh4_scifb_size) \
342 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
343 sh4_scifb_offset, sh4_scifb_size)
344 #define SCIF_FNS(name, scif_offset, scif_size) \
345 CPU_SCIF_FNS(name, scif_offset, scif_size)
347 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
348 sh4_sci_offset, sh4_sci_size, \
349 sh3_scif_offset, sh3_scif_size,\
350 sh4_scif_offset, sh4_scif_size, \
351 h8_sci_offset, h8_sci_size) \
352 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
353 sh3_scif_offset, sh3_scif_size)
354 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
355 sh4_scif_offset, sh4_scif_size) \
356 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
358 #elif defined(CONFIG_CPU_SH7723)
359 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
360 sh4_scif_offset, sh4_scif_size) \
361 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
362 sh4_scif_offset, sh4_scif_size)
363 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
364 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
366 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
367 sh4_sci_offset, sh4_sci_size, \
368 sh3_scif_offset, sh3_scif_size,\
369 sh4_scif_offset, sh4_scif_size, \
370 h8_sci_offset, h8_sci_size) \
371 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
372 sh4_scif_offset, sh4_scif_size)
373 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \
374 sh4_scif_offset, sh4_scif_size) \
375 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
378 #if defined(CONFIG_CPU_SH7705) || \
379 defined(CONFIG_CPU_SH7720) || \
380 defined(CONFIG_CPU_SH7721) || \
381 defined(CONFIG_SH73A0)
383 SCIF_FNS(SCSMR, 0x00, 16)
384 SCIF_FNS(SCBRR, 0x04, 8)
385 SCIF_FNS(SCSCR, 0x08, 16)
386 SCIF_FNS(SCTDSR, 0x0c, 8)
387 SCIF_FNS(SCFER, 0x10, 16)
388 SCIF_FNS(SCxSR, 0x14, 16)
389 SCIF_FNS(SCFCR, 0x18, 16)
390 SCIF_FNS(SCFDR, 0x1c, 16)
391 SCIF_FNS(SCxTDR, 0x20, 8)
392 SCIF_FNS(SCxRDR, 0x24, 8)
393 SCIF_FNS(SCLSR, 0x00, 0)
394 SCIF_FNS(DL, 0x00, 0) /* dummy */
395 #elif defined(CONFIG_R8A7740)
396 SCIF_FNS(SCSMR, 0x00, 16)
397 SCIF_FNS(SCBRR, 0x04, 8)
398 SCIF_FNS(SCSCR, 0x08, 16)
399 SCIF_FNS(SCTDSR, 0x0c, 16)
400 SCIF_FNS(SCFER, 0x10, 16)
401 SCIF_FNS(SCxSR, 0x14, 16)
402 SCIF_FNS(SCFCR, 0x18, 16)
403 SCIF_FNS(SCFDR, 0x1c, 16)
404 SCIF_FNS(SCTFDR, 0x38, 16)
405 SCIF_FNS(SCRFDR, 0x3c, 16)
406 SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
407 SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
408 SCIF_FNS(SCLSR, 0x00, 0)
409 SCIF_FNS(DL, 0x00, 0) /* dummy */
410 #elif defined(CONFIG_CPU_SH7723)
411 SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
412 SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
413 SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
414 SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
415 SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
416 SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
417 SCIx_FNS(SCSPTR, 0, 0, 0, 0)
418 SCIF_FNS(SCTDSR, 0x0c, 8)
419 SCIF_FNS(SCFER, 0x10, 16)
420 SCIF_FNS(SCFCR, 0x18, 16)
421 SCIF_FNS(SCFDR, 0x1c, 16)
422 SCIF_FNS(SCLSR, 0x24, 16)
423 SCIF_FNS(DL, 0x00, 0) /* dummy */
424 #elif defined(CONFIG_RCAR_GEN2)
425 /* SCIFA and SCIF register offsets and size */
426 SCIx_FNS(SCSMR, 0, 0, 0x00, 16, 0, 0, 0x00, 16, 0, 0)
427 SCIx_FNS(SCBRR, 0, 0, 0x04, 8, 0, 0, 0x04, 8, 0, 0)
428 SCIx_FNS(SCSCR, 0, 0, 0x08, 16, 0, 0, 0x08, 16, 0, 0)
429 SCIx_FNS(SCxTDR, 0, 0, 0x20, 8, 0, 0, 0x0C, 8, 0, 0)
430 SCIx_FNS(SCxSR, 0, 0, 0x14, 16, 0, 0, 0x10, 16, 0, 0)
431 SCIx_FNS(SCxRDR, 0, 0, 0x24, 8, 0, 0, 0x14, 8, 0, 0)
432 SCIF_FNS(SCFCR, 0, 0, 0x18, 16)
433 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
434 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
435 SCIF_FNS(DL, 0, 0, 0x30, 16)
436 SCIF_FNS(CKS, 0, 0, 0x34, 16)
437 #if defined(CONFIG_SCIF_A)
438 SCIF_FNS(SCLSR, 0, 0, 0x14, 16)
440 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
443 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
444 /* name off sz off sz off sz off sz off sz*/
445 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
446 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
447 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
448 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
449 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
450 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
451 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
452 #if defined(CONFIG_CPU_SH7780)
453 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
454 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
455 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
456 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
457 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
458 #elif defined(CONFIG_CPU_SH7763)
459 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
460 SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
461 SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
462 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
463 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
464 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
465 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
468 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
469 #if defined(CONFIG_CPU_SH7722)
470 SCIF_FNS(SCSPTR, 0, 0, 0, 0)
472 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
474 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
476 SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */
478 #define sci_in(port, reg) sci_##reg##_in(port)
479 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
481 #if defined(CONFIG_CPU_SH7706) || \
482 defined(CONFIG_CPU_SH7707) || \
483 defined(CONFIG_CPU_SH7708) || \
484 defined(CONFIG_CPU_SH7709)
485 static inline int sci_rxd_in(struct uart_port *port)
487 if (port->mapbase == 0xfffffe80)
488 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
491 #elif defined(CONFIG_CPU_SH7750) || \
492 defined(CONFIG_CPU_SH7751) || \
493 defined(CONFIG_CPU_SH7751R) || \
494 defined(CONFIG_CPU_SH7750R) || \
495 defined(CONFIG_CPU_SH7750S)
496 static inline int sci_rxd_in(struct uart_port *port)
498 if (port->mapbase == 0xffe00000)
499 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
502 #else /* default case for non-SCI processors */
503 static inline int sci_rxd_in(struct uart_port *port)
510 * Values for the BitRate Register (SCBRR)
512 * The values are actually divisors for a frequency which can
513 * be internal to the SH3 (14.7456MHz) or derived from an external
514 * clock source. This driver assumes the internal clock is used;
515 * to support using an external clock source, config options or
516 * possibly command-line options would need to be added.
518 * Also, to support speeds below 2400 (why?) the lower 2 bits of
519 * the SCSMR register would also need to be set to non-zero values.
521 * -- Greg Banks 27Feb2000
523 * Answer: The SCBRR register is only eight bits, and the value in
524 * it gets larger with lower baud rates. At around 2400 (depending on
525 * the peripherial module clock) you run out of bits. However the
526 * lower two bits of SCSMR allow the module clock to be divided down,
527 * scaling the value which is needed in SCBRR.
529 * -- Stuart Menefy - 23 May 2000
531 * I meant, why would anyone bother with bitrates below 2400.
533 * -- Greg Banks - 7Jul2000
535 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
536 * tape reader as a console!
538 * -- Mitch Davis - 15 Jul 2000
541 #if defined(CONFIG_CPU_SH7780)
542 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
543 #elif defined(CONFIG_CPU_SH7705) || \
544 defined(CONFIG_CPU_SH7720) || \
545 defined(CONFIG_CPU_SH7721) || \
546 defined(CONFIG_SH73A0) || \
547 defined(CONFIG_R8A7740)
548 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
549 #elif defined(CONFIG_CPU_SH7723)
550 static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
552 if (port->type == PORT_SCIF)
553 return (clk+16*bps)/(32*bps)-1;
555 return ((clk*2)+16*bps)/(16*bps)-1;
557 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
558 #elif defined(CONFIG_RCAR_GEN2)
559 #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
560 #if defined(CONFIG_SCIF_A)
561 #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */
563 #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
565 #else /* Generic SH */
566 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
570 #define DL_VALUE(bps, clk) 0