2 * SuperH SCIF device driver.
3 * Copyright (c) 2007,2008 Nobuhiro Iwamatsu
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <asm/processor.h>
23 #if defined(CONFIG_CONS_SCIF0)
24 # define SCIF_BASE SCIF0_BASE
25 #elif defined(CONFIG_CONS_SCIF1)
26 # define SCIF_BASE SCIF1_BASE
27 #elif defined(CONFIG_CONS_SCIF2)
28 # define SCIF_BASE SCIF2_BASE
29 #elif defined(CONFIG_CONS_SCIF3)
30 # define SCIF_BASE SCIF3_BASE
31 #elif defined(CONFIG_CONS_SCIF4)
32 # define SCIF_BASE SCIF4_BASE
33 #elif defined(CONFIG_CONS_SCIF5)
34 # define SCIF_BASE SCIF5_BASE
36 # error "Default SCIF doesn't set....."
40 #define SCSMR (vu_short *)(SCIF_BASE + 0x0)
41 #define SCBRR (vu_char *)(SCIF_BASE + 0x4)
42 #define SCSCR (vu_short *)(SCIF_BASE + 0x8)
43 #define SCFCR (vu_short *)(SCIF_BASE + 0x18)
44 #define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
45 #if defined(CONFIG_CPU_SH7720) || \
46 (defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A))
47 # define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
48 # define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
49 # define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
51 # define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
52 # define SCFSR (vu_short *)(SCIF_BASE + 0x10)
53 # define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
56 #if defined(CONFIG_CPU_SH7780) || \
57 defined(CONFIG_CPU_SH7785)
58 # define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
59 # define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
60 # define SCLSR (vu_short *)(SCIF_BASE + 0x28)
61 # define SCRER (vu_short *)(SCIF_BASE + 0x2C)
63 # define FIFOLEVEL_MASK 0xFF
64 #elif defined(CONFIG_CPU_SH7763)
65 # if defined(CONFIG_CONS_SCIF2)
66 # define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
67 # define SCLSR (vu_short *)(SCIF_BASE + 0x24)
69 # define FIFOLEVEL_MASK 0x1F
71 # define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
72 # define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
73 # define SCLSR (vu_short *)(SCIF_BASE + 0x28)
74 # define SCRER (vu_short *)(SCIF_BASE + 0x2C)
76 # define FIFOLEVEL_MASK 0xFF
78 #elif defined(CONFIG_CPU_SH7723)
79 # if defined(CONFIG_SCIF_A)
81 # define LSR_ORER 0x0200
82 # define FIFOLEVEL_MASK 0x3F
84 # define SCLSR (vu_short *)(SCIF_BASE + 0x24)
86 # define FIFOLEVEL_MASK 0x1F
88 #elif defined(CONFIG_CPU_SH7750) || \
89 defined(CONFIG_CPU_SH7751) || \
90 defined(CONFIG_CPU_SH7722) || \
91 defined(CONFIG_CPU_SH7203)
92 # define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
93 # define SCLSR (vu_short *)(SCIF_BASE + 0x24)
95 # define FIFOLEVEL_MASK 0x1F
96 #elif defined(CONFIG_CPU_SH7720)
98 # define LSR_ORER 0x0200
99 # define FIFOLEVEL_MASK 0x1F
100 #elif defined(CONFIG_CPU_SH7710) || \
101 defined(CONFIG_CPU_SH7712)
102 # define SCLSR SCFSR /* SCSSR */
104 # define FIFOLEVEL_MASK 0x1F
107 /* SCBRR register value setting */
108 #if defined(CONFIG_CPU_SH7720)
109 # define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
110 #elif defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A)
111 /* SH7723 SCIFA use bus clock. So clock *2 */
112 # define SCBRR_VALUE(bps, clk) (((clk*2*2)+16*bps)/(32*bps)-1)
113 #else /* Generic SuperH */
114 # define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
117 #define SCR_RE (1 << 4)
118 #define SCR_TE (1 << 5)
119 #define FCR_RFRST (1 << 1) /* RFCL */
120 #define FCR_TFRST (1 << 2) /* TFCL */
121 #define FSR_DR (1 << 0)
122 #define FSR_RDF (1 << 1)
123 #define FSR_FER (1 << 3)
124 #define FSR_BRK (1 << 4)
125 #define FSR_FER (1 << 3)
126 #define FSR_TEND (1 << 6)
127 #define FSR_ER (1 << 7)
129 /*----------------------------------------------------------------------*/
131 void serial_setbrg(void)
133 DECLARE_GLOBAL_DATA_PTR;
134 *SCBRR = SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ);
137 int serial_init(void)
139 *SCSCR = (SCR_RE | SCR_TE);
142 *SCFCR = (FCR_RFRST | FCR_TFRST);
150 static int serial_rx_fifo_level(void)
153 return (*SCRFDR >> 0) & FIFOLEVEL_MASK;
155 return (*SCFDR >> 0) & FIFOLEVEL_MASK;
159 void serial_raw_putc(const char c)
161 unsigned int fsr_bits_to_clear;
164 if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */
165 fsr_bits_to_clear = FSR_TEND;
171 if (fsr_bits_to_clear != 0)
172 *SCFSR &= ~fsr_bits_to_clear;
175 void serial_putc(const char c)
178 serial_raw_putc('\r');
182 void serial_puts(const char *s)
185 while ((c = *s++) != 0)
189 int serial_tstc(void)
191 return serial_rx_fifo_level() ? 1 : 0;
194 #define FSR_ERR_CLEAR 0x0063
195 #define RDRF_CLEAR 0x00fc
196 void handle_error(void)
200 *SCFSR = FSR_ERR_CLEAR;
205 int serial_getc_check(void)
207 unsigned short status;
211 if (status & (FSR_FER | FSR_ER | FSR_BRK))
213 if (*SCLSR & LSR_ORER)
215 return status & (FSR_DR | FSR_RDF);
218 int serial_getc(void)
220 unsigned short status;
223 while (!serial_getc_check())
231 if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
234 if (*SCLSR & LSR_ORER)